Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3919742

1

T1

9

T2

4

T3

17

full_word

1140189

1

T1

5

T2

3

T3

8

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	5059631	1			T1	14		T2	7		T3	25
auto[TlIntgErrCmd]	99	1			T83	5		T132	1		T134	5
auto[TlIntgErrData]	101	1			T83	8		T132	5		T134	4
auto[TlIntgErrBoth]	100	1			T83	7		T132	4		T134	11

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

764511

1

T1

4

T2

3

T3

1

auto[1]

4295420

1

T1

10

T2

4

T3

24

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	337903	1			T1	2		T3	1		T4	1
auto[TlIntgErrNone]	partial	auto[1]	3581565	1			T1	7		T2	4		T3	16
auto[TlIntgErrNone]	full_word	auto[0]	426473	1			T1	2		T2	3		T4	2
auto[TlIntgErrNone]	full_word	auto[1]	713690	1			T1	3		T3	8		T4	1
auto[TlIntgErrCmd]	partial	auto[0]	33	1			T83	1		T132	1		T162	4
auto[TlIntgErrCmd]	partial	auto[1]	58	1			T83	3		T134	5		T162	1
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T83	1		T166	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T162	2		T166	2		T135	1
auto[TlIntgErrData]	partial	auto[0]	49	1			T83	2		T132	2		T134	1
auto[TlIntgErrData]	partial	auto[1]	38	1			T83	4		T132	2		T134	3
auto[TlIntgErrData]	full_word	auto[0]	9	1			T83	2		T162	1		T166	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T132	1		T162	1		T135	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T83	5		T134	3		T162	4
auto[TlIntgErrBoth]	partial	auto[1]	55	1			T83	2		T132	3		T134	7
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T167	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T132	1		T134	1		T166	1