Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.16	100.00	85.71	97.60		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	160960294	951453	0	0
late_debug_enable_rd_A	160960294	27151	0	0
late_debug_enable_regwen_rd_A	160960294	24361	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160960294	951453	0	0
T8	0	200148	0	0
T18	223312	0	0	0
T20	12744	0	0	0
T24	381740	123420	0	0
T44	0	69729	0	0
T49	0	110485	0	0
T50	0	165316	0	0
T51	0	142364	0	0
T81	0	53444	0	0
T82	0	104	0	0
T83	0	6	0	0
T84	0	13	0	0
T85	546994	0	0	0
T86	6132	0	0	0
T87	313251	0	0	0
T88	63088	0	0	0
T89	198546	0	0	0
T90	4610	0	0	0
T91	25448	0	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160960294	27151	0	0
T81	300933	16776	0	0
T84	17541	28	0	0
T92	257337	130	0	0
T96	9431	6	0	0
T100	11090	2	0	0
T108	9956	2	0	0
T132	51604	38	0	0
T133	0	50	0	0
T134	0	96	0	0
T135	0	79	0	0
T136	4248	0	0	0
T137	416660	0	0	0
T138	2152	0	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160960294	24361	0	0
T81	300933	15300	0	0
T84	17541	27	0	0
T92	257337	128	0	0
T96	9431	13	0	0
T100	11090	1	0	0
T108	9956	8	0	0
T132	51604	38	0	0
T133	0	34	0	0
T134	0	96	0	0
T135	0	99	0	0
T136	4248	0	0	0
T137	416660	0	0	0
T138	2152	0	0	0