SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
94.16 | 100.00 | 85.71 | 97.60 | 100.00 | 87.50 | dut |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
124 | 1 | 1 | |
128 | 1 | 1 | |
168 | 4 | 4 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 245 | 245 | 0 | 0 |
OutputsKnown_A | 84414536 | 84365354 | 0 | 0 |
gen_flops.gen_no_stable_chks.OutputDelay_A | 84414536 | 84363221 | 0 | 735 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 245 | 245 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T28 | 1 | 1 | 0 | 0 |
T32 | 1 | 1 | 0 | 0 |
T34 | 1 | 1 | 0 | 0 |
T35 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 84414536 | 84365354 | 0 | 0 |
T1 | 91062 | 90833 | 0 | 0 |
T2 | 130736 | 130664 | 0 | 0 |
T3 | 81646 | 81589 | 0 | 0 |
T4 | 221812 | 221553 | 0 | 0 |
T9 | 53233 | 53180 | 0 | 0 |
T10 | 727607 | 727476 | 0 | 0 |
T28 | 14636 | 14558 | 0 | 0 |
T32 | 7678 | 7609 | 0 | 0 |
T34 | 9722 | 9660 | 0 | 0 |
T35 | 9016 | 7557 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 84414536 | 84363221 | 0 | 735 |
T1 | 91062 | 90821 | 0 | 3 |
T2 | 130736 | 130661 | 0 | 3 |
T3 | 81646 | 81586 | 0 | 3 |
T4 | 221812 | 221541 | 0 | 3 |
T9 | 53233 | 53177 | 0 | 3 |
T10 | 727607 | 727470 | 0 | 3 |
T28 | 14636 | 14555 | 0 | 3 |
T32 | 7678 | 7606 | 0 | 3 |
T34 | 9722 | 9657 | 0 | 3 |
T35 | 9016 | 7494 | 0 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |