Module Definition
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Module : rv_dm_enable_checker
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.enable_checker 100.00 100.00 100.00



Module Instance : tb.dut.enable_checker

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.16 100.00 85.71 97.60 100.00 87.50 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : rv_dm_enable_checker
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv' or '../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
29 1 1
36 1 1


Assert Coverage for Module : rv_dm_enable_checker
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DebugRequestNeedsDebug_A 84414536 84365354 0 0
MemTLResponseWithoutDebugIsError_A 84414536 84365354 0 0
NdmResetAckNeedsDebug_A 84414536 84365354 0 0
SbaTLRequestNeedsDebug_A 84414536 84365354 0 0


DebugRequestNeedsDebug_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 84414536 84365354 0 0
T1 91062 90833 0 0
T2 130736 130664 0 0
T3 81646 81589 0 0
T4 221812 221553 0 0
T9 53233 53180 0 0
T10 727607 727476 0 0
T28 14636 14558 0 0
T32 7678 7609 0 0
T34 9722 9660 0 0
T35 9016 7557 0 0

MemTLResponseWithoutDebugIsError_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 84414536 84365354 0 0
T1 91062 90833 0 0
T2 130736 130664 0 0
T3 81646 81589 0 0
T4 221812 221553 0 0
T9 53233 53180 0 0
T10 727607 727476 0 0
T28 14636 14558 0 0
T32 7678 7609 0 0
T34 9722 9660 0 0
T35 9016 7557 0 0

NdmResetAckNeedsDebug_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 84414536 84365354 0 0
T1 91062 90833 0 0
T2 130736 130664 0 0
T3 81646 81589 0 0
T4 221812 221553 0 0
T9 53233 53180 0 0
T10 727607 727476 0 0
T28 14636 14558 0 0
T32 7678 7609 0 0
T34 9722 9660 0 0
T35 9016 7557 0 0

SbaTLRequestNeedsDebug_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 84414536 84365354 0 0
T1 91062 90833 0 0
T2 130736 130664 0 0
T3 81646 81589 0 0
T4 221812 221553 0 0
T9 53233 53180 0 0
T10 727607 727476 0 0
T28 14636 14558 0 0
T32 7678 7609 0 0
T34 9722 9660 0 0
T35 9016 7557 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%