Module Definition
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Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_clock_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_rst_n_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_scan.i_dft_tck_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 26077296 26075876 0 0
selKnown1 99563153 99561733 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 26077296 26075876 0 0
T1 20726 20722 0 0
T2 2871 2867 0 0
T3 41940 41936 0 0
T4 20920 20916 0 0
T5 0 8 0 0
T9 11925 11921 0 0
T10 20248 20244 0 0
T25 0 2 0 0
T26 0 10 0 0
T28 1860 1856 0 0
T32 2052 2048 0 0
T33 0 12 0 0
T34 1347 1343 0 0
T35 10757 10753 0 0
T42 0 9 0 0
T58 0 9 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 99563153 99561733 0 0
T1 101428 101424 0 0
T2 132172 132168 0 0
T3 102617 102613 0 0
T4 232276 232272 0 0
T5 0 6 0 0
T9 59196 59192 0 0
T10 737733 737729 0 0
T25 0 2 0 0
T26 0 10 0 0
T28 15567 15563 0 0
T32 8705 8701 0 0
T33 0 8 0 0
T34 10396 10392 0 0
T35 14415 14411 0 0
T42 0 8 0 0
T58 0 8 0 0

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 10928267 10928022 0 0
selKnown1 84414536 84414291 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 10928267 10928022 0 0
T1 10358 10357 0 0
T2 1434 1433 0 0
T3 20969 20968 0 0
T4 10456 10455 0 0
T9 5961 5960 0 0
T10 10122 10121 0 0
T28 929 928 0 0
T32 1025 1024 0 0
T34 672 671 0 0
T35 5357 5356 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 84414536 84414291 0 0
T1 91062 91061 0 0
T2 130736 130735 0 0
T3 81646 81645 0 0
T4 221812 221811 0 0
T9 53233 53232 0 0
T10 727607 727606 0 0
T28 14636 14635 0 0
T32 7678 7677 0 0
T34 9722 9721 0 0
T35 9016 9015 0 0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 771 526 0 0
selKnown1 711 466 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 771 526 0 0
T1 4 3 0 0
T2 1 0 0 0
T3 1 0 0 0
T4 4 3 0 0
T5 0 4 0 0
T9 1 0 0 0
T10 2 1 0 0
T25 0 1 0 0
T26 0 5 0 0
T28 1 0 0 0
T32 1 0 0 0
T33 0 6 0 0
T34 1 0 0 0
T35 21 20 0 0
T42 0 4 0 0
T58 0 4 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 711 466 0 0
T1 4 3 0 0
T2 1 0 0 0
T3 1 0 0 0
T4 4 3 0 0
T5 0 3 0 0
T9 1 0 0 0
T10 2 1 0 0
T25 0 1 0 0
T26 0 5 0 0
T28 1 0 0 0
T32 1 0 0 0
T33 0 4 0 0
T34 1 0 0 0
T35 21 20 0 0
T42 0 4 0 0
T58 0 4 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 15146249 15145784 0 0
selKnown1 15146032 15145567 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 15146249 15145784 0 0
T1 10358 10357 0 0
T2 1435 1434 0 0
T3 20969 20968 0 0
T4 10456 10455 0 0
T9 5962 5961 0 0
T10 10122 10121 0 0
T28 929 928 0 0
T32 1025 1024 0 0
T34 673 672 0 0
T35 5358 5357 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 15146032 15145567 0 0
T1 10358 10357 0 0
T2 1434 1433 0 0
T3 20969 20968 0 0
T4 10456 10455 0 0
T9 5961 5960 0 0
T10 10122 10121 0 0
T28 929 928 0 0
T32 1025 1024 0 0
T34 672 671 0 0
T35 5357 5356 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 2009 1544 0 0
selKnown1 1874 1409 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 2009 1544 0 0
T1 6 5 0 0
T2 1 0 0 0
T3 1 0 0 0
T4 4 3 0 0
T5 0 4 0 0
T9 1 0 0 0
T10 2 1 0 0
T25 0 1 0 0
T26 0 5 0 0
T28 1 0 0 0
T32 1 0 0 0
T33 0 6 0 0
T34 1 0 0 0
T35 21 20 0 0
T42 0 5 0 0
T58 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1874 1409 0 0
T1 4 3 0 0
T2 1 0 0 0
T3 1 0 0 0
T4 4 3 0 0
T5 0 3 0 0
T9 1 0 0 0
T10 2 1 0 0
T25 0 1 0 0
T26 0 5 0 0
T28 1 0 0 0
T32 1 0 0 0
T33 0 4 0 0
T34 1 0 0 0
T35 21 20 0 0
T42 0 4 0 0
T58 0 4 0 0

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