Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	661766	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

944700

1

T4

32194

T8

2

T25

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	526521	1			T4	9645		T8	1		T25	1
values[0x0]	337514	1			T4	14811		T8	1		T25	1
values[0x1]	742431	1			T4	41473		T5	197013		T6	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	306326	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1300140

1

T4

53617

T8

2

T25

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6063	1			T4	267		T5	1160		T12	1187
valid_sources[0x01]	6187	1			T4	237		T5	1190		T6	2
valid_sources[0x02]	7440	1			T4	292		T5	1220		T12	1186
valid_sources[0x03]	7075	1			T4	389		T5	1196		T12	1198
valid_sources[0x04]	6256	1			T4	278		T5	1159		T12	1200
valid_sources[0x05]	5880	1			T4	178		T5	1172		T12	1246
valid_sources[0x06]	6148	1			T4	172		T5	1175		T12	1153
valid_sources[0x07]	6379	1			T4	296		T5	1131		T12	1244
valid_sources[0x08]	5663	1			T4	235		T5	1215		T12	1218
valid_sources[0x09]	6753	1			T4	339		T5	1193		T12	1237
valid_sources[0x0a]	5762	1			T4	254		T5	1152		T35	11
valid_sources[0x0b]	6050	1			T4	284		T5	1163		T12	1231
valid_sources[0x0c]	6424	1			T4	324		T5	1147		T12	1202
valid_sources[0x0d]	6256	1			T4	338		T5	1156		T12	1256
valid_sources[0x0e]	6799	1			T4	249		T5	1185		T12	1251
valid_sources[0x0f]	6761	1			T4	250		T5	1125		T12	1222
valid_sources[0x10]	5411	1			T4	230		T5	1219		T12	1155
valid_sources[0x11]	6239	1			T4	295		T5	1153		T12	1216
valid_sources[0x12]	6888	1			T4	252		T5	1175		T12	1241
valid_sources[0x13]	6426	1			T4	357		T5	1216		T12	1208
valid_sources[0x14]	6442	1			T4	207		T5	1228		T12	1224
valid_sources[0x15]	6255	1			T4	195		T5	1213		T12	1291
valid_sources[0x16]	6717	1			T4	243		T5	1198		T12	1204
valid_sources[0x17]	6062	1			T4	284		T5	1176		T12	1215
valid_sources[0x18]	6109	1			T4	208		T5	1244		T12	1186
valid_sources[0x19]	6011	1			T4	206		T5	1114		T147	1
valid_sources[0x1a]	5922	1			T4	215		T5	1213		T12	1190
valid_sources[0x1b]	6159	1			T4	216		T5	1163		T12	1228
valid_sources[0x1c]	6200	1			T4	279		T5	1238		T12	1156
valid_sources[0x1d]	7251	1			T4	268		T5	1199		T12	1214
valid_sources[0x1e]	5611	1			T4	175		T5	1210		T18	1
valid_sources[0x1f]	6295	1			T4	245		T5	1200		T12	1218
valid_sources[0x20]	6136	1			T4	263		T5	1188		T12	1242
valid_sources[0x21]	6037	1			T4	264		T5	1212		T12	1256
valid_sources[0x22]	7270	1			T4	240		T5	1219		T10	1
valid_sources[0x23]	6292	1			T4	283		T5	1203		T12	1206
valid_sources[0x24]	7321	1			T4	268		T5	1198		T12	1228
valid_sources[0x25]	6413	1			T4	180		T5	1250		T12	1229
valid_sources[0x26]	6380	1			T4	164		T5	1248		T12	1295
valid_sources[0x27]	5566	1			T4	271		T5	1141		T34	1
valid_sources[0x28]	5973	1			T4	300		T5	1209		T12	1189
valid_sources[0x29]	6281	1			T4	206		T5	1213		T12	1209
valid_sources[0x2a]	6155	1			T4	289		T5	1233		T12	1228
valid_sources[0x2b]	6042	1			T4	274		T5	1227		T12	1190
valid_sources[0x2c]	5746	1			T4	201		T5	1208		T12	1258
valid_sources[0x2d]	6116	1			T4	271		T5	1205		T12	1185
valid_sources[0x2e]	6047	1			T4	259		T5	1174		T147	2
valid_sources[0x2f]	6210	1			T4	436		T5	1174		T12	1197
valid_sources[0x30]	5868	1			T4	266		T5	1117		T12	1197
valid_sources[0x31]	6680	1			T4	162		T5	1139		T10	1
valid_sources[0x32]	5882	1			T4	276		T5	1204		T12	1229
valid_sources[0x33]	6431	1			T4	460		T5	1281		T12	1134
valid_sources[0x34]	6198	1			T4	276		T5	1185		T11	1
valid_sources[0x35]	6663	1			T4	149		T5	1181		T6	1
valid_sources[0x36]	6282	1			T4	255		T5	1195		T12	1186
valid_sources[0x37]	6586	1			T4	241		T5	1251		T12	1215
valid_sources[0x38]	6167	1			T4	317		T5	1189		T12	1215
valid_sources[0x39]	6030	1			T4	223		T5	1245		T12	1239
valid_sources[0x3a]	6551	1			T4	216		T5	1145		T12	1158
valid_sources[0x3b]	7675	1			T4	359		T5	1195		T147	1
valid_sources[0x3c]	6437	1			T4	349		T5	1149		T12	1230
valid_sources[0x3d]	7287	1			T4	241		T5	1165		T11	1
valid_sources[0x3e]	6222	1			T4	232		T5	1178		T12	1221
valid_sources[0x3f]	5711	1			T4	321		T5	1123		T12	1171
valid_sources[0x40]	5971	1			T4	192		T5	1188		T12	1213
valid_sources[0x41]	5735	1			T4	217		T5	1187		T11	2
valid_sources[0x42]	5275	1			T4	134		T5	1118		T12	1194
valid_sources[0x43]	7859	1			T4	293		T5	1180		T12	1243
valid_sources[0x44]	5888	1			T4	362		T5	1188		T24	1
valid_sources[0x45]	6455	1			T4	275		T5	1182		T6	1
valid_sources[0x46]	5947	1			T4	291		T5	1137		T12	1170
valid_sources[0x47]	6679	1			T4	314		T5	1290		T12	1246
valid_sources[0x48]	6120	1			T4	275		T5	1221		T12	1190
valid_sources[0x49]	6684	1			T4	392		T5	1282		T12	1227
valid_sources[0x4a]	6137	1			T4	313		T5	1175		T10	1
valid_sources[0x4b]	7017	1			T4	176		T5	1260		T12	1194
valid_sources[0x4c]	6314	1			T4	220		T5	1140		T12	1253
valid_sources[0x4d]	6025	1			T4	225		T5	1200		T12	1213
valid_sources[0x4e]	6211	1			T4	314		T5	1204		T12	1270
valid_sources[0x4f]	6210	1			T4	246		T5	1152		T6	1
valid_sources[0x50]	6160	1			T4	246		T25	2		T5	1153
valid_sources[0x51]	6361	1			T4	285		T5	1183		T12	1274
valid_sources[0x52]	6279	1			T4	293		T5	1201		T13	2
valid_sources[0x53]	5812	1			T4	208		T5	1189		T12	1179
valid_sources[0x54]	6854	1			T4	247		T5	1131		T12	1198
valid_sources[0x55]	5215	1			T4	136		T5	1177		T12	1236
valid_sources[0x56]	6918	1			T4	317		T5	1170		T147	1
valid_sources[0x57]	6181	1			T4	293		T5	1238		T12	1203
valid_sources[0x58]	6484	1			T4	271		T5	1223		T12	1288
valid_sources[0x59]	5502	1			T4	257		T5	1172		T12	1181
valid_sources[0x5a]	6621	1			T4	266		T5	1221		T12	1254
valid_sources[0x5b]	5975	1			T4	207		T5	1166		T12	1182
valid_sources[0x5c]	5950	1			T4	338		T5	1193		T12	1250
valid_sources[0x5d]	5764	1			T4	288		T5	1209		T12	1182
valid_sources[0x5e]	6151	1			T4	277		T5	1215		T12	1234
valid_sources[0x5f]	6172	1			T4	337		T5	1221		T11	3
valid_sources[0x60]	6253	1			T4	219		T5	1176		T12	1196
valid_sources[0x61]	5884	1			T4	224		T5	1159		T11	2
valid_sources[0x62]	8230	1			T4	287		T5	1202		T12	1280
valid_sources[0x63]	6142	1			T4	223		T5	1178		T6	2
valid_sources[0x64]	6042	1			T4	244		T5	1225		T12	1250
valid_sources[0x65]	6787	1			T4	240		T5	1117		T6	1
valid_sources[0x66]	5935	1			T4	246		T5	1172		T12	1169
valid_sources[0x67]	6528	1			T4	304		T5	1150		T12	1160
valid_sources[0x68]	5990	1			T4	235		T5	1285		T12	1199
valid_sources[0x69]	6270	1			T4	203		T5	1212		T12	1215
valid_sources[0x6a]	5875	1			T4	211		T5	1220		T12	1186
valid_sources[0x6b]	6363	1			T4	264		T5	1200		T12	1239
valid_sources[0x6c]	5903	1			T4	185		T5	1216		T12	1211
valid_sources[0x6d]	5826	1			T4	324		T5	1188		T12	1230
valid_sources[0x6e]	6552	1			T4	266		T5	1183		T43	2
valid_sources[0x6f]	6091	1			T4	182		T5	1269		T12	1234
valid_sources[0x70]	6751	1			T4	275		T5	1172		T12	1257
valid_sources[0x71]	5730	1			T4	276		T5	1134		T12	1139
valid_sources[0x72]	7279	1			T4	200		T5	1208		T12	1209
valid_sources[0x73]	6230	1			T4	249		T5	1173		T13	3
valid_sources[0x74]	6366	1			T4	173		T5	1166		T6	1
valid_sources[0x75]	5679	1			T4	210		T5	1171		T12	1228
valid_sources[0x76]	6018	1			T4	286		T5	1260		T12	1258
valid_sources[0x77]	5890	1			T4	291		T5	1110		T12	1244
valid_sources[0x78]	5967	1			T4	254		T5	1154		T12	1253
valid_sources[0x79]	5907	1			T4	138		T5	1240		T13	1
valid_sources[0x7a]	6466	1			T4	251		T5	1211		T12	1230
valid_sources[0x7b]	7244	1			T4	264		T5	1176		T6	1
valid_sources[0x7c]	6164	1			T4	308		T5	1112		T6	1
valid_sources[0x7d]	6357	1			T4	208		T5	1143		T12	1184
valid_sources[0x7e]	6170	1			T4	300		T5	1238		T12	1222
valid_sources[0x7f]	5996	1			T4	203		T5	1148		T12	1237
valid_sources[0x80]	6847	1			T4	220		T5	1141		T12	1210

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

360715

1

T4

8599

T8

1

T5

36704

values[0x0]

all_enables

biggest_size

292191

1

T4

11919

T8

1

T25

1

values[0x1]

all_enables

biggest_size

291794

1

T4

11676

T5

53843

T6

3

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	31821	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

688290

1

T7

1

T1

1

T2

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	185837	1			T4	11353		T5	56988		T12	57230
values[0x0]	260486	1			T7	1		T1	1		T2	1
values[0x1]	273788	1			T27	9		T4	17145		T28	9

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	17118	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

702993

1

T7

1

T1

1

T2

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2714	1			T4	148		T5	955		T12	711
valid_sources[0x01]	2794	1			T4	161		T5	993		T12	732
valid_sources[0x02]	2178	1			T4	180		T25	1		T5	835
valid_sources[0x03]	3030	1			T4	187		T5	988		T176	1
valid_sources[0x04]	2539	1			T4	162		T5	1036		T12	478
valid_sources[0x05]	2654	1			T4	180		T5	844		T12	739
valid_sources[0x06]	2929	1			T4	160		T39	1		T5	812
valid_sources[0x07]	2381	1			T4	194		T39	1		T5	882
valid_sources[0x08]	2768	1			T4	177		T5	845		T177	1
valid_sources[0x09]	2258	1			T4	202		T5	821		T12	319
valid_sources[0x0a]	3525	1			T27	6		T4	186		T5	789
valid_sources[0x0b]	3199	1			T4	182		T5	978		T12	998
valid_sources[0x0c]	3601	1			T4	204		T5	791		T12	1791
valid_sources[0x0d]	2635	1			T4	177		T5	823		T47	1
valid_sources[0x0e]	3070	1			T4	178		T5	1043		T12	985
valid_sources[0x0f]	2710	1			T4	185		T5	857		T178	1
valid_sources[0x10]	2565	1			T4	185		T5	945		T179	4
valid_sources[0x11]	2681	1			T4	189		T5	736		T12	810
valid_sources[0x12]	3207	1			T27	1		T4	188		T5	872
valid_sources[0x13]	2733	1			T4	167		T5	904		T12	747
valid_sources[0x14]	2831	1			T4	185		T5	827		T43	1
valid_sources[0x15]	2591	1			T4	185		T5	830		T9	1
valid_sources[0x16]	3372	1			T4	165		T5	901		T12	1466
valid_sources[0x17]	2790	1			T4	191		T28	1		T5	929
valid_sources[0x18]	3648	1			T4	185		T5	813		T12	1773
valid_sources[0x19]	2603	1			T4	169		T5	908		T12	583
valid_sources[0x1a]	2357	1			T4	144		T5	683		T12	703
valid_sources[0x1b]	1804	1			T4	187		T5	720		T12	77
valid_sources[0x1c]	2698	1			T4	169		T5	1005		T12	419
valid_sources[0x1d]	2326	1			T4	168		T5	879		T12	433
valid_sources[0x1e]	2927	1			T4	188		T28	1		T5	909
valid_sources[0x1f]	2680	1			T4	206		T5	898		T12	745
valid_sources[0x20]	2575	1			T4	160		T5	820		T47	1
valid_sources[0x21]	2711	1			T3	1		T4	173		T5	745
valid_sources[0x22]	2872	1			T4	178		T5	1179		T12	650
valid_sources[0x23]	2994	1			T4	175		T5	937		T180	1
valid_sources[0x24]	2885	1			T4	155		T28	1		T39	2
valid_sources[0x25]	2985	1			T4	187		T28	1		T5	704
valid_sources[0x26]	3331	1			T4	176		T5	717		T12	1582
valid_sources[0x27]	2801	1			T4	203		T5	915		T12	837
valid_sources[0x28]	2833	1			T4	156		T5	1080		T11	1
valid_sources[0x29]	2674	1			T4	175		T5	774		T114	4
valid_sources[0x2a]	2566	1			T4	168		T5	777		T22	1
valid_sources[0x2b]	2735	1			T4	167		T5	734		T12	922
valid_sources[0x2c]	3040	1			T27	1		T4	203		T5	868
valid_sources[0x2d]	2767	1			T4	162		T5	944		T47	1
valid_sources[0x2e]	3670	1			T4	177		T5	865		T13	1
valid_sources[0x2f]	3017	1			T4	174		T5	1149		T43	1
valid_sources[0x30]	2625	1			T4	153		T5	950		T12	612
valid_sources[0x31]	3021	1			T4	164		T5	810		T52	1
valid_sources[0x32]	2852	1			T4	190		T46	1		T5	954
valid_sources[0x33]	2921	1			T4	170		T5	787		T12	1168
valid_sources[0x34]	3264	1			T4	174		T5	722		T180	1
valid_sources[0x35]	3062	1			T27	2		T4	140		T5	807
valid_sources[0x36]	2733	1			T4	161		T5	948		T12	787
valid_sources[0x37]	2287	1			T4	180		T5	905		T12	375
valid_sources[0x38]	2199	1			T4	181		T5	608		T12	531
valid_sources[0x39]	3237	1			T4	181		T28	1		T5	853
valid_sources[0x3a]	2940	1			T27	1		T4	172		T5	923
valid_sources[0x3b]	2750	1			T4	180		T5	789		T12	938
valid_sources[0x3c]	4349	1			T4	147		T21	1		T5	878
valid_sources[0x3d]	3860	1			T2	1		T4	156		T5	917
valid_sources[0x3e]	2862	1			T4	135		T5	1045		T18	1
valid_sources[0x3f]	3076	1			T4	176		T5	1017		T12	974
valid_sources[0x40]	2344	1			T4	176		T5	818		T12	512
valid_sources[0x41]	3407	1			T4	168		T5	1115		T12	1385
valid_sources[0x42]	3149	1			T4	153		T21	3		T5	960
valid_sources[0x43]	2417	1			T4	163		T21	2		T5	766
valid_sources[0x44]	3321	1			T4	159		T5	997		T12	1147
valid_sources[0x45]	3015	1			T4	195		T5	935		T12	1029
valid_sources[0x46]	2665	1			T4	180		T5	987		T44	2
valid_sources[0x47]	3195	1			T4	179		T5	759		T47	1
valid_sources[0x48]	2853	1			T27	1		T4	161		T5	793
valid_sources[0x49]	3137	1			T4	170		T5	833		T180	1
valid_sources[0x4a]	2552	1			T4	156		T5	903		T180	1
valid_sources[0x4b]	2632	1			T4	160		T5	692		T12	830
valid_sources[0x4c]	2405	1			T4	183		T5	888		T10	3
valid_sources[0x4d]	2404	1			T4	168		T5	791		T12	626
valid_sources[0x4e]	3010	1			T4	212		T5	850		T52	1
valid_sources[0x4f]	2799	1			T4	172		T5	920		T12	694
valid_sources[0x50]	3111	1			T4	144		T5	958		T12	1173
valid_sources[0x51]	2759	1			T4	160		T5	878		T181	3
valid_sources[0x52]	3599	1			T4	204		T5	903		T180	1
valid_sources[0x53]	3389	1			T4	181		T5	937		T12	1477
valid_sources[0x54]	3574	1			T4	186		T5	981		T12	1536
valid_sources[0x55]	2806	1			T4	147		T5	913		T9	1
valid_sources[0x56]	2337	1			T4	177		T5	814		T26	1
valid_sources[0x57]	2341	1			T4	172		T5	718		T12	634
valid_sources[0x58]	2779	1			T4	153		T5	839		T9	1
valid_sources[0x59]	2239	1			T4	174		T28	1		T5	869
valid_sources[0x5a]	2830	1			T4	171		T5	1049		T12	773
valid_sources[0x5b]	2954	1			T4	197		T5	896		T12	964
valid_sources[0x5c]	3122	1			T4	175		T5	783		T12	1338
valid_sources[0x5d]	2929	1			T7	1		T4	165		T28	1
valid_sources[0x5e]	2925	1			T4	199		T5	921		T12	806
valid_sources[0x5f]	3577	1			T4	153		T5	1009		T12	1483
valid_sources[0x60]	2553	1			T4	174		T5	733		T47	1
valid_sources[0x61]	2645	1			T4	198		T5	908		T12	331
valid_sources[0x62]	3047	1			T4	160		T5	847		T12	1024
valid_sources[0x63]	3090	1			T4	157		T5	935		T12	1171
valid_sources[0x64]	2826	1			T4	186		T5	864		T52	1
valid_sources[0x65]	3069	1			T4	195		T5	956		T12	1050
valid_sources[0x66]	2589	1			T4	151		T5	775		T9	1
valid_sources[0x67]	2789	1			T4	162		T5	1121		T12	694
valid_sources[0x68]	2839	1			T4	169		T5	996		T12	792
valid_sources[0x69]	2483	1			T4	213		T5	755		T114	3
valid_sources[0x6a]	2821	1			T4	176		T5	785		T12	1025
valid_sources[0x6b]	2715	1			T4	181		T5	1005		T52	1
valid_sources[0x6c]	2499	1			T4	166		T5	845		T12	489
valid_sources[0x6d]	2951	1			T4	174		T5	1166		T12	756
valid_sources[0x6e]	2624	1			T4	169		T5	927		T12	525
valid_sources[0x6f]	2630	1			T4	150		T5	1044		T12	592
valid_sources[0x70]	2783	1			T4	178		T5	939		T12	872
valid_sources[0x71]	2132	1			T4	160		T39	1		T5	810
valid_sources[0x72]	2809	1			T4	177		T5	861		T182	1
valid_sources[0x73]	2537	1			T4	159		T28	1		T5	866
valid_sources[0x74]	2800	1			T4	168		T5	872		T52	1
valid_sources[0x75]	3294	1			T4	165		T5	784		T12	1471
valid_sources[0x76]	3043	1			T4	183		T28	1		T5	719
valid_sources[0x77]	2836	1			T4	170		T5	817		T12	880
valid_sources[0x78]	2832	1			T4	167		T5	808		T12	997
valid_sources[0x79]	3003	1			T4	170		T5	989		T45	1
valid_sources[0x7a]	2654	1			T4	190		T28	1		T5	854
valid_sources[0x7b]	3208	1			T4	150		T5	979		T12	1246
valid_sources[0x7c]	3080	1			T4	181		T5	833		T12	1033
valid_sources[0x7d]	2398	1			T4	152		T5	793		T12	563
valid_sources[0x7e]	2714	1			T4	180		T5	1221		T12	541
valid_sources[0x7f]	3310	1			T4	208		T5	746		T12	1503
valid_sources[0x80]	2648	1			T4	165		T5	1014		T177	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

173444

1

T4

10727

T5

53716

T12

54001

values[0x0]

all_enables

biggest_size

257711

1

T7

1

T1

1

T2

1

values[0x1]

all_enables

biggest_size

257135

1

T27

2

T4

16143

T28

1