SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[rv_dm_mem_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[rv_dm_regs_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 3576327 | 1 | T4 | 193764 | T8 | 2 | T25 | 2 | ||||
auto[1] | 1292182 | 1 | T4 | 84052 | T5 | 415195 | T12 | 416321 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 4868325 | 1 | T4 | 277816 | T8 | 2 | T25 | 2 | ||||
values[1] | 22 | 1 | T76 | 1 | T119 | 3 | T122 | 1 | ||||
values[2] | 7 | 1 | T124 | 1 | T123 | 1 | T163 | 1 | ||||
values[3] | 86 | 1 | T76 | 5 | T119 | 4 | T124 | 9 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 4868309 | 1 | T4 | 277816 | T8 | 2 | T25 | 2 | ||||
values[1] | 20 | 1 | T76 | 3 | T124 | 1 | T122 | 3 | ||||
values[2] | 7 | 1 | T119 | 2 | T122 | 1 | T164 | 3 | ||||
values[3] | 94 | 1 | T76 | 5 | T119 | 5 | T124 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 4868209 | 1 | T4 | 277816 | T8 | 2 | T25 | 2 | ||||
auto[TlIntgErrCmd] | 100 | 1 | T76 | 7 | T119 | 8 | T124 | 9 | ||||
auto[TlIntgErrData] | 116 | 1 | T76 | 11 | T119 | 8 | T124 | 7 | ||||
auto[TlIntgErrBoth] | 84 | 1 | T76 | 2 | T119 | 4 | T124 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[0] | 2002440 | 0 | T7 | 1 | T1 | 1 | T2 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 2002241 | 1 | T7 | 1 | T1 | 1 | T2 | 1 | ||||
values[1] | 23 | 1 | T76 | 3 | T119 | 1 | T124 | 1 | ||||
values[2] | 4 | 1 | T165 | 1 | T166 | 1 | T167 | 2 | ||||
values[3] | 90 | 1 | T76 | 7 | T119 | 10 | T124 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 2002236 | 1 | T7 | 1 | T1 | 1 | T2 | 1 | ||||
values[1] | 11 | 1 | T76 | 1 | T122 | 1 | T123 | 2 | ||||
values[2] | 3 | 1 | T168 | 1 | T169 | 2 | - | - | ||||
values[3] | 118 | 1 | T76 | 3 | T119 | 6 | T124 | 12 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 2002140 | 1 | T7 | 1 | T1 | 1 | T2 | 1 | ||||
auto[TlIntgErrCmd] | 96 | 1 | T76 | 9 | T119 | 8 | T124 | 4 | ||||
auto[TlIntgErrData] | 101 | 1 | T76 | 5 | T119 | 3 | T124 | 7 | ||||
auto[TlIntgErrBoth] | 103 | 1 | T76 | 6 | T119 | 9 | T124 | 9 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |