Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3813699

1

T4

238786

T25

1

T5

116542

full_word

1054810

1

T4

39030

T8

2

T25

1

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4868209	1			T4	277816		T8	2		T25	2
auto[TlIntgErrCmd]	100	1			T76	7		T119	8		T124	9
auto[TlIntgErrData]	116	1			T76	11		T119	8		T124	7
auto[TlIntgErrBoth]	84	1			T76	2		T119	4		T124	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

659552

1

T4

18036

T8

1

T25

1

auto[1]

4208957

1

T4

259780

T8

1

T25

1

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	285541	1			T4	8660		T25	1		T5	41135
auto[TlIntgErrNone]	partial	auto[1]	3527880	1			T4	230126		T5	112429		T6	9
auto[TlIntgErrNone]	full_word	auto[0]	373868	1			T4	9376		T8	1		T5	40911
auto[TlIntgErrNone]	full_word	auto[1]	680920	1			T4	29654		T8	1		T25	1
auto[TlIntgErrCmd]	partial	auto[0]	38	1			T76	2		T119	5		T124	3
auto[TlIntgErrCmd]	partial	auto[1]	56	1			T76	4		T119	1		T124	5
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T119	1		T124	1		T123	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T76	1		T119	1		-	-
auto[TlIntgErrData]	partial	auto[0]	63	1			T76	6		T119	2		T124	5
auto[TlIntgErrData]	partial	auto[1]	45	1			T76	4		T119	6		T124	2
auto[TlIntgErrData]	full_word	auto[0]	3	1			T76	1		T169	2		-	-
auto[TlIntgErrData]	full_word	auto[1]	5	1			T122	1		T170	2		T171	1
auto[TlIntgErrBoth]	partial	auto[0]	33	1			T119	1		T124	2		T122	3
auto[TlIntgErrBoth]	partial	auto[1]	43	1			T76	2		T119	3		T124	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T124	1		T123	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T170	1		T172	1		T168	1