Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.16	100.00	85.71	97.60		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	173833201	950818	0	0
late_debug_enable_rd_A	173833201	22242	0	0
late_debug_enable_regwen_rd_A	173833201	19986	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173833201	950818	0	0
T4	383403	59684	0	0
T5	931247	305035	0	0
T6	81549	0	0	0
T8	4529	0	0	0
T12	0	306203	0	0
T17	0	134091	0	0
T21	67896	0	0	0
T25	3770	0	0	0
T28	2076	0	0	0
T39	2271	0	0	0
T46	468641	0	0	0
T47	6009	0	0	0
T48	0	48440	0	0
T74	0	28700	0	0
T75	0	14832	0	0
T76	0	4	0	0
T77	0	48	0	0
T78	0	703	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173833201	22242	0	0
T4	383403	20137	0	0
T5	931247	0	0	0
T6	81549	0	0	0
T8	4529	0	0	0
T21	67896	0	0	0
T25	3770	0	0	0
T28	2076	0	0	0
T39	2271	0	0	0
T46	468641	0	0	0
T47	6009	0	0	0
T77	0	56	0	0
T83	0	13	0	0
T84	0	9	0	0
T87	0	17	0	0
T119	0	26	0	0
T120	0	276	0	0
T121	0	20	0	0
T122	0	84	0	0
T123	0	68	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173833201	19986	0	0
T4	383403	17148	0	0
T5	931247	0	0	0
T6	81549	0	0	0
T8	4529	0	0	0
T21	67896	0	0	0
T25	3770	0	0	0
T28	2076	0	0	0
T39	2271	0	0	0
T46	468641	0	0	0
T47	6009	0	0	0
T77	0	55	0	0
T83	0	4	0	0
T84	0	4	0	0
T87	0	38	0	0
T119	0	37	0	0
T120	0	172	0	0
T121	0	16	0	0
T122	0	88	0	0
T123	0	97	0	0