Toggle Coverage for Module :
prim_onehot_check
| Total | Covered | Percent |
Totals |
5 |
5 |
100.00 |
Total Bits |
14 |
14 |
100.00 |
Total Bits 0->1 |
7 |
7 |
100.00 |
Total Bits 1->0 |
7 |
7 |
100.00 |
| | | |
Ports |
5 |
5 |
100.00 |
Port Bits |
14 |
14 |
100.00 |
Port Bits 0->1 |
7 |
7 |
100.00 |
Port Bits 1->0 |
7 |
7 |
100.00 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T7,T1,T2 |
Yes |
T7,T1,T2 |
INPUT |
rst_ni |
Yes |
Yes |
T4,T21,T5 |
Yes |
T7,T1,T2 |
INPUT |
oh_i[2:0] |
Yes |
Yes |
T27,T28,T39 |
Yes |
T27,T28,T39 |
INPUT |
addr_i[1:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
en_i |
Yes |
Yes |
T7,T1,T2 |
Yes |
T7,T1,T2 |
INPUT |
err_o |
Yes |
Yes |
T40,T41,T42 |
Yes |
T40,T41,T42 |
OUTPUT |