Line Coverage for Module :
prim_generic_clock_mux2
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Module :
prim_generic_clock_mux2
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T7,T1,T2 |
0 | 1 | Covered | T7,T1,T2 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T1,T2 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T7,T1,T2 |
1 | 1 | Covered | T7,T1,T2 |
Assert Coverage for Module :
prim_generic_clock_mux2
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
13666563 |
13665143 |
0 |
0 |
selKnown1 |
100718312 |
100716892 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
13666563 |
13665143 |
0 |
0 |
T1 |
28371 |
28369 |
0 |
0 |
T2 |
30950 |
30948 |
0 |
0 |
T3 |
32007 |
32005 |
0 |
0 |
T4 |
295254 |
295250 |
0 |
0 |
T5 |
21 |
19 |
0 |
0 |
T6 |
6 |
4 |
0 |
0 |
T7 |
11837 |
11835 |
0 |
0 |
T8 |
2009 |
2005 |
0 |
0 |
T18 |
0 |
8 |
0 |
0 |
T21 |
51171 |
51167 |
0 |
0 |
T24 |
0 |
9 |
0 |
0 |
T25 |
2071 |
2067 |
0 |
0 |
T26 |
0 |
8 |
0 |
0 |
T27 |
372 |
370 |
0 |
0 |
T28 |
773 |
769 |
0 |
0 |
T39 |
2 |
0 |
0 |
0 |
T43 |
0 |
10 |
0 |
0 |
T44 |
0 |
10 |
0 |
0 |
T45 |
0 |
12 |
0 |
0 |
T46 |
2 |
0 |
0 |
0 |
T47 |
2 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
100718312 |
100716892 |
0 |
0 |
T1 |
83175 |
83173 |
0 |
0 |
T2 |
133184 |
133182 |
0 |
0 |
T3 |
156343 |
156341 |
0 |
0 |
T4 |
531031 |
531028 |
0 |
0 |
T5 |
20 |
18 |
0 |
0 |
T6 |
6 |
4 |
0 |
0 |
T7 |
59499 |
59497 |
0 |
0 |
T8 |
5534 |
5530 |
0 |
0 |
T18 |
0 |
6 |
0 |
0 |
T21 |
93488 |
93484 |
0 |
0 |
T24 |
0 |
4 |
0 |
0 |
T25 |
4806 |
4802 |
0 |
0 |
T26 |
0 |
8 |
0 |
0 |
T27 |
9071 |
9069 |
0 |
0 |
T28 |
2463 |
2459 |
0 |
0 |
T39 |
2 |
0 |
0 |
0 |
T43 |
0 |
8 |
0 |
0 |
T44 |
0 |
10 |
0 |
0 |
T45 |
0 |
12 |
0 |
0 |
T46 |
2 |
0 |
0 |
0 |
T47 |
2 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T7,T1,T2 |
0 | 1 | Covered | T7,T1,T2 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T1,T2 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T7,T1,T2 |
1 | 1 | Covered | T7,T1,T2 |
Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
4918882 |
4918637 |
0 |
0 |
selKnown1 |
91971020 |
91970775 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
4918882 |
4918637 |
0 |
0 |
T1 |
14185 |
14184 |
0 |
0 |
T2 |
15475 |
15474 |
0 |
0 |
T3 |
16003 |
16002 |
0 |
0 |
T4 |
147616 |
147615 |
0 |
0 |
T7 |
5918 |
5917 |
0 |
0 |
T8 |
1003 |
1002 |
0 |
0 |
T21 |
25578 |
25577 |
0 |
0 |
T25 |
1034 |
1033 |
0 |
0 |
T27 |
186 |
185 |
0 |
0 |
T28 |
385 |
384 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
91971020 |
91970775 |
0 |
0 |
T1 |
68990 |
68989 |
0 |
0 |
T2 |
117709 |
117708 |
0 |
0 |
T3 |
140340 |
140339 |
0 |
0 |
T4 |
383403 |
383403 |
0 |
0 |
T7 |
53581 |
53580 |
0 |
0 |
T8 |
4529 |
4528 |
0 |
0 |
T21 |
67896 |
67895 |
0 |
0 |
T25 |
3770 |
3769 |
0 |
0 |
T27 |
8885 |
8884 |
0 |
0 |
T28 |
2076 |
2075 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T7,T1,T2 |
0 | 1 | Covered | T7,T1,T2 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T1,T2 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T7,T1,T2 |
1 | 1 | Covered | T7,T1,T2 |
Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
726 |
481 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
3 |
2 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T18 |
0 |
4 |
0 |
0 |
T21 |
7 |
6 |
0 |
0 |
T24 |
0 |
4 |
0 |
0 |
T25 |
1 |
0 |
0 |
0 |
T26 |
0 |
4 |
0 |
0 |
T28 |
1 |
0 |
0 |
0 |
T39 |
1 |
0 |
0 |
0 |
T43 |
0 |
5 |
0 |
0 |
T44 |
0 |
5 |
0 |
0 |
T45 |
0 |
6 |
0 |
0 |
T46 |
1 |
0 |
0 |
0 |
T47 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
669 |
424 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
3 |
2 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T18 |
0 |
3 |
0 |
0 |
T21 |
7 |
6 |
0 |
0 |
T24 |
0 |
2 |
0 |
0 |
T25 |
1 |
0 |
0 |
0 |
T26 |
0 |
4 |
0 |
0 |
T28 |
1 |
0 |
0 |
0 |
T39 |
1 |
0 |
0 |
0 |
T43 |
0 |
4 |
0 |
0 |
T44 |
0 |
5 |
0 |
0 |
T45 |
0 |
6 |
0 |
0 |
T46 |
1 |
0 |
0 |
0 |
T47 |
1 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T7,T1,T2 |
0 | 1 | Covered | T7,T1,T2 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T1,T2 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T7,T1,T2 |
1 | 1 | Covered | T7,T1,T2 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
8745027 |
8744562 |
0 |
0 |
selKnown1 |
8744813 |
8744348 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8745027 |
8744562 |
0 |
0 |
T1 |
14186 |
14185 |
0 |
0 |
T2 |
15475 |
15474 |
0 |
0 |
T3 |
16004 |
16003 |
0 |
0 |
T4 |
147616 |
147615 |
0 |
0 |
T7 |
5919 |
5918 |
0 |
0 |
T8 |
1004 |
1003 |
0 |
0 |
T21 |
25579 |
25578 |
0 |
0 |
T25 |
1035 |
1034 |
0 |
0 |
T27 |
186 |
185 |
0 |
0 |
T28 |
386 |
385 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8744813 |
8744348 |
0 |
0 |
T1 |
14185 |
14184 |
0 |
0 |
T2 |
15475 |
15474 |
0 |
0 |
T3 |
16003 |
16002 |
0 |
0 |
T4 |
147616 |
147615 |
0 |
0 |
T7 |
5918 |
5917 |
0 |
0 |
T8 |
1003 |
1002 |
0 |
0 |
T21 |
25578 |
25577 |
0 |
0 |
T25 |
1034 |
1033 |
0 |
0 |
T27 |
186 |
185 |
0 |
0 |
T28 |
385 |
384 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T7,T1,T2 |
0 | 1 | Covered | T7,T1,T2 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T1,T2 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T7,T1,T2 |
1 | 1 | Covered | T7,T1,T2 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
1928 |
1463 |
0 |
0 |
selKnown1 |
1810 |
1345 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1928 |
1463 |
0 |
0 |
T4 |
12 |
11 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
3 |
2 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T18 |
0 |
4 |
0 |
0 |
T21 |
7 |
6 |
0 |
0 |
T24 |
0 |
5 |
0 |
0 |
T25 |
1 |
0 |
0 |
0 |
T26 |
0 |
4 |
0 |
0 |
T28 |
1 |
0 |
0 |
0 |
T39 |
1 |
0 |
0 |
0 |
T43 |
0 |
5 |
0 |
0 |
T44 |
0 |
5 |
0 |
0 |
T45 |
0 |
6 |
0 |
0 |
T46 |
1 |
0 |
0 |
0 |
T47 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1810 |
1345 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
3 |
2 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T18 |
0 |
3 |
0 |
0 |
T21 |
7 |
6 |
0 |
0 |
T24 |
0 |
2 |
0 |
0 |
T25 |
1 |
0 |
0 |
0 |
T26 |
0 |
4 |
0 |
0 |
T28 |
1 |
0 |
0 |
0 |
T39 |
1 |
0 |
0 |
0 |
T43 |
0 |
4 |
0 |
0 |
T44 |
0 |
5 |
0 |
0 |
T45 |
0 |
6 |
0 |
0 |
T46 |
1 |
0 |
0 |
0 |
T47 |
1 |
0 |
0 |
0 |