SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
84.59 | 96.32 | 86.85 | 92.10 | 73.75 | 90.44 | 98.53 | 54.13 |
T57 | /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.3249001717 | Aug 09 05:11:50 PM PDT 24 | Aug 09 05:12:19 PM PDT 24 | 37293490017 ps | ||
T78 | /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.2493158077 | Aug 09 05:12:31 PM PDT 24 | Aug 09 05:12:35 PM PDT 24 | 456677740 ps | ||
T307 | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.564145521 | Aug 09 05:12:03 PM PDT 24 | Aug 09 05:12:27 PM PDT 24 | 16864051983 ps | ||
T77 | /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.1844298971 | Aug 09 05:12:01 PM PDT 24 | Aug 09 05:12:04 PM PDT 24 | 198913505 ps | ||
T116 | /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.1835813797 | Aug 09 05:12:09 PM PDT 24 | Aug 09 05:12:14 PM PDT 24 | 369925128 ps | ||
T308 | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.1034587962 | Aug 09 05:12:22 PM PDT 24 | Aug 09 05:12:23 PM PDT 24 | 947076827 ps | ||
T58 | /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.1813638924 | Aug 09 05:11:49 PM PDT 24 | Aug 09 05:13:42 PM PDT 24 | 35765710141 ps | ||
T309 | /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.2827465034 | Aug 09 05:11:57 PM PDT 24 | Aug 09 05:11:57 PM PDT 24 | 135144467 ps | ||
T310 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2899181066 | Aug 09 05:11:54 PM PDT 24 | Aug 09 05:11:55 PM PDT 24 | 207458056 ps | ||
T79 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.409628223 | Aug 09 05:11:57 PM PDT 24 | Aug 09 05:13:12 PM PDT 24 | 7365546257 ps | ||
T311 | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.1830521234 | Aug 09 05:12:29 PM PDT 24 | Aug 09 05:12:58 PM PDT 24 | 41885256328 ps | ||
T312 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.957746190 | Aug 09 05:12:00 PM PDT 24 | Aug 09 05:13:02 PM PDT 24 | 57244445323 ps | ||
T313 | /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.4038809673 | Aug 09 05:11:59 PM PDT 24 | Aug 09 05:14:39 PM PDT 24 | 55598428264 ps | ||
T112 | /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.60369248 | Aug 09 05:12:20 PM PDT 24 | Aug 09 05:12:24 PM PDT 24 | 318161167 ps | ||
T80 | /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.520856733 | Aug 09 05:12:24 PM PDT 24 | Aug 09 05:12:30 PM PDT 24 | 179989624 ps | ||
T113 | /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.3278635020 | Aug 09 05:12:16 PM PDT 24 | Aug 09 05:12:22 PM PDT 24 | 1240403425 ps | ||
T114 | /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.3292630669 | Aug 09 05:12:09 PM PDT 24 | Aug 09 05:12:11 PM PDT 24 | 174067743 ps | ||
T117 | /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.910429095 | Aug 09 05:12:14 PM PDT 24 | Aug 09 05:12:25 PM PDT 24 | 3448020131 ps | ||
T81 | /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.3757664038 | Aug 09 05:12:22 PM PDT 24 | Aug 09 05:12:24 PM PDT 24 | 81047839 ps | ||
T115 | /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3451610174 | Aug 09 05:12:00 PM PDT 24 | Aug 09 05:12:14 PM PDT 24 | 2673393951 ps | ||
T82 | /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.3509186316 | Aug 09 05:12:08 PM PDT 24 | Aug 09 05:12:10 PM PDT 24 | 104637182 ps | ||
T314 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.796626403 | Aug 09 05:12:04 PM PDT 24 | Aug 09 05:12:09 PM PDT 24 | 1757865829 ps | ||
T83 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.513086340 | Aug 09 05:11:56 PM PDT 24 | Aug 09 05:11:58 PM PDT 24 | 69603874 ps | ||
T84 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1473760607 | Aug 09 05:12:00 PM PDT 24 | Aug 09 05:12:29 PM PDT 24 | 1510720810 ps | ||
T85 | /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.1028159375 | Aug 09 05:12:22 PM PDT 24 | Aug 09 05:12:24 PM PDT 24 | 127101496 ps | ||
T118 | /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.1650632762 | Aug 09 05:12:03 PM PDT 24 | Aug 09 05:12:13 PM PDT 24 | 864230605 ps | ||
T86 | /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.4001365736 | Aug 09 05:12:06 PM PDT 24 | Aug 09 05:12:10 PM PDT 24 | 276003309 ps | ||
T152 | /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.2361505159 | Aug 09 05:12:22 PM PDT 24 | Aug 09 05:12:38 PM PDT 24 | 3121181706 ps | ||
T161 | /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.154817606 | Aug 09 05:12:03 PM PDT 24 | Aug 09 05:15:12 PM PDT 24 | 20270324692 ps | ||
T315 | /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1768226088 | Aug 09 05:11:54 PM PDT 24 | Aug 09 05:11:55 PM PDT 24 | 76125592 ps | ||
T153 | /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2024560873 | Aug 09 05:12:08 PM PDT 24 | Aug 09 05:12:21 PM PDT 24 | 3189425803 ps | ||
T87 | /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.70373090 | Aug 09 05:12:20 PM PDT 24 | Aug 09 05:12:24 PM PDT 24 | 287975258 ps | ||
T94 | /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.701833421 | Aug 09 05:12:15 PM PDT 24 | Aug 09 05:12:19 PM PDT 24 | 341562241 ps | ||
T107 | /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.797074885 | Aug 09 05:12:21 PM PDT 24 | Aug 09 05:12:24 PM PDT 24 | 123059946 ps | ||
T316 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.760458209 | Aug 09 05:12:01 PM PDT 24 | Aug 09 05:12:03 PM PDT 24 | 1011773493 ps | ||
T95 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.1159717386 | Aug 09 05:11:42 PM PDT 24 | Aug 09 05:12:16 PM PDT 24 | 34982177262 ps | ||
T108 | /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.2454671365 | Aug 09 05:12:09 PM PDT 24 | Aug 09 05:12:13 PM PDT 24 | 1770193982 ps | ||
T96 | /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.3212025165 | Aug 09 05:12:28 PM PDT 24 | Aug 09 05:12:30 PM PDT 24 | 902711226 ps | ||
T317 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.2255236854 | Aug 09 05:11:49 PM PDT 24 | Aug 09 05:11:51 PM PDT 24 | 937548159 ps | ||
T97 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.1994000944 | Aug 09 05:11:59 PM PDT 24 | Aug 09 05:12:01 PM PDT 24 | 525270426 ps | ||
T154 | /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.764928922 | Aug 09 05:12:27 PM PDT 24 | Aug 09 05:12:48 PM PDT 24 | 4637214075 ps | ||
T98 | /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.4103315774 | Aug 09 05:12:13 PM PDT 24 | Aug 09 05:12:15 PM PDT 24 | 153975714 ps | ||
T318 | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.3843567209 | Aug 09 05:12:14 PM PDT 24 | Aug 09 05:12:15 PM PDT 24 | 2694222047 ps | ||
T319 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.306071224 | Aug 09 05:11:56 PM PDT 24 | Aug 09 05:11:57 PM PDT 24 | 353981419 ps | ||
T320 | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.3079095669 | Aug 09 05:12:18 PM PDT 24 | Aug 09 05:12:20 PM PDT 24 | 232329897 ps | ||
T321 | /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.1750142334 | Aug 09 05:12:08 PM PDT 24 | Aug 09 05:15:48 PM PDT 24 | 36016085610 ps | ||
T322 | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.1077612629 | Aug 09 05:12:01 PM PDT 24 | Aug 09 05:12:04 PM PDT 24 | 997796348 ps | ||
T99 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.3637989335 | Aug 09 05:11:40 PM PDT 24 | Aug 09 05:11:42 PM PDT 24 | 402673163 ps | ||
T323 | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.1902041273 | Aug 09 05:12:21 PM PDT 24 | Aug 09 05:12:22 PM PDT 24 | 141273808 ps | ||
T324 | /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.2813532389 | Aug 09 05:12:17 PM PDT 24 | Aug 09 05:12:19 PM PDT 24 | 370807014 ps | ||
T325 | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.642510380 | Aug 09 05:12:22 PM PDT 24 | Aug 09 05:12:37 PM PDT 24 | 11848907750 ps | ||
T326 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.1787079663 | Aug 09 05:11:56 PM PDT 24 | Aug 09 05:11:58 PM PDT 24 | 789123733 ps | ||
T327 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1441945921 | Aug 09 05:11:48 PM PDT 24 | Aug 09 05:11:53 PM PDT 24 | 4924366343 ps | ||
T160 | /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.1887148189 | Aug 09 05:12:03 PM PDT 24 | Aug 09 05:12:59 PM PDT 24 | 34658816205 ps | ||
T148 | /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1996242727 | Aug 09 05:12:05 PM PDT 24 | Aug 09 05:12:30 PM PDT 24 | 3132081228 ps | ||
T104 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.1417666957 | Aug 09 05:12:01 PM PDT 24 | Aug 09 05:12:03 PM PDT 24 | 191218248 ps | ||
T328 | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.3981266647 | Aug 09 05:12:15 PM PDT 24 | Aug 09 05:12:19 PM PDT 24 | 6296089374 ps | ||
T329 | /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.805461026 | Aug 09 05:11:57 PM PDT 24 | Aug 09 05:12:04 PM PDT 24 | 2848934250 ps | ||
T330 | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.104825096 | Aug 09 05:12:09 PM PDT 24 | Aug 09 05:12:13 PM PDT 24 | 7625455857 ps | ||
T331 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.1841933599 | Aug 09 05:11:57 PM PDT 24 | Aug 09 05:12:03 PM PDT 24 | 3617821616 ps | ||
T100 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.2298870080 | Aug 09 05:11:56 PM PDT 24 | Aug 09 05:13:02 PM PDT 24 | 1242128420 ps | ||
T332 | /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.210756637 | Aug 09 05:12:20 PM PDT 24 | Aug 09 05:12:23 PM PDT 24 | 363525579 ps | ||
T333 | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.640265419 | Aug 09 05:12:08 PM PDT 24 | Aug 09 05:12:09 PM PDT 24 | 254393041 ps | ||
T334 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.3918936645 | Aug 09 05:11:51 PM PDT 24 | Aug 09 05:11:53 PM PDT 24 | 1084749261 ps | ||
T335 | /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.16960149 | Aug 09 05:12:06 PM PDT 24 | Aug 09 05:12:08 PM PDT 24 | 251425230 ps | ||
T149 | /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.2702480059 | Aug 09 05:12:15 PM PDT 24 | Aug 09 05:12:35 PM PDT 24 | 1832893770 ps | ||
T90 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.1596684616 | Aug 09 05:11:49 PM PDT 24 | Aug 09 05:12:05 PM PDT 24 | 20040228707 ps | ||
T150 | /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.2250806240 | Aug 09 05:12:30 PM PDT 24 | Aug 09 05:12:41 PM PDT 24 | 1892468886 ps | ||
T336 | /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.3682077830 | Aug 09 05:12:17 PM PDT 24 | Aug 09 05:12:21 PM PDT 24 | 207565187 ps | ||
T337 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.10643480 | Aug 09 05:11:52 PM PDT 24 | Aug 09 05:12:15 PM PDT 24 | 26953253146 ps | ||
T338 | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.1020495550 | Aug 09 05:12:14 PM PDT 24 | Aug 09 05:12:27 PM PDT 24 | 8902820223 ps | ||
T339 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.2533378493 | Aug 09 05:11:49 PM PDT 24 | Aug 09 05:11:58 PM PDT 24 | 8618149265 ps | ||
T340 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.2969340262 | Aug 09 05:11:41 PM PDT 24 | Aug 09 05:11:42 PM PDT 24 | 227586698 ps | ||
T101 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.1207778958 | Aug 09 05:11:48 PM PDT 24 | Aug 09 05:11:51 PM PDT 24 | 449605300 ps | ||
T341 | /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.231585634 | Aug 09 05:11:54 PM PDT 24 | Aug 09 05:12:46 PM PDT 24 | 58330462643 ps | ||
T342 | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.1329118062 | Aug 09 05:12:28 PM PDT 24 | Aug 09 05:12:49 PM PDT 24 | 13713905695 ps | ||
T343 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.4082921368 | Aug 09 05:11:47 PM PDT 24 | Aug 09 05:11:52 PM PDT 24 | 2073798362 ps | ||
T344 | /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.3953193157 | Aug 09 05:12:27 PM PDT 24 | Aug 09 05:12:31 PM PDT 24 | 317368993 ps | ||
T102 | /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1016846078 | Aug 09 05:12:21 PM PDT 24 | Aug 09 05:12:26 PM PDT 24 | 353426407 ps | ||
T155 | /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.3216057582 | Aug 09 05:12:28 PM PDT 24 | Aug 09 05:12:49 PM PDT 24 | 4552245528 ps | ||
T345 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3604200579 | Aug 09 05:11:49 PM PDT 24 | Aug 09 05:12:17 PM PDT 24 | 3089306800 ps | ||
T156 | /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.972907489 | Aug 09 05:11:52 PM PDT 24 | Aug 09 05:12:09 PM PDT 24 | 2292630257 ps | ||
T346 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.3955951769 | Aug 09 05:11:56 PM PDT 24 | Aug 09 05:12:27 PM PDT 24 | 3462650832 ps | ||
T347 | /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3185524454 | Aug 09 05:12:14 PM PDT 24 | Aug 09 05:12:17 PM PDT 24 | 99042208 ps | ||
T348 | /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.752476949 | Aug 09 05:12:02 PM PDT 24 | Aug 09 05:12:06 PM PDT 24 | 153043589 ps | ||
T349 | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.1546599581 | Aug 09 05:12:33 PM PDT 24 | Aug 09 05:12:34 PM PDT 24 | 197999048 ps | ||
T350 | /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.1603061557 | Aug 09 05:12:24 PM PDT 24 | Aug 09 05:12:33 PM PDT 24 | 870894647 ps | ||
T351 | /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.1300352773 | Aug 09 05:12:20 PM PDT 24 | Aug 09 05:12:23 PM PDT 24 | 124932831 ps | ||
T352 | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.1989280742 | Aug 09 05:12:00 PM PDT 24 | Aug 09 05:12:01 PM PDT 24 | 333430876 ps | ||
T106 | /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.2760785259 | Aug 09 05:12:13 PM PDT 24 | Aug 09 05:12:15 PM PDT 24 | 96081423 ps | ||
T353 | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.4239016606 | Aug 09 05:12:18 PM PDT 24 | Aug 09 05:12:19 PM PDT 24 | 124866045 ps | ||
T354 | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.4091254467 | Aug 09 05:12:03 PM PDT 24 | Aug 09 05:12:06 PM PDT 24 | 2547978371 ps | ||
T355 | /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.2787666521 | Aug 09 05:12:35 PM PDT 24 | Aug 09 05:12:38 PM PDT 24 | 271518509 ps | ||
T356 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.397967376 | Aug 09 05:11:57 PM PDT 24 | Aug 09 05:14:00 PM PDT 24 | 188256303783 ps | ||
T357 | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2426208627 | Aug 09 05:12:22 PM PDT 24 | Aug 09 05:12:25 PM PDT 24 | 569013362 ps | ||
T103 | /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.2670485953 | Aug 09 05:12:27 PM PDT 24 | Aug 09 05:12:28 PM PDT 24 | 256238479 ps | ||
T358 | /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.2278292031 | Aug 09 05:12:15 PM PDT 24 | Aug 09 05:13:24 PM PDT 24 | 13243044755 ps | ||
T91 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.1414883910 | Aug 09 05:11:41 PM PDT 24 | Aug 09 05:12:15 PM PDT 24 | 12773870854 ps | ||
T359 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.857093065 | Aug 09 05:11:42 PM PDT 24 | Aug 09 05:11:47 PM PDT 24 | 6184258618 ps | ||
T360 | /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.1882043351 | Aug 09 05:12:14 PM PDT 24 | Aug 09 05:12:18 PM PDT 24 | 611892746 ps | ||
T361 | /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.3989581108 | Aug 09 05:12:29 PM PDT 24 | Aug 09 05:12:32 PM PDT 24 | 537455871 ps | ||
T362 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.3322985942 | Aug 09 05:11:56 PM PDT 24 | Aug 09 05:12:02 PM PDT 24 | 3184419645 ps | ||
T92 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.933930641 | Aug 09 05:11:50 PM PDT 24 | Aug 09 05:12:03 PM PDT 24 | 3954655636 ps | ||
T363 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2757907573 | Aug 09 05:11:40 PM PDT 24 | Aug 09 05:11:42 PM PDT 24 | 1431852726 ps | ||
T364 | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.797945535 | Aug 09 05:12:14 PM PDT 24 | Aug 09 05:12:48 PM PDT 24 | 11191085079 ps | ||
T365 | /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.2834838981 | Aug 09 05:12:09 PM PDT 24 | Aug 09 05:12:11 PM PDT 24 | 202139060 ps | ||
T366 | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.1354400202 | Aug 09 05:12:28 PM PDT 24 | Aug 09 05:12:29 PM PDT 24 | 240271699 ps | ||
T367 | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.1222782025 | Aug 09 05:12:03 PM PDT 24 | Aug 09 05:12:07 PM PDT 24 | 3091120263 ps | ||
T109 | /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1058773184 | Aug 09 05:12:05 PM PDT 24 | Aug 09 05:12:09 PM PDT 24 | 176467691 ps | ||
T93 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.1118674703 | Aug 09 05:11:54 PM PDT 24 | Aug 09 05:11:59 PM PDT 24 | 5288815939 ps | ||
T368 | /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.3314161720 | Aug 09 05:12:20 PM PDT 24 | Aug 09 05:12:27 PM PDT 24 | 4193462783 ps | ||
T369 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.3307451770 | Aug 09 05:11:57 PM PDT 24 | Aug 09 05:12:00 PM PDT 24 | 1195282249 ps | ||
T370 | /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.874648201 | Aug 09 05:11:41 PM PDT 24 | Aug 09 05:11:42 PM PDT 24 | 85388134 ps | ||
T371 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2402682196 | Aug 09 05:12:01 PM PDT 24 | Aug 09 05:12:10 PM PDT 24 | 6749785375 ps | ||
T372 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.2976024311 | Aug 09 05:12:01 PM PDT 24 | Aug 09 05:12:22 PM PDT 24 | 28244942931 ps | ||
T373 | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.755236549 | Aug 09 05:12:07 PM PDT 24 | Aug 09 05:12:11 PM PDT 24 | 6000387581 ps | ||
T374 | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.3716230987 | Aug 09 05:12:09 PM PDT 24 | Aug 09 05:12:15 PM PDT 24 | 5297498217 ps | ||
T151 | /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.739566532 | Aug 09 05:12:23 PM PDT 24 | Aug 09 05:12:46 PM PDT 24 | 3895275716 ps | ||
T375 | /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.2173948591 | Aug 09 05:12:24 PM PDT 24 | Aug 09 05:12:28 PM PDT 24 | 842173909 ps | ||
T376 | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.1836057280 | Aug 09 05:12:35 PM PDT 24 | Aug 09 05:12:44 PM PDT 24 | 3489749371 ps | ||
T377 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.1268340465 | Aug 09 05:12:04 PM PDT 24 | Aug 09 05:12:13 PM PDT 24 | 9200008652 ps | ||
T378 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.3689272594 | Aug 09 05:11:51 PM PDT 24 | Aug 09 05:13:15 PM PDT 24 | 71377043451 ps | ||
T379 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2031907679 | Aug 09 05:12:04 PM PDT 24 | Aug 09 05:12:09 PM PDT 24 | 175787225 ps | ||
T380 | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.3397273868 | Aug 09 05:12:22 PM PDT 24 | Aug 09 05:12:24 PM PDT 24 | 1580012677 ps | ||
T381 | /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3224251162 | Aug 09 05:12:09 PM PDT 24 | Aug 09 05:12:28 PM PDT 24 | 9106145151 ps | ||
T382 | /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.4195615449 | Aug 09 05:11:55 PM PDT 24 | Aug 09 05:11:56 PM PDT 24 | 166206527 ps | ||
T383 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.2900113756 | Aug 09 05:11:54 PM PDT 24 | Aug 09 05:11:56 PM PDT 24 | 482105572 ps | ||
T110 | /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.795889190 | Aug 09 05:12:29 PM PDT 24 | Aug 09 05:12:33 PM PDT 24 | 389139617 ps | ||
T111 | /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2029809774 | Aug 09 05:12:08 PM PDT 24 | Aug 09 05:12:13 PM PDT 24 | 2713854441 ps | ||
T384 | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.1205900667 | Aug 09 05:12:28 PM PDT 24 | Aug 09 05:14:19 PM PDT 24 | 40671837093 ps | ||
T385 | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.2692782755 | Aug 09 05:12:14 PM PDT 24 | Aug 09 05:12:23 PM PDT 24 | 11149389558 ps | ||
T386 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.4100362567 | Aug 09 05:11:49 PM PDT 24 | Aug 09 05:12:07 PM PDT 24 | 7898750058 ps | ||
T387 | /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.2426667781 | Aug 09 05:12:06 PM PDT 24 | Aug 09 05:12:09 PM PDT 24 | 138960821 ps | ||
T388 | /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.4254379455 | Aug 09 05:12:28 PM PDT 24 | Aug 09 05:12:35 PM PDT 24 | 250788534 ps | ||
T389 | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.1713757672 | Aug 09 05:12:35 PM PDT 24 | Aug 09 05:13:18 PM PDT 24 | 15152220935 ps | ||
T390 | /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.3191317757 | Aug 09 05:12:29 PM PDT 24 | Aug 09 05:12:31 PM PDT 24 | 178080946 ps | ||
T391 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.1891346091 | Aug 09 05:11:56 PM PDT 24 | Aug 09 05:12:25 PM PDT 24 | 53820208652 ps | ||
T392 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.1219607453 | Aug 09 05:11:42 PM PDT 24 | Aug 09 05:11:43 PM PDT 24 | 189212401 ps | ||
T393 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.1702990971 | Aug 09 05:11:56 PM PDT 24 | Aug 09 05:12:06 PM PDT 24 | 12423981448 ps | ||
T394 | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2054293436 | Aug 09 05:12:22 PM PDT 24 | Aug 09 05:12:23 PM PDT 24 | 178638096 ps | ||
T395 | /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.291548278 | Aug 09 05:12:02 PM PDT 24 | Aug 09 05:12:02 PM PDT 24 | 29092498 ps | ||
T396 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.2263523371 | Aug 09 05:11:47 PM PDT 24 | Aug 09 05:11:50 PM PDT 24 | 309713097 ps | ||
T397 | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.686890863 | Aug 09 05:12:24 PM PDT 24 | Aug 09 05:12:47 PM PDT 24 | 16996166129 ps | ||
T398 | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.845370616 | Aug 09 05:12:21 PM PDT 24 | Aug 09 05:12:24 PM PDT 24 | 5943484512 ps | ||
T399 | /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.185610248 | Aug 09 05:12:34 PM PDT 24 | Aug 09 05:12:37 PM PDT 24 | 106934816 ps | ||
T400 | /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.2998943155 | Aug 09 05:12:03 PM PDT 24 | Aug 09 05:12:04 PM PDT 24 | 47676206 ps | ||
T401 | /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.3580367658 | Aug 09 05:12:21 PM PDT 24 | Aug 09 05:12:23 PM PDT 24 | 202477992 ps | ||
T402 | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.570016944 | Aug 09 05:12:22 PM PDT 24 | Aug 09 05:12:30 PM PDT 24 | 4337068855 ps | ||
T403 | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.4151049034 | Aug 09 05:12:22 PM PDT 24 | Aug 09 05:12:23 PM PDT 24 | 253722539 ps | ||
T404 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.903383714 | Aug 09 05:11:51 PM PDT 24 | Aug 09 05:11:53 PM PDT 24 | 72016495 ps | ||
T405 | /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.4016234851 | Aug 09 05:12:33 PM PDT 24 | Aug 09 05:12:36 PM PDT 24 | 144781115 ps | ||
T406 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.777897729 | Aug 09 05:11:58 PM PDT 24 | Aug 09 05:11:59 PM PDT 24 | 131436209 ps | ||
T407 | /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.3066161025 | Aug 09 05:11:56 PM PDT 24 | Aug 09 05:11:57 PM PDT 24 | 58147201 ps | ||
T408 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.1281512571 | Aug 09 05:11:49 PM PDT 24 | Aug 09 05:11:50 PM PDT 24 | 284898369 ps | ||
T409 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.3863736684 | Aug 09 05:11:48 PM PDT 24 | Aug 09 05:11:51 PM PDT 24 | 920725710 ps | ||
T157 | /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.2527427678 | Aug 09 05:12:29 PM PDT 24 | Aug 09 05:12:45 PM PDT 24 | 1301310362 ps | ||
T410 | /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.3092945042 | Aug 09 05:11:41 PM PDT 24 | Aug 09 05:11:47 PM PDT 24 | 959215769 ps | ||
T411 | /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.44051299 | Aug 09 05:12:28 PM PDT 24 | Aug 09 05:12:32 PM PDT 24 | 258155427 ps | ||
T105 | /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.2053293602 | Aug 09 05:12:17 PM PDT 24 | Aug 09 05:12:19 PM PDT 24 | 291833587 ps | ||
T412 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.2805061716 | Aug 09 05:11:50 PM PDT 24 | Aug 09 05:12:54 PM PDT 24 | 6989335708 ps | ||
T413 | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.1644106469 | Aug 09 05:12:14 PM PDT 24 | Aug 09 05:12:34 PM PDT 24 | 6972638626 ps | ||
T414 | /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3806814436 | Aug 09 05:12:08 PM PDT 24 | Aug 09 05:12:11 PM PDT 24 | 125333569 ps | ||
T415 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1660177270 | Aug 09 05:11:42 PM PDT 24 | Aug 09 05:12:33 PM PDT 24 | 72131150169 ps | ||
T416 | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.64289849 | Aug 09 05:12:18 PM PDT 24 | Aug 09 05:12:22 PM PDT 24 | 4150717464 ps | ||
T417 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2952622657 | Aug 09 05:12:00 PM PDT 24 | Aug 09 05:12:01 PM PDT 24 | 283718097 ps | ||
T418 | /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.2425720926 | Aug 09 05:12:04 PM PDT 24 | Aug 09 05:12:05 PM PDT 24 | 222001704 ps | ||
T419 | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2210465386 | Aug 09 05:12:01 PM PDT 24 | Aug 09 05:12:03 PM PDT 24 | 1050022381 ps | ||
T420 | /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.3478006627 | Aug 09 05:11:43 PM PDT 24 | Aug 09 05:11:44 PM PDT 24 | 147032215 ps | ||
T421 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.3894561789 | Aug 09 05:11:56 PM PDT 24 | Aug 09 05:11:58 PM PDT 24 | 51730279 ps | ||
T422 | /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.1322383267 | Aug 09 05:11:50 PM PDT 24 | Aug 09 05:11:54 PM PDT 24 | 893385642 ps | ||
T423 | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.3336389396 | Aug 09 05:12:27 PM PDT 24 | Aug 09 05:12:31 PM PDT 24 | 1277845858 ps | ||
T424 | /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.2664212344 | Aug 09 05:12:02 PM PDT 24 | Aug 09 05:12:05 PM PDT 24 | 278333711 ps | ||
T425 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.4260956082 | Aug 09 05:12:02 PM PDT 24 | Aug 09 05:13:20 PM PDT 24 | 38503399781 ps | ||
T426 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.1872612281 | Aug 09 05:11:55 PM PDT 24 | Aug 09 05:11:57 PM PDT 24 | 181586014 ps | ||
T427 | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.3665378503 | Aug 09 05:12:08 PM PDT 24 | Aug 09 05:12:09 PM PDT 24 | 185675475 ps | ||
T428 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.638250170 | Aug 09 05:11:49 PM PDT 24 | Aug 09 05:11:53 PM PDT 24 | 2289272372 ps | ||
T429 | /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.4217735800 | Aug 09 05:12:07 PM PDT 24 | Aug 09 05:12:30 PM PDT 24 | 40701295301 ps | ||
T430 | /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.931081760 | Aug 09 05:11:42 PM PDT 24 | Aug 09 05:11:45 PM PDT 24 | 169253831 ps | ||
T158 | /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.2605659108 | Aug 09 05:11:58 PM PDT 24 | Aug 09 05:12:22 PM PDT 24 | 6019772788 ps | ||
T431 | /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.2935497752 | Aug 09 05:12:21 PM PDT 24 | Aug 09 05:12:26 PM PDT 24 | 270738326 ps | ||
T432 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.3649220484 | Aug 09 05:11:55 PM PDT 24 | Aug 09 05:13:01 PM PDT 24 | 1642176560 ps | ||
T433 | /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.3352138303 | Aug 09 05:11:56 PM PDT 24 | Aug 09 05:11:57 PM PDT 24 | 71687972 ps | ||
T434 | /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.1717651600 | Aug 09 05:12:01 PM PDT 24 | Aug 09 05:12:04 PM PDT 24 | 117929712 ps | ||
T435 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.1439495134 | Aug 09 05:11:57 PM PDT 24 | Aug 09 05:12:01 PM PDT 24 | 338723946 ps | ||
T436 | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.1592799684 | Aug 09 05:12:08 PM PDT 24 | Aug 09 05:12:11 PM PDT 24 | 721963550 ps | ||
T437 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.2426439531 | Aug 09 05:11:43 PM PDT 24 | Aug 09 05:11:46 PM PDT 24 | 169093170 ps | ||
T438 | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.3093030722 | Aug 09 05:12:27 PM PDT 24 | Aug 09 05:12:29 PM PDT 24 | 282578950 ps | ||
T439 | /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.1674977663 | Aug 09 05:12:21 PM PDT 24 | Aug 09 05:12:27 PM PDT 24 | 517956585 ps | ||
T440 | /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.1911541913 | Aug 09 05:12:32 PM PDT 24 | Aug 09 05:12:35 PM PDT 24 | 222074911 ps | ||
T441 | /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.2241286592 | Aug 09 05:11:50 PM PDT 24 | Aug 09 05:11:51 PM PDT 24 | 101644085 ps | ||
T442 | /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.4282736735 | Aug 09 05:11:48 PM PDT 24 | Aug 09 05:11:53 PM PDT 24 | 1443542782 ps | ||
T443 | /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.1062148027 | Aug 09 05:12:03 PM PDT 24 | Aug 09 05:12:13 PM PDT 24 | 3744175093 ps | ||
T444 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.1769396673 | Aug 09 05:11:56 PM PDT 24 | Aug 09 05:12:01 PM PDT 24 | 230300376 ps | ||
T445 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.2555537343 | Aug 09 05:11:41 PM PDT 24 | Aug 09 05:12:50 PM PDT 24 | 12701006489 ps | ||
T446 | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.711314446 | Aug 09 05:12:22 PM PDT 24 | Aug 09 05:12:25 PM PDT 24 | 2186196311 ps | ||
T447 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3900287637 | Aug 09 05:11:43 PM PDT 24 | Aug 09 05:11:46 PM PDT 24 | 2144125714 ps | ||
T448 | /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.197655201 | Aug 09 05:11:55 PM PDT 24 | Aug 09 05:12:01 PM PDT 24 | 631250020 ps | ||
T449 | /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.3471999994 | Aug 09 05:11:56 PM PDT 24 | Aug 09 05:12:04 PM PDT 24 | 1080962397 ps | ||
T450 | /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.3907968191 | Aug 09 05:12:14 PM PDT 24 | Aug 09 05:12:25 PM PDT 24 | 1849026334 ps | ||
T451 | /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2998498547 | Aug 09 05:12:19 PM PDT 24 | Aug 09 05:12:22 PM PDT 24 | 187576146 ps | ||
T159 | /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.4145332284 | Aug 09 05:12:20 PM PDT 24 | Aug 09 05:12:43 PM PDT 24 | 6816372439 ps | ||
T452 | /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.1828876169 | Aug 09 05:12:30 PM PDT 24 | Aug 09 05:12:37 PM PDT 24 | 643095110 ps | ||
T453 | /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.3628876034 | Aug 09 05:11:43 PM PDT 24 | Aug 09 05:11:53 PM PDT 24 | 1672086550 ps | ||
T454 | /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.1826350592 | Aug 09 05:12:08 PM PDT 24 | Aug 09 05:12:11 PM PDT 24 | 292449562 ps | ||
T455 | /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.1640285384 | Aug 09 05:12:13 PM PDT 24 | Aug 09 05:12:18 PM PDT 24 | 1137292547 ps | ||
T456 | /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.3648719510 | Aug 09 05:12:27 PM PDT 24 | Aug 09 05:12:30 PM PDT 24 | 457503630 ps | ||
T457 | /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.533636454 | Aug 09 05:11:56 PM PDT 24 | Aug 09 05:12:00 PM PDT 24 | 176882380 ps | ||
T458 | /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.1773495891 | Aug 09 05:12:20 PM PDT 24 | Aug 09 05:12:24 PM PDT 24 | 936871034 ps | ||
T459 | /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.760306827 | Aug 09 05:12:13 PM PDT 24 | Aug 09 05:12:19 PM PDT 24 | 296551175 ps | ||
T460 | /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.2762242238 | Aug 09 05:12:03 PM PDT 24 | Aug 09 05:13:48 PM PDT 24 | 25363166540 ps | ||
T461 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.1220722284 | Aug 09 05:12:02 PM PDT 24 | Aug 09 05:12:05 PM PDT 24 | 190170407 ps | ||
T462 | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.2267972012 | Aug 09 05:12:21 PM PDT 24 | Aug 09 05:12:22 PM PDT 24 | 89070167 ps | ||
T463 | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.2396001910 | Aug 09 05:12:08 PM PDT 24 | Aug 09 05:12:13 PM PDT 24 | 3644182574 ps | ||
T464 | /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.241654518 | Aug 09 05:12:02 PM PDT 24 | Aug 09 05:12:10 PM PDT 24 | 535796959 ps | ||
T465 | /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3381428282 | Aug 09 05:12:13 PM PDT 24 | Aug 09 05:12:17 PM PDT 24 | 712263675 ps |
Test location | /workspace/coverage/default/6.rv_dm_stress_all_with_rand_reset.2459108049 |
Short name | T6 |
Test name | |
Test status | |
Simulation time | 120856806148 ps |
CPU time | 493.01 seconds |
Started | Aug 09 07:13:31 PM PDT 24 |
Finished | Aug 09 07:21:45 PM PDT 24 |
Peak memory | 235948 kb |
Host | smart-29c31581-7fa8-4df4-ba99-55075bda5386 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459108049 -assert nopost proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all_with_rand_reset.2459108049 |
Directory | /workspace/6.rv_dm_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.530168167 |
Short name | T12 |
Test name | |
Test status | |
Simulation time | 1876258636 ps |
CPU time | 2.22 seconds |
Started | Aug 09 07:13:43 PM PDT 24 |
Finished | Aug 09 07:13:45 PM PDT 24 |
Peak memory | 213840 kb |
Host | smart-2fcb71bc-ada1-48d7-8f08-004d2eb899e4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=530168167 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.530168167 |
Directory | /workspace/14.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.234875599 |
Short name | T126 |
Test name | |
Test status | |
Simulation time | 102756361172 ps |
CPU time | 267.16 seconds |
Started | Aug 09 07:13:44 PM PDT 24 |
Finished | Aug 09 07:18:12 PM PDT 24 |
Peak memory | 216756 kb |
Host | smart-c1266f3a-15c4-41af-b702-961189c53470 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=234875599 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.234875599 |
Directory | /workspace/10.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.1813638924 |
Short name | T58 |
Test name | |
Test status | |
Simulation time | 35765710141 ps |
CPU time | 112.51 seconds |
Started | Aug 09 05:11:49 PM PDT 24 |
Finished | Aug 09 05:13:42 PM PDT 24 |
Peak memory | 222152 kb |
Host | smart-4a2539c0-ca0d-48f1-8a42-c4a8389333db |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813638924 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.1813638924 |
Directory | /workspace/0.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.910429095 |
Short name | T117 |
Test name | |
Test status | |
Simulation time | 3448020131 ps |
CPU time | 11.56 seconds |
Started | Aug 09 05:12:14 PM PDT 24 |
Finished | Aug 09 05:12:25 PM PDT 24 |
Peak memory | 213844 kb |
Host | smart-1db9b744-3986-4242-8ea9-ef3d7c07ed41 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910429095 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.910429095 |
Directory | /workspace/11.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/1.rv_dm_stress_all_with_rand_reset.506616606 |
Short name | T74 |
Test name | |
Test status | |
Simulation time | 499078237813 ps |
CPU time | 1831.78 seconds |
Started | Aug 09 07:13:27 PM PDT 24 |
Finished | Aug 09 07:43:59 PM PDT 24 |
Peak memory | 241584 kb |
Host | smart-b2e800c2-2eea-4018-b97a-115c32e57085 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506616606 -assert nopostp roc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all_with_rand_reset.506616606 |
Directory | /workspace/1.rv_dm_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/35.rv_dm_alert_test.3768117735 |
Short name | T33 |
Test name | |
Test status | |
Simulation time | 58224092 ps |
CPU time | 0.85 seconds |
Started | Aug 09 07:13:56 PM PDT 24 |
Finished | Aug 09 07:13:56 PM PDT 24 |
Peak memory | 205276 kb |
Host | smart-56e4f8b9-c96c-411a-84f9-b72ab58acac5 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768117735 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.3768117735 |
Directory | /workspace/35.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/0.rv_dm_dmi_failed_op.3112309100 |
Short name | T50 |
Test name | |
Test status | |
Simulation time | 311323779 ps |
CPU time | 1.74 seconds |
Started | Aug 09 07:13:16 PM PDT 24 |
Finished | Aug 09 07:13:18 PM PDT 24 |
Peak memory | 205256 kb |
Host | smart-e5e14389-1645-485f-b74c-8c71e1a56447 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3112309100 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dmi_failed_op.3112309100 |
Directory | /workspace/0.rv_dm_dmi_failed_op/latest |
Test location | /workspace/coverage/default/1.rv_dm_sba_debug_disabled.3714601365 |
Short name | T119 |
Test name | |
Test status | |
Simulation time | 5037286874 ps |
CPU time | 12.55 seconds |
Started | Aug 09 07:13:24 PM PDT 24 |
Finished | Aug 09 07:13:37 PM PDT 24 |
Peak memory | 205616 kb |
Host | smart-2f6b08eb-c926-4633-8221-169e23ccb074 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3714601365 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.3714601365 |
Directory | /workspace/1.rv_dm_sba_debug_disabled/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.2298870080 |
Short name | T100 |
Test name | |
Test status | |
Simulation time | 1242128420 ps |
CPU time | 66.16 seconds |
Started | Aug 09 05:11:56 PM PDT 24 |
Finished | Aug 09 05:13:02 PM PDT 24 |
Peak memory | 205484 kb |
Host | smart-bbcddeaf-b0cf-4527-9e54-7970d0c49cf3 |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298870080 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 4.rv_dm_csr_aliasing.2298870080 |
Directory | /workspace/4.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/default/1.rv_dm_debug_disabled.2279453807 |
Short name | T53 |
Test name | |
Test status | |
Simulation time | 86752285 ps |
CPU time | 0.86 seconds |
Started | Aug 09 07:13:24 PM PDT 24 |
Finished | Aug 09 07:13:26 PM PDT 24 |
Peak memory | 215796 kb |
Host | smart-cc1a51e8-d666-4454-ad77-88f04d47699e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2279453807 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.2279453807 |
Directory | /workspace/1.rv_dm_debug_disabled/latest |
Test location | /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.4182860196 |
Short name | T188 |
Test name | |
Test status | |
Simulation time | 12224999519 ps |
CPU time | 8.95 seconds |
Started | Aug 09 07:13:42 PM PDT 24 |
Finished | Aug 09 07:13:51 PM PDT 24 |
Peak memory | 213976 kb |
Host | smart-2ddbcda8-8f8a-46bf-9b7e-f07145f9628c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4182860196 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.4182860196 |
Directory | /workspace/12.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/33.rv_dm_stress_all.2070680023 |
Short name | T22 |
Test name | |
Test status | |
Simulation time | 7600822945 ps |
CPU time | 12.78 seconds |
Started | Aug 09 07:13:55 PM PDT 24 |
Finished | Aug 09 07:14:08 PM PDT 24 |
Peak memory | 205588 kb |
Host | smart-b629ff73-09f2-402c-8562-62a31d76dc3a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070680023 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.2070680023 |
Directory | /workspace/33.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/0.rv_dm_sec_cm.3671404044 |
Short name | T66 |
Test name | |
Test status | |
Simulation time | 993026783 ps |
CPU time | 1.73 seconds |
Started | Aug 09 07:13:29 PM PDT 24 |
Finished | Aug 09 07:13:31 PM PDT 24 |
Peak memory | 229876 kb |
Host | smart-5c89f962-e8fe-4f1a-817b-0c7b4d5f82e6 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671404044 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.3671404044 |
Directory | /workspace/0.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_exception.4054010736 |
Short name | T17 |
Test name | |
Test status | |
Simulation time | 110506891 ps |
CPU time | 0.93 seconds |
Started | Aug 09 07:13:23 PM PDT 24 |
Finished | Aug 09 07:13:24 PM PDT 24 |
Peak memory | 205280 kb |
Host | smart-802d4300-76e0-4d6e-a2cf-f4fef2e0a371 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4054010736 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.4054010736 |
Directory | /workspace/1.rv_dm_cmderr_exception/latest |
Test location | /workspace/coverage/default/4.rv_dm_stress_all.112190809 |
Short name | T246 |
Test name | |
Test status | |
Simulation time | 2022937986 ps |
CPU time | 6.45 seconds |
Started | Aug 09 07:13:38 PM PDT 24 |
Finished | Aug 09 07:13:44 PM PDT 24 |
Peak memory | 213592 kb |
Host | smart-9888b5dc-ea9f-488b-8203-7985bc8baaa4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112190809 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.112190809 |
Directory | /workspace/4.rv_dm_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.972907489 |
Short name | T156 |
Test name | |
Test status | |
Simulation time | 2292630257 ps |
CPU time | 16.89 seconds |
Started | Aug 09 05:11:52 PM PDT 24 |
Finished | Aug 09 05:12:09 PM PDT 24 |
Peak memory | 213892 kb |
Host | smart-ebbbafd9-b9a9-4d01-9ce3-33d7adc2cc2f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972907489 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.972907489 |
Directory | /workspace/1.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.520856733 |
Short name | T80 |
Test name | |
Test status | |
Simulation time | 179989624 ps |
CPU time | 6.52 seconds |
Started | Aug 09 05:12:24 PM PDT 24 |
Finished | Aug 09 05:12:30 PM PDT 24 |
Peak memory | 205556 kb |
Host | smart-0f7f516e-2ba0-46a7-bb4e-6fd402883ae3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520856733 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same_ csr_outstanding.520856733 |
Directory | /workspace/15.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/default/25.rv_dm_stress_all.2536228765 |
Short name | T7 |
Test name | |
Test status | |
Simulation time | 3915922676 ps |
CPU time | 6.31 seconds |
Started | Aug 09 07:13:51 PM PDT 24 |
Finished | Aug 09 07:13:57 PM PDT 24 |
Peak memory | 213824 kb |
Host | smart-2857eaa4-192f-4014-8b1b-d86f145719bc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536228765 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.2536228765 |
Directory | /workspace/25.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/0.rv_dm_rom_read_access.927257234 |
Short name | T38 |
Test name | |
Test status | |
Simulation time | 86093303 ps |
CPU time | 0.99 seconds |
Started | Aug 09 07:13:15 PM PDT 24 |
Finished | Aug 09 07:13:16 PM PDT 24 |
Peak memory | 213444 kb |
Host | smart-04f57ab8-5318-40af-b85a-702475f138a4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=927257234 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.927257234 |
Directory | /workspace/0.rv_dm_rom_read_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.4221943497 |
Short name | T142 |
Test name | |
Test status | |
Simulation time | 16678234953 ps |
CPU time | 30.44 seconds |
Started | Aug 09 07:13:33 PM PDT 24 |
Finished | Aug 09 07:14:04 PM PDT 24 |
Peak memory | 213924 kb |
Host | smart-134e2a5c-5211-40d2-a5e3-6ce22fac25d9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4221943497 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.4221943497 |
Directory | /workspace/1.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_hartsel_warl.584286986 |
Short name | T25 |
Test name | |
Test status | |
Simulation time | 377191923 ps |
CPU time | 0.77 seconds |
Started | Aug 09 07:13:16 PM PDT 24 |
Finished | Aug 09 07:13:17 PM PDT 24 |
Peak memory | 205252 kb |
Host | smart-9218fc82-3f61-453f-a28e-56151c541222 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=584286986 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hartsel_warl_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hartsel_warl.584286986 |
Directory | /workspace/0.rv_dm_hartsel_warl/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.739566532 |
Short name | T151 |
Test name | |
Test status | |
Simulation time | 3895275716 ps |
CPU time | 22.78 seconds |
Started | Aug 09 05:12:23 PM PDT 24 |
Finished | Aug 09 05:12:46 PM PDT 24 |
Peak memory | 213884 kb |
Host | smart-49315858-5b8c-46aa-a8d3-9bc74af1eb20 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739566532 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.739566532 |
Directory | /workspace/15.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.2527427678 |
Short name | T157 |
Test name | |
Test status | |
Simulation time | 1301310362 ps |
CPU time | 16.12 seconds |
Started | Aug 09 05:12:29 PM PDT 24 |
Finished | Aug 09 05:12:45 PM PDT 24 |
Peak memory | 213788 kb |
Host | smart-dc54e9f5-3500-4ef2-bd1f-a36d4f7e90d8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527427678 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.2 527427678 |
Directory | /workspace/18.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.2451952759 |
Short name | T130 |
Test name | |
Test status | |
Simulation time | 1416974451 ps |
CPU time | 5.16 seconds |
Started | Aug 09 07:13:41 PM PDT 24 |
Finished | Aug 09 07:13:46 PM PDT 24 |
Peak memory | 213812 kb |
Host | smart-48ff702f-0eaf-452b-b3b1-8f8bb02e38a8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2451952759 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.2451952759 |
Directory | /workspace/13.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/29.rv_dm_stress_all.1778293379 |
Short name | T146 |
Test name | |
Test status | |
Simulation time | 5132698406 ps |
CPU time | 4.71 seconds |
Started | Aug 09 07:13:59 PM PDT 24 |
Finished | Aug 09 07:14:04 PM PDT 24 |
Peak memory | 213788 kb |
Host | smart-ad472cc9-3f62-457d-a002-96b024741993 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778293379 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.1778293379 |
Directory | /workspace/29.rv_dm_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.306071224 |
Short name | T319 |
Test name | |
Test status | |
Simulation time | 353981419 ps |
CPU time | 1.14 seconds |
Started | Aug 09 05:11:56 PM PDT 24 |
Finished | Aug 09 05:11:57 PM PDT 24 |
Peak memory | 204940 kb |
Host | smart-4e8762b0-a32d-4d6c-8190-4ab174872f3c |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306071224 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr _hw_reset.306071224 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/default/0.rv_dm_abstractcmd_status.2213243627 |
Short name | T45 |
Test name | |
Test status | |
Simulation time | 105233953 ps |
CPU time | 0.97 seconds |
Started | Aug 09 07:13:13 PM PDT 24 |
Finished | Aug 09 07:13:15 PM PDT 24 |
Peak memory | 205264 kb |
Host | smart-ec0fc864-a66c-4c13-97b2-12f404b703a7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2213243627 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.2213243627 |
Directory | /workspace/0.rv_dm_abstractcmd_status/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.1414883910 |
Short name | T91 |
Test name | |
Test status | |
Simulation time | 12773870854 ps |
CPU time | 34 seconds |
Started | Aug 09 05:11:41 PM PDT 24 |
Finished | Aug 09 05:12:15 PM PDT 24 |
Peak memory | 205644 kb |
Host | smart-6adbcac5-e3d0-42cc-b32b-dabd93bc94d0 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414883910 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs r_hw_reset.1414883910 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.691761254 |
Short name | T34 |
Test name | |
Test status | |
Simulation time | 753008560 ps |
CPU time | 3.06 seconds |
Started | Aug 09 07:13:22 PM PDT 24 |
Finished | Aug 09 07:13:26 PM PDT 24 |
Peak memory | 205264 kb |
Host | smart-b1d04d52-9a87-4238-8ac3-977e16619529 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=691761254 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.691761254 |
Directory | /workspace/0.rv_dm_cmderr_halt_resume/latest |
Test location | /workspace/coverage/default/0.rv_dm_hart_unavail.3906220585 |
Short name | T144 |
Test name | |
Test status | |
Simulation time | 265421368 ps |
CPU time | 1.09 seconds |
Started | Aug 09 07:13:18 PM PDT 24 |
Finished | Aug 09 07:13:19 PM PDT 24 |
Peak memory | 205260 kb |
Host | smart-4caeaee7-768b-4ad8-950c-f68e666b0679 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3906220585 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.3906220585 |
Directory | /workspace/0.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/15.rv_dm_stress_all.1822364476 |
Short name | T132 |
Test name | |
Test status | |
Simulation time | 4365330816 ps |
CPU time | 4.34 seconds |
Started | Aug 09 07:13:43 PM PDT 24 |
Finished | Aug 09 07:13:48 PM PDT 24 |
Peak memory | 205584 kb |
Host | smart-163c27e6-ff8c-4300-957d-924d29db7a75 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822364476 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.1822364476 |
Directory | /workspace/15.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/32.rv_dm_stress_all.1365384324 |
Short name | T138 |
Test name | |
Test status | |
Simulation time | 8226742006 ps |
CPU time | 20.09 seconds |
Started | Aug 09 07:13:54 PM PDT 24 |
Finished | Aug 09 07:14:14 PM PDT 24 |
Peak memory | 213768 kb |
Host | smart-f1e13147-5417-4736-b02f-e9783da687cc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365384324 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.1365384324 |
Directory | /workspace/32.rv_dm_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.2053293602 |
Short name | T105 |
Test name | |
Test status | |
Simulation time | 291833587 ps |
CPU time | 1.49 seconds |
Started | Aug 09 05:12:17 PM PDT 24 |
Finished | Aug 09 05:12:19 PM PDT 24 |
Peak memory | 213712 kb |
Host | smart-1788bbf0-4f04-4903-87c8-1985de582981 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053293602 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.2053293602 |
Directory | /workspace/10.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.2555537343 |
Short name | T445 |
Test name | |
Test status | |
Simulation time | 12701006489 ps |
CPU time | 68.82 seconds |
Started | Aug 09 05:11:41 PM PDT 24 |
Finished | Aug 09 05:12:50 PM PDT 24 |
Peak memory | 213804 kb |
Host | smart-2b496691-3638-4c40-b88e-80ac2a1a674e |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555537343 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 0.rv_dm_csr_aliasing.2555537343 |
Directory | /workspace/0.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.1159717386 |
Short name | T95 |
Test name | |
Test status | |
Simulation time | 34982177262 ps |
CPU time | 33.82 seconds |
Started | Aug 09 05:11:42 PM PDT 24 |
Finished | Aug 09 05:12:16 PM PDT 24 |
Peak memory | 206060 kb |
Host | smart-76b0152a-4ad2-4158-8968-9d3da03feb7a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159717386 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.1159717386 |
Directory | /workspace/0.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.1219607453 |
Short name | T392 |
Test name | |
Test status | |
Simulation time | 189212401 ps |
CPU time | 1.51 seconds |
Started | Aug 09 05:11:42 PM PDT 24 |
Finished | Aug 09 05:11:43 PM PDT 24 |
Peak memory | 213728 kb |
Host | smart-2ea83a11-48e4-475f-8723-dbdd9cc9f4c5 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219607453 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.1219607453 |
Directory | /workspace/0.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.2426439531 |
Short name | T437 |
Test name | |
Test status | |
Simulation time | 169093170 ps |
CPU time | 2.17 seconds |
Started | Aug 09 05:11:43 PM PDT 24 |
Finished | Aug 09 05:11:46 PM PDT 24 |
Peak memory | 218600 kb |
Host | smart-f8fb5902-f833-4641-b2bd-33a2d861f5bb |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426439531 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.2426439531 |
Directory | /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.3637989335 |
Short name | T99 |
Test name | |
Test status | |
Simulation time | 402673163 ps |
CPU time | 2.13 seconds |
Started | Aug 09 05:11:40 PM PDT 24 |
Finished | Aug 09 05:11:42 PM PDT 24 |
Peak memory | 213664 kb |
Host | smart-51894492-bf47-4111-8cef-fe1effb1afb1 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637989335 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.3637989335 |
Directory | /workspace/0.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1660177270 |
Short name | T415 |
Test name | |
Test status | |
Simulation time | 72131150169 ps |
CPU time | 50.78 seconds |
Started | Aug 09 05:11:42 PM PDT 24 |
Finished | Aug 09 05:12:33 PM PDT 24 |
Peak memory | 205548 kb |
Host | smart-dbfee666-d0f5-43fc-8dbc-45697f6c680f |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660177270 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs r_aliasing.1660177270 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1441945921 |
Short name | T327 |
Test name | |
Test status | |
Simulation time | 4924366343 ps |
CPU time | 4.74 seconds |
Started | Aug 09 05:11:48 PM PDT 24 |
Finished | Aug 09 05:11:53 PM PDT 24 |
Peak memory | 205524 kb |
Host | smart-f8979aba-2709-4043-b0aa-79f631604033 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441945921 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0. rv_dm_jtag_dmi_csr_bit_bash.1441945921 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3900287637 |
Short name | T447 |
Test name | |
Test status | |
Simulation time | 2144125714 ps |
CPU time | 2.26 seconds |
Started | Aug 09 05:11:43 PM PDT 24 |
Finished | Aug 09 05:11:46 PM PDT 24 |
Peak memory | 205500 kb |
Host | smart-e1189ea5-5f11-4662-8a69-0bdd871a2bca |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900287637 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.3 900287637 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2757907573 |
Short name | T363 |
Test name | |
Test status | |
Simulation time | 1431852726 ps |
CPU time | 1.84 seconds |
Started | Aug 09 05:11:40 PM PDT 24 |
Finished | Aug 09 05:11:42 PM PDT 24 |
Peak memory | 205284 kb |
Host | smart-c365f1a9-42db-4acf-93fb-ccfc4b66b3bb |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757907573 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_aliasing.2757907573 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.857093065 |
Short name | T359 |
Test name | |
Test status | |
Simulation time | 6184258618 ps |
CPU time | 4.88 seconds |
Started | Aug 09 05:11:42 PM PDT 24 |
Finished | Aug 09 05:11:47 PM PDT 24 |
Peak memory | 205560 kb |
Host | smart-df6a00b8-b1a9-4ffa-9045-d907a29da1dd |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857093065 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr _bit_bash.857093065 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.2969340262 |
Short name | T340 |
Test name | |
Test status | |
Simulation time | 227586698 ps |
CPU time | 0.84 seconds |
Started | Aug 09 05:11:41 PM PDT 24 |
Finished | Aug 09 05:11:42 PM PDT 24 |
Peak memory | 205264 kb |
Host | smart-1eeaed00-3a9f-4d34-8733-2f59605b4af8 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969340262 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_hw_reset.2969340262 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.3863736684 |
Short name | T409 |
Test name | |
Test status | |
Simulation time | 920725710 ps |
CPU time | 2.55 seconds |
Started | Aug 09 05:11:48 PM PDT 24 |
Finished | Aug 09 05:11:51 PM PDT 24 |
Peak memory | 205236 kb |
Host | smart-4f6bf66d-b55d-453d-a2f8-0e7a7f327b48 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863736684 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.3 863736684 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.874648201 |
Short name | T370 |
Test name | |
Test status | |
Simulation time | 85388134 ps |
CPU time | 0.7 seconds |
Started | Aug 09 05:11:41 PM PDT 24 |
Finished | Aug 09 05:11:42 PM PDT 24 |
Peak memory | 205324 kb |
Host | smart-503199e8-a089-423f-8c18-b4061fc1a549 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874648201 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_part ial_access.874648201 |
Directory | /workspace/0.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.3478006627 |
Short name | T420 |
Test name | |
Test status | |
Simulation time | 147032215 ps |
CPU time | 1.05 seconds |
Started | Aug 09 05:11:43 PM PDT 24 |
Finished | Aug 09 05:11:44 PM PDT 24 |
Peak memory | 205268 kb |
Host | smart-bf172eee-e72e-4c67-81fb-611e6e886865 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478006627 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.3478006627 |
Directory | /workspace/0.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.931081760 |
Short name | T430 |
Test name | |
Test status | |
Simulation time | 169253831 ps |
CPU time | 3.39 seconds |
Started | Aug 09 05:11:42 PM PDT 24 |
Finished | Aug 09 05:11:45 PM PDT 24 |
Peak memory | 205608 kb |
Host | smart-018bf6da-0e0a-402f-8965-c04bed5c7065 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931081760 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_c sr_outstanding.931081760 |
Directory | /workspace/0.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.3092945042 |
Short name | T410 |
Test name | |
Test status | |
Simulation time | 959215769 ps |
CPU time | 6.16 seconds |
Started | Aug 09 05:11:41 PM PDT 24 |
Finished | Aug 09 05:11:47 PM PDT 24 |
Peak memory | 213848 kb |
Host | smart-fab36c16-6ec7-45d1-94d8-bf377ea572f4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092945042 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.3092945042 |
Directory | /workspace/0.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.3628876034 |
Short name | T453 |
Test name | |
Test status | |
Simulation time | 1672086550 ps |
CPU time | 9.21 seconds |
Started | Aug 09 05:11:43 PM PDT 24 |
Finished | Aug 09 05:11:53 PM PDT 24 |
Peak memory | 213740 kb |
Host | smart-18ddfbd7-3da5-492b-9bde-9089e44c50c5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628876034 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.3628876034 |
Directory | /workspace/0.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3604200579 |
Short name | T345 |
Test name | |
Test status | |
Simulation time | 3089306800 ps |
CPU time | 28.03 seconds |
Started | Aug 09 05:11:49 PM PDT 24 |
Finished | Aug 09 05:12:17 PM PDT 24 |
Peak memory | 213908 kb |
Host | smart-819449fb-613b-4c1b-af24-9d8b830f98c7 |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604200579 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 1.rv_dm_csr_aliasing.3604200579 |
Directory | /workspace/1.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.2805061716 |
Short name | T412 |
Test name | |
Test status | |
Simulation time | 6989335708 ps |
CPU time | 64.39 seconds |
Started | Aug 09 05:11:50 PM PDT 24 |
Finished | Aug 09 05:12:54 PM PDT 24 |
Peak memory | 213800 kb |
Host | smart-cff1d471-e51c-45da-bb1b-b4cc9848af8d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805061716 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.2805061716 |
Directory | /workspace/1.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.1207778958 |
Short name | T101 |
Test name | |
Test status | |
Simulation time | 449605300 ps |
CPU time | 2.6 seconds |
Started | Aug 09 05:11:48 PM PDT 24 |
Finished | Aug 09 05:11:51 PM PDT 24 |
Peak memory | 213692 kb |
Host | smart-de087498-d9ed-46e8-97b7-658f6e19dae3 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207778958 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.1207778958 |
Directory | /workspace/1.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.2263523371 |
Short name | T396 |
Test name | |
Test status | |
Simulation time | 309713097 ps |
CPU time | 3.74 seconds |
Started | Aug 09 05:11:47 PM PDT 24 |
Finished | Aug 09 05:11:50 PM PDT 24 |
Peak memory | 219104 kb |
Host | smart-a8634a7c-3cbe-4e18-ba38-79e60fc9c4fb |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263523371 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.2263523371 |
Directory | /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.903383714 |
Short name | T404 |
Test name | |
Test status | |
Simulation time | 72016495 ps |
CPU time | 1.59 seconds |
Started | Aug 09 05:11:51 PM PDT 24 |
Finished | Aug 09 05:11:53 PM PDT 24 |
Peak memory | 213696 kb |
Host | smart-07a77072-cbac-4f2c-aeba-deeb903fb59b |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903383714 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.903383714 |
Directory | /workspace/1.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.3689272594 |
Short name | T378 |
Test name | |
Test status | |
Simulation time | 71377043451 ps |
CPU time | 84.32 seconds |
Started | Aug 09 05:11:51 PM PDT 24 |
Finished | Aug 09 05:13:15 PM PDT 24 |
Peak memory | 205896 kb |
Host | smart-7341f667-a073-402d-b07e-0c8d3ff78d2d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689272594 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs r_aliasing.3689272594 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.2533378493 |
Short name | T339 |
Test name | |
Test status | |
Simulation time | 8618149265 ps |
CPU time | 9.08 seconds |
Started | Aug 09 05:11:49 PM PDT 24 |
Finished | Aug 09 05:11:58 PM PDT 24 |
Peak memory | 205500 kb |
Host | smart-303e5e59-11e1-4f0d-b757-36da073b71a5 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533378493 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1. rv_dm_jtag_dmi_csr_bit_bash.2533378493 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.933930641 |
Short name | T92 |
Test name | |
Test status | |
Simulation time | 3954655636 ps |
CPU time | 13.14 seconds |
Started | Aug 09 05:11:50 PM PDT 24 |
Finished | Aug 09 05:12:03 PM PDT 24 |
Peak memory | 205644 kb |
Host | smart-ded4c976-c4d6-4810-a71d-42dab3d8a032 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933930641 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr _hw_reset.933930641 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.4082921368 |
Short name | T343 |
Test name | |
Test status | |
Simulation time | 2073798362 ps |
CPU time | 4.57 seconds |
Started | Aug 09 05:11:47 PM PDT 24 |
Finished | Aug 09 05:11:52 PM PDT 24 |
Peak memory | 205488 kb |
Host | smart-7a0784e9-861c-4e65-bbcc-c69b7b7c5e1f |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082921368 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.4 082921368 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.3918936645 |
Short name | T334 |
Test name | |
Test status | |
Simulation time | 1084749261 ps |
CPU time | 2.1 seconds |
Started | Aug 09 05:11:51 PM PDT 24 |
Finished | Aug 09 05:11:53 PM PDT 24 |
Peak memory | 205248 kb |
Host | smart-c7b34c2d-3d25-458b-96c5-0857d7d26734 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918936645 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs r_aliasing.3918936645 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.4100362567 |
Short name | T386 |
Test name | |
Test status | |
Simulation time | 7898750058 ps |
CPU time | 17.82 seconds |
Started | Aug 09 05:11:49 PM PDT 24 |
Finished | Aug 09 05:12:07 PM PDT 24 |
Peak memory | 205468 kb |
Host | smart-42be02a9-930b-4e4a-81ed-6fcbc20654ae |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100362567 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs r_bit_bash.4100362567 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.2291062777 |
Short name | T61 |
Test name | |
Test status | |
Simulation time | 376861474 ps |
CPU time | 1.61 seconds |
Started | Aug 09 05:11:49 PM PDT 24 |
Finished | Aug 09 05:11:50 PM PDT 24 |
Peak memory | 205200 kb |
Host | smart-0c4ef3dd-5eee-4615-be59-70922884a1fe |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291062777 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.2 291062777 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1768226088 |
Short name | T315 |
Test name | |
Test status | |
Simulation time | 76125592 ps |
CPU time | 0.7 seconds |
Started | Aug 09 05:11:54 PM PDT 24 |
Finished | Aug 09 05:11:55 PM PDT 24 |
Peak memory | 205340 kb |
Host | smart-d391df55-04ad-45b8-8e69-0f6eb86c1f08 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768226088 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par tial_access.1768226088 |
Directory | /workspace/1.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.2241286592 |
Short name | T441 |
Test name | |
Test status | |
Simulation time | 101644085 ps |
CPU time | 0.79 seconds |
Started | Aug 09 05:11:50 PM PDT 24 |
Finished | Aug 09 05:11:51 PM PDT 24 |
Peak memory | 205236 kb |
Host | smart-b9b76d42-965d-4fd7-8e98-87c2aa284382 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241286592 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.2241286592 |
Directory | /workspace/1.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.4282736735 |
Short name | T442 |
Test name | |
Test status | |
Simulation time | 1443542782 ps |
CPU time | 4.49 seconds |
Started | Aug 09 05:11:48 PM PDT 24 |
Finished | Aug 09 05:11:53 PM PDT 24 |
Peak memory | 205508 kb |
Host | smart-fb66629b-ef75-4510-941f-82cce896e5e4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282736735 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_ csr_outstanding.4282736735 |
Directory | /workspace/1.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.3249001717 |
Short name | T57 |
Test name | |
Test status | |
Simulation time | 37293490017 ps |
CPU time | 28.96 seconds |
Started | Aug 09 05:11:50 PM PDT 24 |
Finished | Aug 09 05:12:19 PM PDT 24 |
Peak memory | 222160 kb |
Host | smart-60298d12-84e0-4b66-9b6b-b3a77b1d71b3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249001717 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.3249001717 |
Directory | /workspace/1.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.1322383267 |
Short name | T422 |
Test name | |
Test status | |
Simulation time | 893385642 ps |
CPU time | 4.19 seconds |
Started | Aug 09 05:11:50 PM PDT 24 |
Finished | Aug 09 05:11:54 PM PDT 24 |
Peak memory | 213836 kb |
Host | smart-d907501f-cc3a-467f-9a33-7d76cd45e6bb |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322383267 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.1322383267 |
Directory | /workspace/1.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.1882043351 |
Short name | T360 |
Test name | |
Test status | |
Simulation time | 611892746 ps |
CPU time | 3.72 seconds |
Started | Aug 09 05:12:14 PM PDT 24 |
Finished | Aug 09 05:12:18 PM PDT 24 |
Peak memory | 219480 kb |
Host | smart-4c9bc5f1-d4d5-4fbc-b0ac-645d035b5cc1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882043351 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.1882043351 |
Directory | /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.2692782755 |
Short name | T385 |
Test name | |
Test status | |
Simulation time | 11149389558 ps |
CPU time | 8.54 seconds |
Started | Aug 09 05:12:14 PM PDT 24 |
Finished | Aug 09 05:12:23 PM PDT 24 |
Peak memory | 205564 kb |
Host | smart-847af52e-a96c-4979-9717-0eb2d518ead3 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692782755 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10 .rv_dm_jtag_dmi_csr_bit_bash.2692782755 |
Directory | /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.3843567209 |
Short name | T318 |
Test name | |
Test status | |
Simulation time | 2694222047 ps |
CPU time | 1.46 seconds |
Started | Aug 09 05:12:14 PM PDT 24 |
Finished | Aug 09 05:12:15 PM PDT 24 |
Peak memory | 205508 kb |
Host | smart-1c8624bd-f6a2-4b3d-a225-7ca22c387ae4 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843567209 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw. 3843567209 |
Directory | /workspace/10.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.3079095669 |
Short name | T320 |
Test name | |
Test status | |
Simulation time | 232329897 ps |
CPU time | 1.24 seconds |
Started | Aug 09 05:12:18 PM PDT 24 |
Finished | Aug 09 05:12:20 PM PDT 24 |
Peak memory | 205288 kb |
Host | smart-2b0bb543-5a27-44fd-b069-68f22f167c51 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079095669 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw. 3079095669 |
Directory | /workspace/10.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.1640285384 |
Short name | T455 |
Test name | |
Test status | |
Simulation time | 1137292547 ps |
CPU time | 4.49 seconds |
Started | Aug 09 05:12:13 PM PDT 24 |
Finished | Aug 09 05:12:18 PM PDT 24 |
Peak memory | 205532 kb |
Host | smart-71294ea5-0fe4-45c2-b0ac-3e4553e195c4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640285384 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same _csr_outstanding.1640285384 |
Directory | /workspace/10.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3185524454 |
Short name | T347 |
Test name | |
Test status | |
Simulation time | 99042208 ps |
CPU time | 2.68 seconds |
Started | Aug 09 05:12:14 PM PDT 24 |
Finished | Aug 09 05:12:17 PM PDT 24 |
Peak memory | 213884 kb |
Host | smart-d42de9f2-785e-4e9e-844d-320ffc8076f1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185524454 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.3185524454 |
Directory | /workspace/10.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.2702480059 |
Short name | T149 |
Test name | |
Test status | |
Simulation time | 1832893770 ps |
CPU time | 20.02 seconds |
Started | Aug 09 05:12:15 PM PDT 24 |
Finished | Aug 09 05:12:35 PM PDT 24 |
Peak memory | 213764 kb |
Host | smart-799f656b-d2c7-46b3-94e4-02a70530df0e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702480059 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.2 702480059 |
Directory | /workspace/10.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3381428282 |
Short name | T465 |
Test name | |
Test status | |
Simulation time | 712263675 ps |
CPU time | 3.53 seconds |
Started | Aug 09 05:12:13 PM PDT 24 |
Finished | Aug 09 05:12:17 PM PDT 24 |
Peak memory | 218212 kb |
Host | smart-6da0fadd-ad77-4b26-8aec-a057ac891bc0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381428282 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.3381428282 |
Directory | /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.2760785259 |
Short name | T106 |
Test name | |
Test status | |
Simulation time | 96081423 ps |
CPU time | 1.55 seconds |
Started | Aug 09 05:12:13 PM PDT 24 |
Finished | Aug 09 05:12:15 PM PDT 24 |
Peak memory | 213728 kb |
Host | smart-62c9a83d-8838-46f0-869d-c9775b043d4d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760785259 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.2760785259 |
Directory | /workspace/11.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.1644106469 |
Short name | T413 |
Test name | |
Test status | |
Simulation time | 6972638626 ps |
CPU time | 19.77 seconds |
Started | Aug 09 05:12:14 PM PDT 24 |
Finished | Aug 09 05:12:34 PM PDT 24 |
Peak memory | 205444 kb |
Host | smart-f89ee368-276d-4d58-800c-0d54bc8b11aa |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644106469 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11 .rv_dm_jtag_dmi_csr_bit_bash.1644106469 |
Directory | /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.540626599 |
Short name | T306 |
Test name | |
Test status | |
Simulation time | 1371311862 ps |
CPU time | 4.66 seconds |
Started | Aug 09 05:12:14 PM PDT 24 |
Finished | Aug 09 05:12:19 PM PDT 24 |
Peak memory | 205380 kb |
Host | smart-8f236684-c480-4d5a-b5e8-52574cfae10f |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540626599 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.540626599 |
Directory | /workspace/11.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.818871372 |
Short name | T59 |
Test name | |
Test status | |
Simulation time | 207862729 ps |
CPU time | 1.19 seconds |
Started | Aug 09 05:12:16 PM PDT 24 |
Finished | Aug 09 05:12:18 PM PDT 24 |
Peak memory | 205280 kb |
Host | smart-b7fe6d4f-bacc-4152-b7c9-d60827ce04d0 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818871372 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.818871372 |
Directory | /workspace/11.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.701833421 |
Short name | T94 |
Test name | |
Test status | |
Simulation time | 341562241 ps |
CPU time | 4.5 seconds |
Started | Aug 09 05:12:15 PM PDT 24 |
Finished | Aug 09 05:12:19 PM PDT 24 |
Peak memory | 205520 kb |
Host | smart-6cde1d84-15b7-414f-b458-814c3caee7a3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701833421 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same_ csr_outstanding.701833421 |
Directory | /workspace/11.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.3682077830 |
Short name | T336 |
Test name | |
Test status | |
Simulation time | 207565187 ps |
CPU time | 4.33 seconds |
Started | Aug 09 05:12:17 PM PDT 24 |
Finished | Aug 09 05:12:21 PM PDT 24 |
Peak memory | 213908 kb |
Host | smart-9b8a6e40-fc9c-4f0d-a001-ebd41500256f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682077830 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.3682077830 |
Directory | /workspace/11.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.1773495891 |
Short name | T458 |
Test name | |
Test status | |
Simulation time | 936871034 ps |
CPU time | 3.67 seconds |
Started | Aug 09 05:12:20 PM PDT 24 |
Finished | Aug 09 05:12:24 PM PDT 24 |
Peak memory | 217080 kb |
Host | smart-691f0aa0-899c-46d6-a70c-23cb00eac9bd |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773495891 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.1773495891 |
Directory | /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.1028159375 |
Short name | T85 |
Test name | |
Test status | |
Simulation time | 127101496 ps |
CPU time | 1.67 seconds |
Started | Aug 09 05:12:22 PM PDT 24 |
Finished | Aug 09 05:12:24 PM PDT 24 |
Peak memory | 213664 kb |
Host | smart-c744fef7-10a7-4a49-921a-9738ca239db1 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028159375 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.1028159375 |
Directory | /workspace/12.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.1020495550 |
Short name | T338 |
Test name | |
Test status | |
Simulation time | 8902820223 ps |
CPU time | 12.17 seconds |
Started | Aug 09 05:12:14 PM PDT 24 |
Finished | Aug 09 05:12:27 PM PDT 24 |
Peak memory | 205480 kb |
Host | smart-f6072703-375d-468f-99b6-777f74311e95 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020495550 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12 .rv_dm_jtag_dmi_csr_bit_bash.1020495550 |
Directory | /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.64289849 |
Short name | T416 |
Test name | |
Test status | |
Simulation time | 4150717464 ps |
CPU time | 3.91 seconds |
Started | Aug 09 05:12:18 PM PDT 24 |
Finished | Aug 09 05:12:22 PM PDT 24 |
Peak memory | 205612 kb |
Host | smart-6ec68d7d-1468-44f5-8a06-666a2023baf2 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64289849 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.64289849 |
Directory | /workspace/12.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.4239016606 |
Short name | T353 |
Test name | |
Test status | |
Simulation time | 124866045 ps |
CPU time | 0.85 seconds |
Started | Aug 09 05:12:18 PM PDT 24 |
Finished | Aug 09 05:12:19 PM PDT 24 |
Peak memory | 205288 kb |
Host | smart-e4fc993f-bf57-4923-a836-5f2db7ad0b0e |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239016606 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw. 4239016606 |
Directory | /workspace/12.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1016846078 |
Short name | T102 |
Test name | |
Test status | |
Simulation time | 353426407 ps |
CPU time | 4.36 seconds |
Started | Aug 09 05:12:21 PM PDT 24 |
Finished | Aug 09 05:12:26 PM PDT 24 |
Peak memory | 205568 kb |
Host | smart-b53aa06a-4aa9-48f7-bb28-b5dc7886ac43 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016846078 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same _csr_outstanding.1016846078 |
Directory | /workspace/12.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.1674977663 |
Short name | T439 |
Test name | |
Test status | |
Simulation time | 517956585 ps |
CPU time | 5.59 seconds |
Started | Aug 09 05:12:21 PM PDT 24 |
Finished | Aug 09 05:12:27 PM PDT 24 |
Peak memory | 213888 kb |
Host | smart-f5ccc779-0e2c-4d1f-b0e1-741e08ca8854 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674977663 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.1674977663 |
Directory | /workspace/12.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.4145332284 |
Short name | T159 |
Test name | |
Test status | |
Simulation time | 6816372439 ps |
CPU time | 23.05 seconds |
Started | Aug 09 05:12:20 PM PDT 24 |
Finished | Aug 09 05:12:43 PM PDT 24 |
Peak memory | 213780 kb |
Host | smart-80b44bfb-b180-4a5d-8168-a265eead32d2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145332284 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.4 145332284 |
Directory | /workspace/12.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.2173948591 |
Short name | T375 |
Test name | |
Test status | |
Simulation time | 842173909 ps |
CPU time | 4 seconds |
Started | Aug 09 05:12:24 PM PDT 24 |
Finished | Aug 09 05:12:28 PM PDT 24 |
Peak memory | 219780 kb |
Host | smart-727014c5-876d-4385-be7b-60d6d8a45943 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173948591 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.2173948591 |
Directory | /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.3580367658 |
Short name | T401 |
Test name | |
Test status | |
Simulation time | 202477992 ps |
CPU time | 1.65 seconds |
Started | Aug 09 05:12:21 PM PDT 24 |
Finished | Aug 09 05:12:23 PM PDT 24 |
Peak memory | 213672 kb |
Host | smart-d3a74706-1c96-4bbd-a4d2-9220f1167cd1 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580367658 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.3580367658 |
Directory | /workspace/13.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.686890863 |
Short name | T397 |
Test name | |
Test status | |
Simulation time | 16996166129 ps |
CPU time | 22.89 seconds |
Started | Aug 09 05:12:24 PM PDT 24 |
Finished | Aug 09 05:12:47 PM PDT 24 |
Peak memory | 205588 kb |
Host | smart-cea42fba-6e84-44d8-974a-dfbc35900cc4 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686890863 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13. rv_dm_jtag_dmi_csr_bit_bash.686890863 |
Directory | /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.642510380 |
Short name | T325 |
Test name | |
Test status | |
Simulation time | 11848907750 ps |
CPU time | 14.59 seconds |
Started | Aug 09 05:12:22 PM PDT 24 |
Finished | Aug 09 05:12:37 PM PDT 24 |
Peak memory | 205528 kb |
Host | smart-9540836c-9b1c-4746-bbdf-05044ebdc016 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642510380 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.642510380 |
Directory | /workspace/13.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2054293436 |
Short name | T394 |
Test name | |
Test status | |
Simulation time | 178638096 ps |
CPU time | 1.18 seconds |
Started | Aug 09 05:12:22 PM PDT 24 |
Finished | Aug 09 05:12:23 PM PDT 24 |
Peak memory | 205260 kb |
Host | smart-21a5eca9-4b30-4bd1-b4d3-a3a9f0134ba6 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054293436 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw. 2054293436 |
Directory | /workspace/13.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.70373090 |
Short name | T87 |
Test name | |
Test status | |
Simulation time | 287975258 ps |
CPU time | 3.59 seconds |
Started | Aug 09 05:12:20 PM PDT 24 |
Finished | Aug 09 05:12:24 PM PDT 24 |
Peak memory | 205644 kb |
Host | smart-6a704564-2857-4a97-a624-9d3aad25fafa |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70373090 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same_c sr_outstanding.70373090 |
Directory | /workspace/13.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.2935497752 |
Short name | T431 |
Test name | |
Test status | |
Simulation time | 270738326 ps |
CPU time | 5.06 seconds |
Started | Aug 09 05:12:21 PM PDT 24 |
Finished | Aug 09 05:12:26 PM PDT 24 |
Peak memory | 213892 kb |
Host | smart-c2d9a8af-3905-40db-ac6f-a2a650a9a27e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935497752 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.2935497752 |
Directory | /workspace/13.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.2361505159 |
Short name | T152 |
Test name | |
Test status | |
Simulation time | 3121181706 ps |
CPU time | 16.45 seconds |
Started | Aug 09 05:12:22 PM PDT 24 |
Finished | Aug 09 05:12:38 PM PDT 24 |
Peak memory | 213916 kb |
Host | smart-97c7ea0a-c72e-4dac-8c89-3f2cbd437aa4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361505159 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.2 361505159 |
Directory | /workspace/13.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.210756637 |
Short name | T332 |
Test name | |
Test status | |
Simulation time | 363525579 ps |
CPU time | 2.64 seconds |
Started | Aug 09 05:12:20 PM PDT 24 |
Finished | Aug 09 05:12:23 PM PDT 24 |
Peak memory | 217924 kb |
Host | smart-9747de56-6425-4824-a921-fb95f68d1e06 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210756637 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.210756637 |
Directory | /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.3757664038 |
Short name | T81 |
Test name | |
Test status | |
Simulation time | 81047839 ps |
CPU time | 1.64 seconds |
Started | Aug 09 05:12:22 PM PDT 24 |
Finished | Aug 09 05:12:24 PM PDT 24 |
Peak memory | 213640 kb |
Host | smart-b7bf40e8-beb3-4640-8880-c5c15557ac2c |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757664038 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.3757664038 |
Directory | /workspace/14.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.2267972012 |
Short name | T462 |
Test name | |
Test status | |
Simulation time | 89070167 ps |
CPU time | 0.78 seconds |
Started | Aug 09 05:12:21 PM PDT 24 |
Finished | Aug 09 05:12:22 PM PDT 24 |
Peak memory | 205156 kb |
Host | smart-67396443-bee2-465b-86d7-1abe744a30c2 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267972012 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14 .rv_dm_jtag_dmi_csr_bit_bash.2267972012 |
Directory | /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.3397273868 |
Short name | T380 |
Test name | |
Test status | |
Simulation time | 1580012677 ps |
CPU time | 2.1 seconds |
Started | Aug 09 05:12:22 PM PDT 24 |
Finished | Aug 09 05:12:24 PM PDT 24 |
Peak memory | 205480 kb |
Host | smart-92a08643-41ae-43fb-b866-3bcc8b82e06a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397273868 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw. 3397273868 |
Directory | /workspace/14.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2426208627 |
Short name | T357 |
Test name | |
Test status | |
Simulation time | 569013362 ps |
CPU time | 2.13 seconds |
Started | Aug 09 05:12:22 PM PDT 24 |
Finished | Aug 09 05:12:25 PM PDT 24 |
Peak memory | 205172 kb |
Host | smart-1dc95b71-cedf-474b-b2a1-d85957f4f737 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426208627 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw. 2426208627 |
Directory | /workspace/14.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.797074885 |
Short name | T107 |
Test name | |
Test status | |
Simulation time | 123059946 ps |
CPU time | 3.67 seconds |
Started | Aug 09 05:12:21 PM PDT 24 |
Finished | Aug 09 05:12:24 PM PDT 24 |
Peak memory | 205568 kb |
Host | smart-2914fdd4-eff1-4baf-b340-1d9bf9e2aa5e |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797074885 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same_ csr_outstanding.797074885 |
Directory | /workspace/14.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.60369248 |
Short name | T112 |
Test name | |
Test status | |
Simulation time | 318161167 ps |
CPU time | 4.21 seconds |
Started | Aug 09 05:12:20 PM PDT 24 |
Finished | Aug 09 05:12:24 PM PDT 24 |
Peak memory | 213816 kb |
Host | smart-f3ebdec2-fc79-40a7-be72-de5a770568ba |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60369248 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.60369248 |
Directory | /workspace/14.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.1603061557 |
Short name | T350 |
Test name | |
Test status | |
Simulation time | 870894647 ps |
CPU time | 8.89 seconds |
Started | Aug 09 05:12:24 PM PDT 24 |
Finished | Aug 09 05:12:33 PM PDT 24 |
Peak memory | 213816 kb |
Host | smart-592b8af1-ab32-4ddb-8f82-a3f81b1ac2ce |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603061557 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.1 603061557 |
Directory | /workspace/14.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.2411222953 |
Short name | T76 |
Test name | |
Test status | |
Simulation time | 460123601 ps |
CPU time | 2.54 seconds |
Started | Aug 09 05:12:23 PM PDT 24 |
Finished | Aug 09 05:12:25 PM PDT 24 |
Peak memory | 218976 kb |
Host | smart-f4d825ea-9f64-41a9-a25f-2776baf8e6c4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411222953 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.2411222953 |
Directory | /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2998498547 |
Short name | T451 |
Test name | |
Test status | |
Simulation time | 187576146 ps |
CPU time | 2.39 seconds |
Started | Aug 09 05:12:19 PM PDT 24 |
Finished | Aug 09 05:12:22 PM PDT 24 |
Peak memory | 213768 kb |
Host | smart-3b53043a-0524-4d5a-8ed6-09a962baf517 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998498547 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.2998498547 |
Directory | /workspace/15.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.845370616 |
Short name | T398 |
Test name | |
Test status | |
Simulation time | 5943484512 ps |
CPU time | 2.9 seconds |
Started | Aug 09 05:12:21 PM PDT 24 |
Finished | Aug 09 05:12:24 PM PDT 24 |
Peak memory | 205600 kb |
Host | smart-286d17a4-c348-4192-9189-daf955397623 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845370616 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15. rv_dm_jtag_dmi_csr_bit_bash.845370616 |
Directory | /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.570016944 |
Short name | T402 |
Test name | |
Test status | |
Simulation time | 4337068855 ps |
CPU time | 7.96 seconds |
Started | Aug 09 05:12:22 PM PDT 24 |
Finished | Aug 09 05:12:30 PM PDT 24 |
Peak memory | 205532 kb |
Host | smart-2520a00b-1edf-4855-8c62-e7636e55a60a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570016944 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.570016944 |
Directory | /workspace/15.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.1034587962 |
Short name | T308 |
Test name | |
Test status | |
Simulation time | 947076827 ps |
CPU time | 0.87 seconds |
Started | Aug 09 05:12:22 PM PDT 24 |
Finished | Aug 09 05:12:23 PM PDT 24 |
Peak memory | 205248 kb |
Host | smart-66889158-72eb-4bac-9462-a4f2b68b1cf4 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034587962 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw. 1034587962 |
Directory | /workspace/15.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.3314161720 |
Short name | T368 |
Test name | |
Test status | |
Simulation time | 4193462783 ps |
CPU time | 6.87 seconds |
Started | Aug 09 05:12:20 PM PDT 24 |
Finished | Aug 09 05:12:27 PM PDT 24 |
Peak memory | 214012 kb |
Host | smart-a8400f2d-cfb1-46b9-815e-76b2154a9572 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314161720 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.3314161720 |
Directory | /workspace/15.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.2787666521 |
Short name | T355 |
Test name | |
Test status | |
Simulation time | 271518509 ps |
CPU time | 2.72 seconds |
Started | Aug 09 05:12:35 PM PDT 24 |
Finished | Aug 09 05:12:38 PM PDT 24 |
Peak memory | 221948 kb |
Host | smart-37c2f1ae-9e20-467a-914e-62f2612df17b |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787666521 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.2787666521 |
Directory | /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.4016234851 |
Short name | T405 |
Test name | |
Test status | |
Simulation time | 144781115 ps |
CPU time | 2.52 seconds |
Started | Aug 09 05:12:33 PM PDT 24 |
Finished | Aug 09 05:12:36 PM PDT 24 |
Peak memory | 213636 kb |
Host | smart-e69a8f8f-11b7-40b7-bbcc-eda60d862905 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016234851 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.4016234851 |
Directory | /workspace/16.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.1902041273 |
Short name | T323 |
Test name | |
Test status | |
Simulation time | 141273808 ps |
CPU time | 1 seconds |
Started | Aug 09 05:12:21 PM PDT 24 |
Finished | Aug 09 05:12:22 PM PDT 24 |
Peak memory | 205212 kb |
Host | smart-7086dfaa-4284-4f75-a939-b1072f81ffed |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902041273 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16 .rv_dm_jtag_dmi_csr_bit_bash.1902041273 |
Directory | /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.711314446 |
Short name | T446 |
Test name | |
Test status | |
Simulation time | 2186196311 ps |
CPU time | 2.86 seconds |
Started | Aug 09 05:12:22 PM PDT 24 |
Finished | Aug 09 05:12:25 PM PDT 24 |
Peak memory | 205596 kb |
Host | smart-80430afa-09be-4445-b1bc-1d8147903fe2 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711314446 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.711314446 |
Directory | /workspace/16.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.4151049034 |
Short name | T403 |
Test name | |
Test status | |
Simulation time | 253722539 ps |
CPU time | 0.97 seconds |
Started | Aug 09 05:12:22 PM PDT 24 |
Finished | Aug 09 05:12:23 PM PDT 24 |
Peak memory | 205280 kb |
Host | smart-5c505223-d0ed-4263-b4b2-df8ade76f9d7 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151049034 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw. 4151049034 |
Directory | /workspace/16.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.4254379455 |
Short name | T388 |
Test name | |
Test status | |
Simulation time | 250788534 ps |
CPU time | 6.55 seconds |
Started | Aug 09 05:12:28 PM PDT 24 |
Finished | Aug 09 05:12:35 PM PDT 24 |
Peak memory | 205532 kb |
Host | smart-843eb4cb-9ee5-4488-bcd3-0f155c67070e |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254379455 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same _csr_outstanding.4254379455 |
Directory | /workspace/16.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.1300352773 |
Short name | T351 |
Test name | |
Test status | |
Simulation time | 124932831 ps |
CPU time | 3.03 seconds |
Started | Aug 09 05:12:20 PM PDT 24 |
Finished | Aug 09 05:12:23 PM PDT 24 |
Peak memory | 213944 kb |
Host | smart-e6d567a9-efb5-4210-b94d-edb772d0c495 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300352773 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.1300352773 |
Directory | /workspace/16.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.3216057582 |
Short name | T155 |
Test name | |
Test status | |
Simulation time | 4552245528 ps |
CPU time | 20.72 seconds |
Started | Aug 09 05:12:28 PM PDT 24 |
Finished | Aug 09 05:12:49 PM PDT 24 |
Peak memory | 213876 kb |
Host | smart-70a16bcc-9c2d-4ff2-a048-9cae98a7e3ce |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216057582 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.3 216057582 |
Directory | /workspace/16.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.185610248 |
Short name | T399 |
Test name | |
Test status | |
Simulation time | 106934816 ps |
CPU time | 3.34 seconds |
Started | Aug 09 05:12:34 PM PDT 24 |
Finished | Aug 09 05:12:37 PM PDT 24 |
Peak memory | 219116 kb |
Host | smart-6b2857ed-2a6e-4a8c-ab62-3929fe2b5fc1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185610248 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.185610248 |
Directory | /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.1911541913 |
Short name | T440 |
Test name | |
Test status | |
Simulation time | 222074911 ps |
CPU time | 2.75 seconds |
Started | Aug 09 05:12:32 PM PDT 24 |
Finished | Aug 09 05:12:35 PM PDT 24 |
Peak memory | 213700 kb |
Host | smart-0450225b-76ec-44e2-80ab-9aae854c1429 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911541913 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.1911541913 |
Directory | /workspace/17.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.1205900667 |
Short name | T384 |
Test name | |
Test status | |
Simulation time | 40671837093 ps |
CPU time | 110.5 seconds |
Started | Aug 09 05:12:28 PM PDT 24 |
Finished | Aug 09 05:14:19 PM PDT 24 |
Peak memory | 205840 kb |
Host | smart-1ee39476-1511-4819-9ec8-0b70a538af52 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205900667 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17 .rv_dm_jtag_dmi_csr_bit_bash.1205900667 |
Directory | /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.3336389396 |
Short name | T423 |
Test name | |
Test status | |
Simulation time | 1277845858 ps |
CPU time | 4.58 seconds |
Started | Aug 09 05:12:27 PM PDT 24 |
Finished | Aug 09 05:12:31 PM PDT 24 |
Peak memory | 205476 kb |
Host | smart-1334d2cb-1f7a-4fde-a462-3f7ad0ab2a3f |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336389396 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw. 3336389396 |
Directory | /workspace/17.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.1354400202 |
Short name | T366 |
Test name | |
Test status | |
Simulation time | 240271699 ps |
CPU time | 0.86 seconds |
Started | Aug 09 05:12:28 PM PDT 24 |
Finished | Aug 09 05:12:29 PM PDT 24 |
Peak memory | 205244 kb |
Host | smart-9b9d780e-b679-40e5-8d35-74c95716e508 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354400202 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw. 1354400202 |
Directory | /workspace/17.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.2493158077 |
Short name | T78 |
Test name | |
Test status | |
Simulation time | 456677740 ps |
CPU time | 4.1 seconds |
Started | Aug 09 05:12:31 PM PDT 24 |
Finished | Aug 09 05:12:35 PM PDT 24 |
Peak memory | 205576 kb |
Host | smart-93bfd2fb-ac6b-4a94-aebf-705489fd47ae |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493158077 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same _csr_outstanding.2493158077 |
Directory | /workspace/17.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.3648719510 |
Short name | T456 |
Test name | |
Test status | |
Simulation time | 457503630 ps |
CPU time | 2.79 seconds |
Started | Aug 09 05:12:27 PM PDT 24 |
Finished | Aug 09 05:12:30 PM PDT 24 |
Peak memory | 213908 kb |
Host | smart-bbb626b0-f58e-4454-91e8-109895331872 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648719510 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.3648719510 |
Directory | /workspace/17.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.764928922 |
Short name | T154 |
Test name | |
Test status | |
Simulation time | 4637214075 ps |
CPU time | 20.62 seconds |
Started | Aug 09 05:12:27 PM PDT 24 |
Finished | Aug 09 05:12:48 PM PDT 24 |
Peak memory | 213940 kb |
Host | smart-6a40d28f-6258-425e-9de7-64d69cb5e916 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764928922 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.764928922 |
Directory | /workspace/17.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.3989581108 |
Short name | T361 |
Test name | |
Test status | |
Simulation time | 537455871 ps |
CPU time | 3.6 seconds |
Started | Aug 09 05:12:29 PM PDT 24 |
Finished | Aug 09 05:12:32 PM PDT 24 |
Peak memory | 219456 kb |
Host | smart-2f1a24bd-d8df-43b4-b75a-0862e1c7f35c |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989581108 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.3989581108 |
Directory | /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.3212025165 |
Short name | T96 |
Test name | |
Test status | |
Simulation time | 902711226 ps |
CPU time | 1.57 seconds |
Started | Aug 09 05:12:28 PM PDT 24 |
Finished | Aug 09 05:12:30 PM PDT 24 |
Peak memory | 213736 kb |
Host | smart-286c41db-c258-4be4-a0a0-4c027833cf05 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212025165 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.3212025165 |
Directory | /workspace/18.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.1329118062 |
Short name | T342 |
Test name | |
Test status | |
Simulation time | 13713905695 ps |
CPU time | 21.16 seconds |
Started | Aug 09 05:12:28 PM PDT 24 |
Finished | Aug 09 05:12:49 PM PDT 24 |
Peak memory | 205416 kb |
Host | smart-1722a276-c3eb-470a-a926-4f9309f3ba80 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329118062 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18 .rv_dm_jtag_dmi_csr_bit_bash.1329118062 |
Directory | /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.1836057280 |
Short name | T376 |
Test name | |
Test status | |
Simulation time | 3489749371 ps |
CPU time | 8.35 seconds |
Started | Aug 09 05:12:35 PM PDT 24 |
Finished | Aug 09 05:12:44 PM PDT 24 |
Peak memory | 205528 kb |
Host | smart-57d1dc8c-7eb4-431b-8f36-5477b4ab04b5 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836057280 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw. 1836057280 |
Directory | /workspace/18.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.1546599581 |
Short name | T349 |
Test name | |
Test status | |
Simulation time | 197999048 ps |
CPU time | 0.81 seconds |
Started | Aug 09 05:12:33 PM PDT 24 |
Finished | Aug 09 05:12:34 PM PDT 24 |
Peak memory | 205132 kb |
Host | smart-637309cc-1e13-42b0-af2a-43d774f20c21 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546599581 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw. 1546599581 |
Directory | /workspace/18.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.1828876169 |
Short name | T452 |
Test name | |
Test status | |
Simulation time | 643095110 ps |
CPU time | 6.25 seconds |
Started | Aug 09 05:12:30 PM PDT 24 |
Finished | Aug 09 05:12:37 PM PDT 24 |
Peak memory | 205528 kb |
Host | smart-d6281abb-b6c1-4f08-8131-b69fd2812ccb |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828876169 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same _csr_outstanding.1828876169 |
Directory | /workspace/18.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.44051299 |
Short name | T411 |
Test name | |
Test status | |
Simulation time | 258155427 ps |
CPU time | 3.35 seconds |
Started | Aug 09 05:12:28 PM PDT 24 |
Finished | Aug 09 05:12:32 PM PDT 24 |
Peak memory | 213788 kb |
Host | smart-8d0ed52e-9b06-46f3-a04f-b865d2b22411 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44051299 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.44051299 |
Directory | /workspace/18.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.3191317757 |
Short name | T390 |
Test name | |
Test status | |
Simulation time | 178080946 ps |
CPU time | 2.56 seconds |
Started | Aug 09 05:12:29 PM PDT 24 |
Finished | Aug 09 05:12:31 PM PDT 24 |
Peak memory | 218944 kb |
Host | smart-ba57aed3-75b0-4547-b3e4-fcbe1e1e3832 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191317757 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.3191317757 |
Directory | /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.2670485953 |
Short name | T103 |
Test name | |
Test status | |
Simulation time | 256238479 ps |
CPU time | 1.52 seconds |
Started | Aug 09 05:12:27 PM PDT 24 |
Finished | Aug 09 05:12:28 PM PDT 24 |
Peak memory | 213804 kb |
Host | smart-33bf5a42-fcf1-48a5-9761-145c7897771a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670485953 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.2670485953 |
Directory | /workspace/19.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.1830521234 |
Short name | T311 |
Test name | |
Test status | |
Simulation time | 41885256328 ps |
CPU time | 29.62 seconds |
Started | Aug 09 05:12:29 PM PDT 24 |
Finished | Aug 09 05:12:58 PM PDT 24 |
Peak memory | 205612 kb |
Host | smart-f99a07a3-21bc-4c09-a3b1-d0c20517cbd8 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830521234 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19 .rv_dm_jtag_dmi_csr_bit_bash.1830521234 |
Directory | /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.1713757672 |
Short name | T389 |
Test name | |
Test status | |
Simulation time | 15152220935 ps |
CPU time | 42.08 seconds |
Started | Aug 09 05:12:35 PM PDT 24 |
Finished | Aug 09 05:13:18 PM PDT 24 |
Peak memory | 205544 kb |
Host | smart-e5222cc6-a9a2-4862-8e54-dbf8f5e2c025 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713757672 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw. 1713757672 |
Directory | /workspace/19.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.3093030722 |
Short name | T438 |
Test name | |
Test status | |
Simulation time | 282578950 ps |
CPU time | 1.4 seconds |
Started | Aug 09 05:12:27 PM PDT 24 |
Finished | Aug 09 05:12:29 PM PDT 24 |
Peak memory | 205196 kb |
Host | smart-94769f58-af63-4005-a3c5-add859be5f4f |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093030722 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw. 3093030722 |
Directory | /workspace/19.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.795889190 |
Short name | T110 |
Test name | |
Test status | |
Simulation time | 389139617 ps |
CPU time | 4.7 seconds |
Started | Aug 09 05:12:29 PM PDT 24 |
Finished | Aug 09 05:12:33 PM PDT 24 |
Peak memory | 205604 kb |
Host | smart-16edaaea-3e41-46e9-8937-4486244dc839 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795889190 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same_ csr_outstanding.795889190 |
Directory | /workspace/19.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.3953193157 |
Short name | T344 |
Test name | |
Test status | |
Simulation time | 317368993 ps |
CPU time | 4.47 seconds |
Started | Aug 09 05:12:27 PM PDT 24 |
Finished | Aug 09 05:12:31 PM PDT 24 |
Peak memory | 213848 kb |
Host | smart-8dae89a0-668d-4f1f-bc10-2240e02c9b92 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953193157 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.3953193157 |
Directory | /workspace/19.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.2250806240 |
Short name | T150 |
Test name | |
Test status | |
Simulation time | 1892468886 ps |
CPU time | 10.94 seconds |
Started | Aug 09 05:12:30 PM PDT 24 |
Finished | Aug 09 05:12:41 PM PDT 24 |
Peak memory | 213840 kb |
Host | smart-c894edb7-9fdb-487d-9bc6-85841a6c10b2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250806240 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.2 250806240 |
Directory | /workspace/19.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.3955951769 |
Short name | T346 |
Test name | |
Test status | |
Simulation time | 3462650832 ps |
CPU time | 31.43 seconds |
Started | Aug 09 05:11:56 PM PDT 24 |
Finished | Aug 09 05:12:27 PM PDT 24 |
Peak memory | 205312 kb |
Host | smart-b1775d08-1acc-4be6-ae81-7c9a5386daa6 |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955951769 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 2.rv_dm_csr_aliasing.3955951769 |
Directory | /workspace/2.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.409628223 |
Short name | T79 |
Test name | |
Test status | |
Simulation time | 7365546257 ps |
CPU time | 74.77 seconds |
Started | Aug 09 05:11:57 PM PDT 24 |
Finished | Aug 09 05:13:12 PM PDT 24 |
Peak memory | 205664 kb |
Host | smart-1e78cad4-7dd6-4927-a026-cde9fc9dcc53 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409628223 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.409628223 |
Directory | /workspace/2.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.1994000944 |
Short name | T97 |
Test name | |
Test status | |
Simulation time | 525270426 ps |
CPU time | 2.32 seconds |
Started | Aug 09 05:11:59 PM PDT 24 |
Finished | Aug 09 05:12:01 PM PDT 24 |
Peak memory | 213676 kb |
Host | smart-c956a991-c3f7-42e5-9e69-09c34052e776 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994000944 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.1994000944 |
Directory | /workspace/2.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.1439495134 |
Short name | T435 |
Test name | |
Test status | |
Simulation time | 338723946 ps |
CPU time | 3.69 seconds |
Started | Aug 09 05:11:57 PM PDT 24 |
Finished | Aug 09 05:12:01 PM PDT 24 |
Peak memory | 213820 kb |
Host | smart-392a148d-b76e-490c-9226-d5d570038c1b |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439495134 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.1439495134 |
Directory | /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.3894561789 |
Short name | T421 |
Test name | |
Test status | |
Simulation time | 51730279 ps |
CPU time | 2.21 seconds |
Started | Aug 09 05:11:56 PM PDT 24 |
Finished | Aug 09 05:11:58 PM PDT 24 |
Peak memory | 213596 kb |
Host | smart-99de5c1a-189a-4994-a058-96a1e3df0bb1 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894561789 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.3894561789 |
Directory | /workspace/2.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.397967376 |
Short name | T356 |
Test name | |
Test status | |
Simulation time | 188256303783 ps |
CPU time | 123.65 seconds |
Started | Aug 09 05:11:57 PM PDT 24 |
Finished | Aug 09 05:14:00 PM PDT 24 |
Peak memory | 208964 kb |
Host | smart-90e9552f-17a2-457f-99c1-9e1598ebbc4c |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397967376 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr _aliasing.397967376 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.638250170 |
Short name | T428 |
Test name | |
Test status | |
Simulation time | 2289272372 ps |
CPU time | 4.12 seconds |
Started | Aug 09 05:11:49 PM PDT 24 |
Finished | Aug 09 05:11:53 PM PDT 24 |
Peak memory | 205472 kb |
Host | smart-fd371144-52d5-4ec9-a26f-0d0981246db9 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638250170 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.r v_dm_jtag_dmi_csr_bit_bash.638250170 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.1596684616 |
Short name | T90 |
Test name | |
Test status | |
Simulation time | 20040228707 ps |
CPU time | 16.08 seconds |
Started | Aug 09 05:11:49 PM PDT 24 |
Finished | Aug 09 05:12:05 PM PDT 24 |
Peak memory | 205560 kb |
Host | smart-665c2d0d-1650-425e-a8c6-3bf0110fdb39 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596684616 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs r_hw_reset.1596684616 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.2255236854 |
Short name | T317 |
Test name | |
Test status | |
Simulation time | 937548159 ps |
CPU time | 1.92 seconds |
Started | Aug 09 05:11:49 PM PDT 24 |
Finished | Aug 09 05:11:51 PM PDT 24 |
Peak memory | 205424 kb |
Host | smart-cb45e86b-5985-4db4-8384-895cdfe171a4 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255236854 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.2 255236854 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.539737889 |
Short name | T60 |
Test name | |
Test status | |
Simulation time | 427552533 ps |
CPU time | 1.74 seconds |
Started | Aug 09 05:11:49 PM PDT 24 |
Finished | Aug 09 05:11:51 PM PDT 24 |
Peak memory | 205276 kb |
Host | smart-040f0f4b-c9b1-40b2-9415-8527f020655a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539737889 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr _aliasing.539737889 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.10643480 |
Short name | T337 |
Test name | |
Test status | |
Simulation time | 26953253146 ps |
CPU time | 22.62 seconds |
Started | Aug 09 05:11:52 PM PDT 24 |
Finished | Aug 09 05:12:15 PM PDT 24 |
Peak memory | 205576 kb |
Host | smart-c55ec0c5-faee-46f0-bb7c-04469d3a9676 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10643480 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_ bit_bash.10643480 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.1281512571 |
Short name | T408 |
Test name | |
Test status | |
Simulation time | 284898369 ps |
CPU time | 0.96 seconds |
Started | Aug 09 05:11:49 PM PDT 24 |
Finished | Aug 09 05:11:50 PM PDT 24 |
Peak memory | 205612 kb |
Host | smart-60cadcea-0053-40fc-840e-a6f20f454795 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281512571 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs r_hw_reset.1281512571 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2899181066 |
Short name | T310 |
Test name | |
Test status | |
Simulation time | 207458056 ps |
CPU time | 0.88 seconds |
Started | Aug 09 05:11:54 PM PDT 24 |
Finished | Aug 09 05:11:55 PM PDT 24 |
Peak memory | 205264 kb |
Host | smart-229b170e-3c50-42e7-be78-e19adf9699cd |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899181066 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.2 899181066 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.3352138303 |
Short name | T433 |
Test name | |
Test status | |
Simulation time | 71687972 ps |
CPU time | 0.82 seconds |
Started | Aug 09 05:11:56 PM PDT 24 |
Finished | Aug 09 05:11:57 PM PDT 24 |
Peak memory | 205284 kb |
Host | smart-fd05e971-13d7-4532-bb0c-27e9bf3bb8f0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352138303 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par tial_access.3352138303 |
Directory | /workspace/2.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.3066161025 |
Short name | T407 |
Test name | |
Test status | |
Simulation time | 58147201 ps |
CPU time | 0.67 seconds |
Started | Aug 09 05:11:56 PM PDT 24 |
Finished | Aug 09 05:11:57 PM PDT 24 |
Peak memory | 205236 kb |
Host | smart-56372b18-f7c4-48d9-a9df-8bf1da99a781 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066161025 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.3066161025 |
Directory | /workspace/2.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.3471999994 |
Short name | T449 |
Test name | |
Test status | |
Simulation time | 1080962397 ps |
CPU time | 8.05 seconds |
Started | Aug 09 05:11:56 PM PDT 24 |
Finished | Aug 09 05:12:04 PM PDT 24 |
Peak memory | 205860 kb |
Host | smart-5d04b0ae-bd7a-44fb-be45-b0070211cd72 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471999994 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_ csr_outstanding.3471999994 |
Directory | /workspace/2.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.231585634 |
Short name | T341 |
Test name | |
Test status | |
Simulation time | 58330462643 ps |
CPU time | 51.17 seconds |
Started | Aug 09 05:11:54 PM PDT 24 |
Finished | Aug 09 05:12:46 PM PDT 24 |
Peak memory | 223468 kb |
Host | smart-1d59e46d-ee67-491c-8dec-492515f0502f |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231585634 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.231585634 |
Directory | /workspace/2.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.805461026 |
Short name | T329 |
Test name | |
Test status | |
Simulation time | 2848934250 ps |
CPU time | 6.99 seconds |
Started | Aug 09 05:11:57 PM PDT 24 |
Finished | Aug 09 05:12:04 PM PDT 24 |
Peak memory | 213892 kb |
Host | smart-e9a21606-0c32-41d9-be39-46ba80648594 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805461026 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.805461026 |
Directory | /workspace/2.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.2605659108 |
Short name | T158 |
Test name | |
Test status | |
Simulation time | 6019772788 ps |
CPU time | 23.79 seconds |
Started | Aug 09 05:11:58 PM PDT 24 |
Finished | Aug 09 05:12:22 PM PDT 24 |
Peak memory | 213836 kb |
Host | smart-f5a76c7a-74cc-4840-8bc7-1af774144695 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605659108 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.2605659108 |
Directory | /workspace/2.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.3649220484 |
Short name | T432 |
Test name | |
Test status | |
Simulation time | 1642176560 ps |
CPU time | 66.65 seconds |
Started | Aug 09 05:11:55 PM PDT 24 |
Finished | Aug 09 05:13:01 PM PDT 24 |
Peak memory | 218600 kb |
Host | smart-a11ebaea-1df5-490f-8e3e-1f9f3748d2c2 |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649220484 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 3.rv_dm_csr_aliasing.3649220484 |
Directory | /workspace/3.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1473760607 |
Short name | T84 |
Test name | |
Test status | |
Simulation time | 1510720810 ps |
CPU time | 28.75 seconds |
Started | Aug 09 05:12:00 PM PDT 24 |
Finished | Aug 09 05:12:29 PM PDT 24 |
Peak memory | 205476 kb |
Host | smart-9256221d-2022-4980-82d4-dcc6fd2a2ae9 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473760607 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.1473760607 |
Directory | /workspace/3.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.513086340 |
Short name | T83 |
Test name | |
Test status | |
Simulation time | 69603874 ps |
CPU time | 1.68 seconds |
Started | Aug 09 05:11:56 PM PDT 24 |
Finished | Aug 09 05:11:58 PM PDT 24 |
Peak memory | 213680 kb |
Host | smart-8b352768-657c-4514-a5d0-f1abfa8bee9b |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513086340 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.513086340 |
Directory | /workspace/3.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.1769396673 |
Short name | T444 |
Test name | |
Test status | |
Simulation time | 230300376 ps |
CPU time | 4.58 seconds |
Started | Aug 09 05:11:56 PM PDT 24 |
Finished | Aug 09 05:12:01 PM PDT 24 |
Peak memory | 220304 kb |
Host | smart-94b2e87d-45e1-4f73-ac8b-0e7b4f9e358a |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769396673 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.1769396673 |
Directory | /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.1872612281 |
Short name | T426 |
Test name | |
Test status | |
Simulation time | 181586014 ps |
CPU time | 1.6 seconds |
Started | Aug 09 05:11:55 PM PDT 24 |
Finished | Aug 09 05:11:57 PM PDT 24 |
Peak memory | 213660 kb |
Host | smart-8b0a5e6e-8535-4d30-b49d-71762f4db805 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872612281 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.1872612281 |
Directory | /workspace/3.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.1891346091 |
Short name | T391 |
Test name | |
Test status | |
Simulation time | 53820208652 ps |
CPU time | 28.77 seconds |
Started | Aug 09 05:11:56 PM PDT 24 |
Finished | Aug 09 05:12:25 PM PDT 24 |
Peak memory | 205492 kb |
Host | smart-8b70f9a9-ece7-476e-960b-a11ff2dd7b68 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891346091 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs r_aliasing.1891346091 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.1841933599 |
Short name | T331 |
Test name | |
Test status | |
Simulation time | 3617821616 ps |
CPU time | 6.31 seconds |
Started | Aug 09 05:11:57 PM PDT 24 |
Finished | Aug 09 05:12:03 PM PDT 24 |
Peak memory | 205524 kb |
Host | smart-3190c2f3-97e2-49e2-be5c-dfd80ca28a47 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841933599 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3. rv_dm_jtag_dmi_csr_bit_bash.1841933599 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.1118674703 |
Short name | T93 |
Test name | |
Test status | |
Simulation time | 5288815939 ps |
CPU time | 5.15 seconds |
Started | Aug 09 05:11:54 PM PDT 24 |
Finished | Aug 09 05:11:59 PM PDT 24 |
Peak memory | 205636 kb |
Host | smart-c1ecdcdf-c495-477a-aa69-9931b764a8be |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118674703 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs r_hw_reset.1118674703 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.1702990971 |
Short name | T393 |
Test name | |
Test status | |
Simulation time | 12423981448 ps |
CPU time | 9.86 seconds |
Started | Aug 09 05:11:56 PM PDT 24 |
Finished | Aug 09 05:12:06 PM PDT 24 |
Peak memory | 205552 kb |
Host | smart-19fc19ee-a9aa-4ae1-935b-741f6ddf7eb2 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702990971 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.1 702990971 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.3307451770 |
Short name | T369 |
Test name | |
Test status | |
Simulation time | 1195282249 ps |
CPU time | 2.35 seconds |
Started | Aug 09 05:11:57 PM PDT 24 |
Finished | Aug 09 05:12:00 PM PDT 24 |
Peak memory | 205224 kb |
Host | smart-e3cea2d4-24fa-411c-abbb-863eb8942c18 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307451770 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs r_aliasing.3307451770 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.3322985942 |
Short name | T362 |
Test name | |
Test status | |
Simulation time | 3184419645 ps |
CPU time | 6.34 seconds |
Started | Aug 09 05:11:56 PM PDT 24 |
Finished | Aug 09 05:12:02 PM PDT 24 |
Peak memory | 205604 kb |
Host | smart-cd0f3ba9-d0b3-43e0-9136-c6d1b7c017c8 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322985942 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs r_bit_bash.3322985942 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.777897729 |
Short name | T406 |
Test name | |
Test status | |
Simulation time | 131436209 ps |
CPU time | 1.01 seconds |
Started | Aug 09 05:11:58 PM PDT 24 |
Finished | Aug 09 05:11:59 PM PDT 24 |
Peak memory | 205248 kb |
Host | smart-db38f025-e62c-414f-a5d7-78cc8574d8d5 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777897729 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr _hw_reset.777897729 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.2900113756 |
Short name | T383 |
Test name | |
Test status | |
Simulation time | 482105572 ps |
CPU time | 1.4 seconds |
Started | Aug 09 05:11:54 PM PDT 24 |
Finished | Aug 09 05:11:56 PM PDT 24 |
Peak memory | 205192 kb |
Host | smart-f98aa1a6-7ee5-40f6-b300-dfea57904e96 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900113756 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.2 900113756 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.2827465034 |
Short name | T309 |
Test name | |
Test status | |
Simulation time | 135144467 ps |
CPU time | 0.68 seconds |
Started | Aug 09 05:11:57 PM PDT 24 |
Finished | Aug 09 05:11:57 PM PDT 24 |
Peak memory | 205292 kb |
Host | smart-db973d9d-3700-4b96-b926-47bb414d8759 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827465034 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par tial_access.2827465034 |
Directory | /workspace/3.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.4195615449 |
Short name | T382 |
Test name | |
Test status | |
Simulation time | 166206527 ps |
CPU time | 0.69 seconds |
Started | Aug 09 05:11:55 PM PDT 24 |
Finished | Aug 09 05:11:56 PM PDT 24 |
Peak memory | 205296 kb |
Host | smart-9070a552-a25c-4de9-9080-90532863b835 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195615449 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.4195615449 |
Directory | /workspace/3.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.533636454 |
Short name | T457 |
Test name | |
Test status | |
Simulation time | 176882380 ps |
CPU time | 3.59 seconds |
Started | Aug 09 05:11:56 PM PDT 24 |
Finished | Aug 09 05:12:00 PM PDT 24 |
Peak memory | 205684 kb |
Host | smart-aea9f255-3562-43b8-b305-14ae414313dc |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533636454 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_c sr_outstanding.533636454 |
Directory | /workspace/3.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.4038809673 |
Short name | T313 |
Test name | |
Test status | |
Simulation time | 55598428264 ps |
CPU time | 159.79 seconds |
Started | Aug 09 05:11:59 PM PDT 24 |
Finished | Aug 09 05:14:39 PM PDT 24 |
Peak memory | 222036 kb |
Host | smart-d32aabbc-0b80-420c-b62d-5f67b3f6e71a |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038809673 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.4038809673 |
Directory | /workspace/3.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.197655201 |
Short name | T448 |
Test name | |
Test status | |
Simulation time | 631250020 ps |
CPU time | 6.43 seconds |
Started | Aug 09 05:11:55 PM PDT 24 |
Finished | Aug 09 05:12:01 PM PDT 24 |
Peak memory | 213872 kb |
Host | smart-005e9f67-5e20-4e16-a734-b4a185270211 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197655201 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.197655201 |
Directory | /workspace/3.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3451610174 |
Short name | T115 |
Test name | |
Test status | |
Simulation time | 2673393951 ps |
CPU time | 14.33 seconds |
Started | Aug 09 05:12:00 PM PDT 24 |
Finished | Aug 09 05:12:14 PM PDT 24 |
Peak memory | 213796 kb |
Host | smart-7b50a535-7523-4b7a-afbb-b285022fa69b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451610174 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.3451610174 |
Directory | /workspace/3.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.4260956082 |
Short name | T425 |
Test name | |
Test status | |
Simulation time | 38503399781 ps |
CPU time | 78.27 seconds |
Started | Aug 09 05:12:02 PM PDT 24 |
Finished | Aug 09 05:13:20 PM PDT 24 |
Peak memory | 205696 kb |
Host | smart-69ea43a0-4204-4e64-b6b4-1a795953d530 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260956082 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.4260956082 |
Directory | /workspace/4.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.1417666957 |
Short name | T104 |
Test name | |
Test status | |
Simulation time | 191218248 ps |
CPU time | 1.6 seconds |
Started | Aug 09 05:12:01 PM PDT 24 |
Finished | Aug 09 05:12:03 PM PDT 24 |
Peak memory | 213676 kb |
Host | smart-6db22e0e-ab60-4d8d-85c8-9d490185a0b0 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417666957 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.1417666957 |
Directory | /workspace/4.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2031907679 |
Short name | T379 |
Test name | |
Test status | |
Simulation time | 175787225 ps |
CPU time | 4.89 seconds |
Started | Aug 09 05:12:04 PM PDT 24 |
Finished | Aug 09 05:12:09 PM PDT 24 |
Peak memory | 213856 kb |
Host | smart-6ae8502f-cb5b-4ca4-8c20-0cf36ac21243 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031907679 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.2031907679 |
Directory | /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.1220722284 |
Short name | T461 |
Test name | |
Test status | |
Simulation time | 190170407 ps |
CPU time | 2.49 seconds |
Started | Aug 09 05:12:02 PM PDT 24 |
Finished | Aug 09 05:12:05 PM PDT 24 |
Peak memory | 213728 kb |
Host | smart-1b89a88b-b28c-4746-9ec1-7d97ee9ee207 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220722284 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.1220722284 |
Directory | /workspace/4.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.957746190 |
Short name | T312 |
Test name | |
Test status | |
Simulation time | 57244445323 ps |
CPU time | 61.87 seconds |
Started | Aug 09 05:12:00 PM PDT 24 |
Finished | Aug 09 05:13:02 PM PDT 24 |
Peak memory | 205528 kb |
Host | smart-16f5bee5-5f9b-45de-af1f-8833b4932b73 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957746190 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr _aliasing.957746190 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.2976024311 |
Short name | T372 |
Test name | |
Test status | |
Simulation time | 28244942931 ps |
CPU time | 20.47 seconds |
Started | Aug 09 05:12:01 PM PDT 24 |
Finished | Aug 09 05:12:22 PM PDT 24 |
Peak memory | 205584 kb |
Host | smart-f847eca4-dba6-4b05-b845-72f98ae1834d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976024311 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4. rv_dm_jtag_dmi_csr_bit_bash.2976024311 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.1268340465 |
Short name | T377 |
Test name | |
Test status | |
Simulation time | 9200008652 ps |
CPU time | 8.51 seconds |
Started | Aug 09 05:12:04 PM PDT 24 |
Finished | Aug 09 05:12:13 PM PDT 24 |
Peak memory | 205724 kb |
Host | smart-b0f5f376-8f82-4a32-a41b-828c145f27a5 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268340465 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs r_hw_reset.1268340465 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.796626403 |
Short name | T314 |
Test name | |
Test status | |
Simulation time | 1757865829 ps |
CPU time | 5.63 seconds |
Started | Aug 09 05:12:04 PM PDT 24 |
Finished | Aug 09 05:12:09 PM PDT 24 |
Peak memory | 205388 kb |
Host | smart-b9478148-e9c5-4c1c-8331-125714661ba9 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796626403 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.796626403 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.760458209 |
Short name | T316 |
Test name | |
Test status | |
Simulation time | 1011773493 ps |
CPU time | 1.36 seconds |
Started | Aug 09 05:12:01 PM PDT 24 |
Finished | Aug 09 05:12:03 PM PDT 24 |
Peak memory | 205184 kb |
Host | smart-b4d569bd-ed44-46ad-b64e-fa2e26d53dcd |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760458209 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr _aliasing.760458209 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2402682196 |
Short name | T371 |
Test name | |
Test status | |
Simulation time | 6749785375 ps |
CPU time | 8.11 seconds |
Started | Aug 09 05:12:01 PM PDT 24 |
Finished | Aug 09 05:12:10 PM PDT 24 |
Peak memory | 205564 kb |
Host | smart-e92faf11-02cc-4130-b669-25d0679c49ad |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402682196 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs r_bit_bash.2402682196 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.1787079663 |
Short name | T326 |
Test name | |
Test status | |
Simulation time | 789123733 ps |
CPU time | 1.26 seconds |
Started | Aug 09 05:11:56 PM PDT 24 |
Finished | Aug 09 05:11:58 PM PDT 24 |
Peak memory | 205208 kb |
Host | smart-19854455-5a34-4ca5-b59d-f72b315fbef0 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787079663 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs r_hw_reset.1787079663 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2952622657 |
Short name | T417 |
Test name | |
Test status | |
Simulation time | 283718097 ps |
CPU time | 0.86 seconds |
Started | Aug 09 05:12:00 PM PDT 24 |
Finished | Aug 09 05:12:01 PM PDT 24 |
Peak memory | 205228 kb |
Host | smart-def9ab63-9ae2-42e8-bcc0-25517df3d434 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952622657 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.2 952622657 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.2998943155 |
Short name | T400 |
Test name | |
Test status | |
Simulation time | 47676206 ps |
CPU time | 0.77 seconds |
Started | Aug 09 05:12:03 PM PDT 24 |
Finished | Aug 09 05:12:04 PM PDT 24 |
Peak memory | 205340 kb |
Host | smart-654a4d05-2151-471a-a755-85a6517fe55a |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998943155 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par tial_access.2998943155 |
Directory | /workspace/4.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.291548278 |
Short name | T395 |
Test name | |
Test status | |
Simulation time | 29092498 ps |
CPU time | 0.69 seconds |
Started | Aug 09 05:12:02 PM PDT 24 |
Finished | Aug 09 05:12:02 PM PDT 24 |
Peak memory | 205220 kb |
Host | smart-3276d617-5a69-432b-819d-de849f847924 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291548278 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.291548278 |
Directory | /workspace/4.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.241654518 |
Short name | T464 |
Test name | |
Test status | |
Simulation time | 535796959 ps |
CPU time | 7.26 seconds |
Started | Aug 09 05:12:02 PM PDT 24 |
Finished | Aug 09 05:12:10 PM PDT 24 |
Peak memory | 205836 kb |
Host | smart-454a3071-1b84-4d40-bbec-b28e8d6615ff |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241654518 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_c sr_outstanding.241654518 |
Directory | /workspace/4.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.154817606 |
Short name | T161 |
Test name | |
Test status | |
Simulation time | 20270324692 ps |
CPU time | 189.43 seconds |
Started | Aug 09 05:12:03 PM PDT 24 |
Finished | Aug 09 05:15:12 PM PDT 24 |
Peak memory | 222192 kb |
Host | smart-f368c79b-3b9e-4557-a70a-4f090fc73421 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154817606 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.154817606 |
Directory | /workspace/4.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.752476949 |
Short name | T348 |
Test name | |
Test status | |
Simulation time | 153043589 ps |
CPU time | 4.53 seconds |
Started | Aug 09 05:12:02 PM PDT 24 |
Finished | Aug 09 05:12:06 PM PDT 24 |
Peak memory | 213816 kb |
Host | smart-ace759b4-153a-45e1-8267-6f82b25e8e87 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752476949 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.752476949 |
Directory | /workspace/4.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1996242727 |
Short name | T148 |
Test name | |
Test status | |
Simulation time | 3132081228 ps |
CPU time | 24.48 seconds |
Started | Aug 09 05:12:05 PM PDT 24 |
Finished | Aug 09 05:12:30 PM PDT 24 |
Peak memory | 213908 kb |
Host | smart-f6aaea51-c2f6-46f2-8cc2-dd77da565471 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996242727 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.1996242727 |
Directory | /workspace/4.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.1717651600 |
Short name | T434 |
Test name | |
Test status | |
Simulation time | 117929712 ps |
CPU time | 2.42 seconds |
Started | Aug 09 05:12:01 PM PDT 24 |
Finished | Aug 09 05:12:04 PM PDT 24 |
Peak memory | 221924 kb |
Host | smart-875cf140-94fc-4654-b790-40401a929a76 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717651600 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.1717651600 |
Directory | /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.2425720926 |
Short name | T418 |
Test name | |
Test status | |
Simulation time | 222001704 ps |
CPU time | 1.45 seconds |
Started | Aug 09 05:12:04 PM PDT 24 |
Finished | Aug 09 05:12:05 PM PDT 24 |
Peak memory | 213680 kb |
Host | smart-6147ac4a-f259-47e0-9a1b-6f925cf27f33 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425720926 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.2425720926 |
Directory | /workspace/5.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.564145521 |
Short name | T307 |
Test name | |
Test status | |
Simulation time | 16864051983 ps |
CPU time | 23.5 seconds |
Started | Aug 09 05:12:03 PM PDT 24 |
Finished | Aug 09 05:12:27 PM PDT 24 |
Peak memory | 205444 kb |
Host | smart-03f55b46-5c80-4887-ae3b-feff3dfd5342 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564145521 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.r v_dm_jtag_dmi_csr_bit_bash.564145521 |
Directory | /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.4091254467 |
Short name | T354 |
Test name | |
Test status | |
Simulation time | 2547978371 ps |
CPU time | 3.18 seconds |
Started | Aug 09 05:12:03 PM PDT 24 |
Finished | Aug 09 05:12:06 PM PDT 24 |
Peak memory | 205520 kb |
Host | smart-d6afd24b-9313-4b4b-bc49-93db277c73e9 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091254467 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.4 091254467 |
Directory | /workspace/5.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.1989280742 |
Short name | T352 |
Test name | |
Test status | |
Simulation time | 333430876 ps |
CPU time | 0.93 seconds |
Started | Aug 09 05:12:00 PM PDT 24 |
Finished | Aug 09 05:12:01 PM PDT 24 |
Peak memory | 205236 kb |
Host | smart-dd8868d8-061f-4af3-a8dc-2c03fb145875 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989280742 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.1 989280742 |
Directory | /workspace/5.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1058773184 |
Short name | T109 |
Test name | |
Test status | |
Simulation time | 176467691 ps |
CPU time | 3.63 seconds |
Started | Aug 09 05:12:05 PM PDT 24 |
Finished | Aug 09 05:12:09 PM PDT 24 |
Peak memory | 205672 kb |
Host | smart-b1fbccd9-1c6c-495e-9f5a-4ed9bac051b1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058773184 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_ csr_outstanding.1058773184 |
Directory | /workspace/5.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.2762242238 |
Short name | T460 |
Test name | |
Test status | |
Simulation time | 25363166540 ps |
CPU time | 104.83 seconds |
Started | Aug 09 05:12:03 PM PDT 24 |
Finished | Aug 09 05:13:48 PM PDT 24 |
Peak memory | 222052 kb |
Host | smart-4159c12f-c53a-4583-a873-9b3909f592bd |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762242238 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.2762242238 |
Directory | /workspace/5.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.2664212344 |
Short name | T424 |
Test name | |
Test status | |
Simulation time | 278333711 ps |
CPU time | 2.61 seconds |
Started | Aug 09 05:12:02 PM PDT 24 |
Finished | Aug 09 05:12:05 PM PDT 24 |
Peak memory | 221960 kb |
Host | smart-7ccb4050-d1f2-48ad-8d20-1d76391a18f6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664212344 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.2664212344 |
Directory | /workspace/5.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.1062148027 |
Short name | T443 |
Test name | |
Test status | |
Simulation time | 3744175093 ps |
CPU time | 10.16 seconds |
Started | Aug 09 05:12:03 PM PDT 24 |
Finished | Aug 09 05:12:13 PM PDT 24 |
Peak memory | 213876 kb |
Host | smart-c934cedf-0d3a-4d79-bd99-7e0213c0c360 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062148027 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.1062148027 |
Directory | /workspace/5.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.3292630669 |
Short name | T114 |
Test name | |
Test status | |
Simulation time | 174067743 ps |
CPU time | 2.53 seconds |
Started | Aug 09 05:12:09 PM PDT 24 |
Finished | Aug 09 05:12:11 PM PDT 24 |
Peak memory | 222104 kb |
Host | smart-ef3b779f-e604-4511-a925-51b0fd2e6710 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292630669 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.3292630669 |
Directory | /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.3509186316 |
Short name | T82 |
Test name | |
Test status | |
Simulation time | 104637182 ps |
CPU time | 1.53 seconds |
Started | Aug 09 05:12:08 PM PDT 24 |
Finished | Aug 09 05:12:10 PM PDT 24 |
Peak memory | 213636 kb |
Host | smart-f43330f5-281f-472a-92c9-e1c088a8773a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509186316 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.3509186316 |
Directory | /workspace/6.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.1222782025 |
Short name | T367 |
Test name | |
Test status | |
Simulation time | 3091120263 ps |
CPU time | 3.68 seconds |
Started | Aug 09 05:12:03 PM PDT 24 |
Finished | Aug 09 05:12:07 PM PDT 24 |
Peak memory | 205484 kb |
Host | smart-a94dc3d3-b0f6-4973-b19d-6ee07a443e97 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222782025 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6. rv_dm_jtag_dmi_csr_bit_bash.1222782025 |
Directory | /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2210465386 |
Short name | T419 |
Test name | |
Test status | |
Simulation time | 1050022381 ps |
CPU time | 1.74 seconds |
Started | Aug 09 05:12:01 PM PDT 24 |
Finished | Aug 09 05:12:03 PM PDT 24 |
Peak memory | 205316 kb |
Host | smart-d474605b-a43d-446b-baa7-0118ca948e4d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210465386 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.2 210465386 |
Directory | /workspace/6.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.1077612629 |
Short name | T322 |
Test name | |
Test status | |
Simulation time | 997796348 ps |
CPU time | 3.32 seconds |
Started | Aug 09 05:12:01 PM PDT 24 |
Finished | Aug 09 05:12:04 PM PDT 24 |
Peak memory | 205196 kb |
Host | smart-ed5b9182-0dc0-4227-85d9-75b6a2ba6dc7 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077612629 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.1 077612629 |
Directory | /workspace/6.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2029809774 |
Short name | T111 |
Test name | |
Test status | |
Simulation time | 2713854441 ps |
CPU time | 4.28 seconds |
Started | Aug 09 05:12:08 PM PDT 24 |
Finished | Aug 09 05:12:13 PM PDT 24 |
Peak memory | 205720 kb |
Host | smart-364d319e-a099-4054-a1f0-b528a077843b |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029809774 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_ csr_outstanding.2029809774 |
Directory | /workspace/6.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.1887148189 |
Short name | T160 |
Test name | |
Test status | |
Simulation time | 34658816205 ps |
CPU time | 56.18 seconds |
Started | Aug 09 05:12:03 PM PDT 24 |
Finished | Aug 09 05:12:59 PM PDT 24 |
Peak memory | 222108 kb |
Host | smart-07150a9e-78fe-41c8-ad6b-32baf3d878ab |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887148189 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.1887148189 |
Directory | /workspace/6.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.1844298971 |
Short name | T77 |
Test name | |
Test status | |
Simulation time | 198913505 ps |
CPU time | 2.77 seconds |
Started | Aug 09 05:12:01 PM PDT 24 |
Finished | Aug 09 05:12:04 PM PDT 24 |
Peak memory | 216204 kb |
Host | smart-48109c4e-52e2-4ba7-b440-99b0f6c184e2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844298971 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.1844298971 |
Directory | /workspace/6.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.1650632762 |
Short name | T118 |
Test name | |
Test status | |
Simulation time | 864230605 ps |
CPU time | 10.51 seconds |
Started | Aug 09 05:12:03 PM PDT 24 |
Finished | Aug 09 05:12:13 PM PDT 24 |
Peak memory | 213676 kb |
Host | smart-8b0785cf-7d97-4303-91cb-eb9e5f7e2564 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650632762 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.1650632762 |
Directory | /workspace/6.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3806814436 |
Short name | T414 |
Test name | |
Test status | |
Simulation time | 125333569 ps |
CPU time | 2.28 seconds |
Started | Aug 09 05:12:08 PM PDT 24 |
Finished | Aug 09 05:12:11 PM PDT 24 |
Peak memory | 216196 kb |
Host | smart-906c4864-da92-4760-b571-d6e0c7ef5563 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806814436 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.3806814436 |
Directory | /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.16960149 |
Short name | T335 |
Test name | |
Test status | |
Simulation time | 251425230 ps |
CPU time | 1.67 seconds |
Started | Aug 09 05:12:06 PM PDT 24 |
Finished | Aug 09 05:12:08 PM PDT 24 |
Peak memory | 213696 kb |
Host | smart-fdb6cf75-4071-4ab5-a291-1881af111554 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16960149 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.16960149 |
Directory | /workspace/7.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.755236549 |
Short name | T373 |
Test name | |
Test status | |
Simulation time | 6000387581 ps |
CPU time | 3.42 seconds |
Started | Aug 09 05:12:07 PM PDT 24 |
Finished | Aug 09 05:12:11 PM PDT 24 |
Peak memory | 205584 kb |
Host | smart-c9f2a917-1db1-4fdd-82a7-b005c141845b |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755236549 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.r v_dm_jtag_dmi_csr_bit_bash.755236549 |
Directory | /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.3716230987 |
Short name | T374 |
Test name | |
Test status | |
Simulation time | 5297498217 ps |
CPU time | 5.44 seconds |
Started | Aug 09 05:12:09 PM PDT 24 |
Finished | Aug 09 05:12:15 PM PDT 24 |
Peak memory | 205480 kb |
Host | smart-9c973065-0e57-495b-a395-7ac90a1058f7 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716230987 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.3 716230987 |
Directory | /workspace/7.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.3665378503 |
Short name | T427 |
Test name | |
Test status | |
Simulation time | 185675475 ps |
CPU time | 0.89 seconds |
Started | Aug 09 05:12:08 PM PDT 24 |
Finished | Aug 09 05:12:09 PM PDT 24 |
Peak memory | 205240 kb |
Host | smart-6db70bb1-09e9-4e6d-85b7-0f9b896cbba0 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665378503 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.3 665378503 |
Directory | /workspace/7.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.2454671365 |
Short name | T108 |
Test name | |
Test status | |
Simulation time | 1770193982 ps |
CPU time | 4 seconds |
Started | Aug 09 05:12:09 PM PDT 24 |
Finished | Aug 09 05:12:13 PM PDT 24 |
Peak memory | 205380 kb |
Host | smart-677a267d-679a-4f92-ae54-38a3aa18be05 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454671365 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_ csr_outstanding.2454671365 |
Directory | /workspace/7.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.4217735800 |
Short name | T429 |
Test name | |
Test status | |
Simulation time | 40701295301 ps |
CPU time | 22.47 seconds |
Started | Aug 09 05:12:07 PM PDT 24 |
Finished | Aug 09 05:12:30 PM PDT 24 |
Peak memory | 213940 kb |
Host | smart-4ed60611-8217-40a0-8921-4def966bb3e4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217735800 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.4217735800 |
Directory | /workspace/7.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.2426667781 |
Short name | T387 |
Test name | |
Test status | |
Simulation time | 138960821 ps |
CPU time | 2.72 seconds |
Started | Aug 09 05:12:06 PM PDT 24 |
Finished | Aug 09 05:12:09 PM PDT 24 |
Peak memory | 213856 kb |
Host | smart-3ed94448-7ca7-4904-bec2-c9d5c9e7a9b2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426667781 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.2426667781 |
Directory | /workspace/7.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2024560873 |
Short name | T153 |
Test name | |
Test status | |
Simulation time | 3189425803 ps |
CPU time | 13.35 seconds |
Started | Aug 09 05:12:08 PM PDT 24 |
Finished | Aug 09 05:12:21 PM PDT 24 |
Peak memory | 221492 kb |
Host | smart-2fb43c7f-966c-4fca-9aa2-5a71415eb265 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024560873 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.2024560873 |
Directory | /workspace/7.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.1835813797 |
Short name | T116 |
Test name | |
Test status | |
Simulation time | 369925128 ps |
CPU time | 4.68 seconds |
Started | Aug 09 05:12:09 PM PDT 24 |
Finished | Aug 09 05:12:14 PM PDT 24 |
Peak memory | 221980 kb |
Host | smart-06049bcd-036d-424f-9f69-84feada22aff |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835813797 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.1835813797 |
Directory | /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.2834838981 |
Short name | T365 |
Test name | |
Test status | |
Simulation time | 202139060 ps |
CPU time | 2.72 seconds |
Started | Aug 09 05:12:09 PM PDT 24 |
Finished | Aug 09 05:12:11 PM PDT 24 |
Peak memory | 213800 kb |
Host | smart-e5dc67de-b7f5-487e-a573-3ff622ae14d1 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834838981 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.2834838981 |
Directory | /workspace/8.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.2396001910 |
Short name | T463 |
Test name | |
Test status | |
Simulation time | 3644182574 ps |
CPU time | 5.06 seconds |
Started | Aug 09 05:12:08 PM PDT 24 |
Finished | Aug 09 05:12:13 PM PDT 24 |
Peak memory | 205488 kb |
Host | smart-026a6ef2-ac54-40db-bab5-bbac938c13d5 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396001910 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8. rv_dm_jtag_dmi_csr_bit_bash.2396001910 |
Directory | /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.104825096 |
Short name | T330 |
Test name | |
Test status | |
Simulation time | 7625455857 ps |
CPU time | 4.83 seconds |
Started | Aug 09 05:12:09 PM PDT 24 |
Finished | Aug 09 05:12:13 PM PDT 24 |
Peak memory | 205412 kb |
Host | smart-5db73fa3-52ae-41a1-8543-12faf09dfbea |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104825096 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.104825096 |
Directory | /workspace/8.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.640265419 |
Short name | T333 |
Test name | |
Test status | |
Simulation time | 254393041 ps |
CPU time | 0.76 seconds |
Started | Aug 09 05:12:08 PM PDT 24 |
Finished | Aug 09 05:12:09 PM PDT 24 |
Peak memory | 205276 kb |
Host | smart-d38c959d-a095-4d52-b773-30dcf0fcd005 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640265419 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.640265419 |
Directory | /workspace/8.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.4001365736 |
Short name | T86 |
Test name | |
Test status | |
Simulation time | 276003309 ps |
CPU time | 4.02 seconds |
Started | Aug 09 05:12:06 PM PDT 24 |
Finished | Aug 09 05:12:10 PM PDT 24 |
Peak memory | 205532 kb |
Host | smart-faebc2fb-8759-4634-9b3a-d3939298fc5a |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001365736 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_ csr_outstanding.4001365736 |
Directory | /workspace/8.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.1750142334 |
Short name | T321 |
Test name | |
Test status | |
Simulation time | 36016085610 ps |
CPU time | 219.53 seconds |
Started | Aug 09 05:12:08 PM PDT 24 |
Finished | Aug 09 05:15:48 PM PDT 24 |
Peak memory | 220992 kb |
Host | smart-edd93ea9-6244-4cdb-b41a-f3ba46cb9b1a |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750142334 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.1750142334 |
Directory | /workspace/8.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.1826350592 |
Short name | T454 |
Test name | |
Test status | |
Simulation time | 292449562 ps |
CPU time | 2.97 seconds |
Started | Aug 09 05:12:08 PM PDT 24 |
Finished | Aug 09 05:12:11 PM PDT 24 |
Peak memory | 213776 kb |
Host | smart-d28de382-d312-4b33-8346-1a1a3fffe52f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826350592 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.1826350592 |
Directory | /workspace/8.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3224251162 |
Short name | T381 |
Test name | |
Test status | |
Simulation time | 9106145151 ps |
CPU time | 18.84 seconds |
Started | Aug 09 05:12:09 PM PDT 24 |
Finished | Aug 09 05:12:28 PM PDT 24 |
Peak memory | 213860 kb |
Host | smart-ed334a50-f44f-4f08-90cf-468614ab46b3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224251162 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.3224251162 |
Directory | /workspace/8.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.2813532389 |
Short name | T324 |
Test name | |
Test status | |
Simulation time | 370807014 ps |
CPU time | 2.25 seconds |
Started | Aug 09 05:12:17 PM PDT 24 |
Finished | Aug 09 05:12:19 PM PDT 24 |
Peak memory | 215776 kb |
Host | smart-9ca0b75e-46d2-417e-a62f-edcdaf53328a |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813532389 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.2813532389 |
Directory | /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.4103315774 |
Short name | T98 |
Test name | |
Test status | |
Simulation time | 153975714 ps |
CPU time | 2.2 seconds |
Started | Aug 09 05:12:13 PM PDT 24 |
Finished | Aug 09 05:12:15 PM PDT 24 |
Peak memory | 213732 kb |
Host | smart-d94a3db8-d885-4151-ba14-5b4ea519b9e6 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103315774 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.4103315774 |
Directory | /workspace/9.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.797945535 |
Short name | T364 |
Test name | |
Test status | |
Simulation time | 11191085079 ps |
CPU time | 34.07 seconds |
Started | Aug 09 05:12:14 PM PDT 24 |
Finished | Aug 09 05:12:48 PM PDT 24 |
Peak memory | 205596 kb |
Host | smart-31a3c0a2-45ae-48a2-84a6-61268baa2f11 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797945535 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.r v_dm_jtag_dmi_csr_bit_bash.797945535 |
Directory | /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.3981266647 |
Short name | T328 |
Test name | |
Test status | |
Simulation time | 6296089374 ps |
CPU time | 4.01 seconds |
Started | Aug 09 05:12:15 PM PDT 24 |
Finished | Aug 09 05:12:19 PM PDT 24 |
Peak memory | 205636 kb |
Host | smart-3d90f5ec-bb94-49d4-93c6-136bf28a2f26 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981266647 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.3 981266647 |
Directory | /workspace/9.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.1592799684 |
Short name | T436 |
Test name | |
Test status | |
Simulation time | 721963550 ps |
CPU time | 2.46 seconds |
Started | Aug 09 05:12:08 PM PDT 24 |
Finished | Aug 09 05:12:11 PM PDT 24 |
Peak memory | 205236 kb |
Host | smart-51683837-c073-418c-b21b-b71f8e1020f9 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592799684 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.1 592799684 |
Directory | /workspace/9.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.760306827 |
Short name | T459 |
Test name | |
Test status | |
Simulation time | 296551175 ps |
CPU time | 6.59 seconds |
Started | Aug 09 05:12:13 PM PDT 24 |
Finished | Aug 09 05:12:19 PM PDT 24 |
Peak memory | 205528 kb |
Host | smart-cd2a5aca-8a87-4850-a083-dd647864ac5f |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760306827 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_c sr_outstanding.760306827 |
Directory | /workspace/9.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.2278292031 |
Short name | T358 |
Test name | |
Test status | |
Simulation time | 13243044755 ps |
CPU time | 69.52 seconds |
Started | Aug 09 05:12:15 PM PDT 24 |
Finished | Aug 09 05:13:24 PM PDT 24 |
Peak memory | 213980 kb |
Host | smart-4e992922-7ce3-42ac-9921-2c570f352674 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278292031 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.2278292031 |
Directory | /workspace/9.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.3278635020 |
Short name | T113 |
Test name | |
Test status | |
Simulation time | 1240403425 ps |
CPU time | 5.67 seconds |
Started | Aug 09 05:12:16 PM PDT 24 |
Finished | Aug 09 05:12:22 PM PDT 24 |
Peak memory | 213892 kb |
Host | smart-58a13ae2-4d7e-466e-a88b-7120bcb93a1a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278635020 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.3278635020 |
Directory | /workspace/9.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.3907968191 |
Short name | T450 |
Test name | |
Test status | |
Simulation time | 1849026334 ps |
CPU time | 10.41 seconds |
Started | Aug 09 05:12:14 PM PDT 24 |
Finished | Aug 09 05:12:25 PM PDT 24 |
Peak memory | 213792 kb |
Host | smart-876f4d85-c88e-4f4f-a5bb-4b03212e3740 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907968191 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.3907968191 |
Directory | /workspace/9.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/0.rv_dm_alert_test.1719069732 |
Short name | T263 |
Test name | |
Test status | |
Simulation time | 44315390 ps |
CPU time | 0.8 seconds |
Started | Aug 09 07:13:27 PM PDT 24 |
Finished | Aug 09 07:13:28 PM PDT 24 |
Peak memory | 205292 kb |
Host | smart-80b759cf-e494-4d63-a400-0c4d799ab36b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719069732 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.1719069732 |
Directory | /workspace/0.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.2565521693 |
Short name | T190 |
Test name | |
Test status | |
Simulation time | 13339535202 ps |
CPU time | 34.68 seconds |
Started | Aug 09 07:13:18 PM PDT 24 |
Finished | Aug 09 07:13:53 PM PDT 24 |
Peak memory | 213944 kb |
Host | smart-f3d6857f-c626-433e-901b-bd0605a03edd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2565521693 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.2565521693 |
Directory | /workspace/0.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.1914614754 |
Short name | T206 |
Test name | |
Test status | |
Simulation time | 6413452371 ps |
CPU time | 2.62 seconds |
Started | Aug 09 07:13:15 PM PDT 24 |
Finished | Aug 09 07:13:18 PM PDT 24 |
Peak memory | 205708 kb |
Host | smart-a63ad91c-2ed7-4e6b-a294-6234740518a6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1914614754 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.1914614754 |
Directory | /workspace/0.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_busy.2410478801 |
Short name | T272 |
Test name | |
Test status | |
Simulation time | 301742782 ps |
CPU time | 1.06 seconds |
Started | Aug 09 07:13:18 PM PDT 24 |
Finished | Aug 09 07:13:19 PM PDT 24 |
Peak memory | 205260 kb |
Host | smart-5d72a35f-3f62-41e4-a7ce-81ebaa5245a2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2410478801 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.2410478801 |
Directory | /workspace/0.rv_dm_cmderr_busy/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_exception.1036445795 |
Short name | T16 |
Test name | |
Test status | |
Simulation time | 477018796 ps |
CPU time | 1.57 seconds |
Started | Aug 09 07:13:18 PM PDT 24 |
Finished | Aug 09 07:13:19 PM PDT 24 |
Peak memory | 205292 kb |
Host | smart-c4926574-968a-4117-b7a5-b60031d4a609 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1036445795 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.1036445795 |
Directory | /workspace/0.rv_dm_cmderr_exception/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_not_supported.1844327375 |
Short name | T26 |
Test name | |
Test status | |
Simulation time | 132745702 ps |
CPU time | 1.01 seconds |
Started | Aug 09 07:13:20 PM PDT 24 |
Finished | Aug 09 07:13:22 PM PDT 24 |
Peak memory | 205272 kb |
Host | smart-70c10ef6-d397-4a6e-a685-1499c237cdde |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1844327375 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.1844327375 |
Directory | /workspace/0.rv_dm_cmderr_not_supported/latest |
Test location | /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.1036764441 |
Short name | T302 |
Test name | |
Test status | |
Simulation time | 108559003 ps |
CPU time | 0.83 seconds |
Started | Aug 09 07:13:18 PM PDT 24 |
Finished | Aug 09 07:13:19 PM PDT 24 |
Peak memory | 205284 kb |
Host | smart-82e5aaa4-9874-4089-956c-895c4563b18c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1036764441 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.1036764441 |
Directory | /workspace/0.rv_dm_dataaddr_rw_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_debug_disabled.528765855 |
Short name | T121 |
Test name | |
Test status | |
Simulation time | 155021995 ps |
CPU time | 1.01 seconds |
Started | Aug 09 07:13:16 PM PDT 24 |
Finished | Aug 09 07:13:17 PM PDT 24 |
Peak memory | 215572 kb |
Host | smart-edfaebdc-0c16-4b2c-96c3-160c7a9a5d1c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=528765855 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.528765855 |
Directory | /workspace/0.rv_dm_debug_disabled/latest |
Test location | /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.28046077 |
Short name | T235 |
Test name | |
Test status | |
Simulation time | 11602502756 ps |
CPU time | 19.93 seconds |
Started | Aug 09 07:13:20 PM PDT 24 |
Finished | Aug 09 07:13:40 PM PDT 24 |
Peak memory | 213868 kb |
Host | smart-769729be-a6c6-480f-820c-c074def8dd1e |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=28046077 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_tl_ access.28046077 |
Directory | /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_halt_resume_whereto.1872531897 |
Short name | T24 |
Test name | |
Test status | |
Simulation time | 482082438 ps |
CPU time | 1.8 seconds |
Started | Aug 09 07:13:13 PM PDT 24 |
Finished | Aug 09 07:13:15 PM PDT 24 |
Peak memory | 205296 kb |
Host | smart-abdea41e-0130-43e3-a412-334e27425f77 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1872531897 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.1872531897 |
Directory | /workspace/0.rv_dm_halt_resume_whereto/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.4021925389 |
Short name | T292 |
Test name | |
Test status | |
Simulation time | 223803994 ps |
CPU time | 1.15 seconds |
Started | Aug 09 07:13:17 PM PDT 24 |
Finished | Aug 09 07:13:18 PM PDT 24 |
Peak memory | 205300 kb |
Host | smart-d79f4b50-b773-4d54-9552-ac03df9552aa |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4021925389 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.4021925389 |
Directory | /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.2802006823 |
Short name | T268 |
Test name | |
Test status | |
Simulation time | 1503349373 ps |
CPU time | 3.82 seconds |
Started | Aug 09 07:13:16 PM PDT 24 |
Finished | Aug 09 07:13:20 PM PDT 24 |
Peak memory | 205164 kb |
Host | smart-5385061b-873a-40a7-a00b-e311c50c0687 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2802006823 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.2802006823 |
Directory | /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.2417415860 |
Short name | T229 |
Test name | |
Test status | |
Simulation time | 227605803 ps |
CPU time | 0.97 seconds |
Started | Aug 09 07:13:13 PM PDT 24 |
Finished | Aug 09 07:13:14 PM PDT 24 |
Peak memory | 205228 kb |
Host | smart-09895a5e-e077-4c5e-b444-ddb19ab0ad62 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2417415860 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.2417415860 |
Directory | /workspace/0.rv_dm_jtag_dtm_hard_reset/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.3770115745 |
Short name | T237 |
Test name | |
Test status | |
Simulation time | 194751790 ps |
CPU time | 0.73 seconds |
Started | Aug 09 07:13:15 PM PDT 24 |
Finished | Aug 09 07:13:16 PM PDT 24 |
Peak memory | 205292 kb |
Host | smart-63be69ef-3bd3-420e-947d-76362ef326cd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3770115745 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.3770115745 |
Directory | /workspace/0.rv_dm_jtag_dtm_idle_hint/latest |
Test location | /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.2356720118 |
Short name | T166 |
Test name | |
Test status | |
Simulation time | 574951867 ps |
CPU time | 2.09 seconds |
Started | Aug 09 07:13:19 PM PDT 24 |
Finished | Aug 09 07:13:21 PM PDT 24 |
Peak memory | 205296 kb |
Host | smart-5efb833d-cc12-40df-8b93-21f772d042bd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2356720118 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.2356720118 |
Directory | /workspace/0.rv_dm_mem_tl_access_halted/latest |
Test location | /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.1441020224 |
Short name | T124 |
Test name | |
Test status | |
Simulation time | 490917861 ps |
CPU time | 1.36 seconds |
Started | Aug 09 07:13:19 PM PDT 24 |
Finished | Aug 09 07:13:20 PM PDT 24 |
Peak memory | 205284 kb |
Host | smart-4a704f71-8db5-41b4-9bab-92d3280fd9c6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1441020224 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.1441020224 |
Directory | /workspace/0.rv_dm_mem_tl_access_resuming/latest |
Test location | /workspace/coverage/default/0.rv_dm_ndmreset_req.1658608176 |
Short name | T30 |
Test name | |
Test status | |
Simulation time | 212474075 ps |
CPU time | 0.89 seconds |
Started | Aug 09 07:13:14 PM PDT 24 |
Finished | Aug 09 07:13:15 PM PDT 24 |
Peak memory | 213500 kb |
Host | smart-708e4fa6-3a92-456e-bffa-a06367233a35 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1658608176 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.1658608176 |
Directory | /workspace/0.rv_dm_ndmreset_req/latest |
Test location | /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.250223070 |
Short name | T4 |
Test name | |
Test status | |
Simulation time | 504842179 ps |
CPU time | 1.01 seconds |
Started | Aug 09 07:13:16 PM PDT 24 |
Finished | Aug 09 07:13:17 PM PDT 24 |
Peak memory | 205256 kb |
Host | smart-3544f66a-f042-474a-b4d7-d280daf384ca |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=250223070 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.250223070 |
Directory | /workspace/0.rv_dm_progbuf_read_write_execute/latest |
Test location | /workspace/coverage/default/0.rv_dm_sba_debug_disabled.3673488808 |
Short name | T120 |
Test name | |
Test status | |
Simulation time | 2527094645 ps |
CPU time | 6.99 seconds |
Started | Aug 09 07:13:14 PM PDT 24 |
Finished | Aug 09 07:13:21 PM PDT 24 |
Peak memory | 205668 kb |
Host | smart-74290fe7-86f8-4336-b177-4d9303d9cb9d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3673488808 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.3673488808 |
Directory | /workspace/0.rv_dm_sba_debug_disabled/latest |
Test location | /workspace/coverage/default/0.rv_dm_sba_tl_access.2636719179 |
Short name | T218 |
Test name | |
Test status | |
Simulation time | 1687534102 ps |
CPU time | 3.4 seconds |
Started | Aug 09 07:13:19 PM PDT 24 |
Finished | Aug 09 07:13:22 PM PDT 24 |
Peak memory | 205676 kb |
Host | smart-c9c9a6b0-a372-4024-8013-0cee832065e5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2636719179 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.2636719179 |
Directory | /workspace/0.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_smoke.489897594 |
Short name | T305 |
Test name | |
Test status | |
Simulation time | 427522722 ps |
CPU time | 1.89 seconds |
Started | Aug 09 07:13:17 PM PDT 24 |
Finished | Aug 09 07:13:19 PM PDT 24 |
Peak memory | 205472 kb |
Host | smart-2a46d28a-63c9-4c2b-863f-341aa8dec5a1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=489897594 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.489897594 |
Directory | /workspace/0.rv_dm_smoke/latest |
Test location | /workspace/coverage/default/0.rv_dm_stress_all.2147135902 |
Short name | T250 |
Test name | |
Test status | |
Simulation time | 6827017773 ps |
CPU time | 10.63 seconds |
Started | Aug 09 07:13:23 PM PDT 24 |
Finished | Aug 09 07:13:34 PM PDT 24 |
Peak memory | 213768 kb |
Host | smart-8700e88a-18ad-496c-a06e-e30ff00f7dac |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147135902 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.2147135902 |
Directory | /workspace/0.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/0.rv_dm_stress_all_with_rand_reset.2512583794 |
Short name | T20 |
Test name | |
Test status | |
Simulation time | 77709146217 ps |
CPU time | 634.95 seconds |
Started | Aug 09 07:13:23 PM PDT 24 |
Finished | Aug 09 07:23:58 PM PDT 24 |
Peak memory | 238572 kb |
Host | smart-f82ecac1-e89e-4810-9d01-5569104b57e1 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512583794 -assert nopost proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all_with_rand_reset.2512583794 |
Directory | /workspace/0.rv_dm_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/0.rv_dm_tap_fsm.1728266153 |
Short name | T56 |
Test name | |
Test status | |
Simulation time | 8403855886 ps |
CPU time | 19.41 seconds |
Started | Aug 09 07:13:19 PM PDT 24 |
Finished | Aug 09 07:13:38 PM PDT 24 |
Peak memory | 205584 kb |
Host | smart-f7c826d2-b5a1-4555-b7ac-e42c5b8bac8d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1728266153 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.1728266153 |
Directory | /workspace/0.rv_dm_tap_fsm/latest |
Test location | /workspace/coverage/default/1.rv_dm_abstractcmd_status.957212920 |
Short name | T5 |
Test name | |
Test status | |
Simulation time | 140352079 ps |
CPU time | 1.09 seconds |
Started | Aug 09 07:13:22 PM PDT 24 |
Finished | Aug 09 07:13:23 PM PDT 24 |
Peak memory | 205252 kb |
Host | smart-146149ab-9c2b-4cfe-8eaa-0f4e05863f88 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=957212920 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.957212920 |
Directory | /workspace/1.rv_dm_abstractcmd_status/latest |
Test location | /workspace/coverage/default/1.rv_dm_alert_test.2044929476 |
Short name | T182 |
Test name | |
Test status | |
Simulation time | 171786156 ps |
CPU time | 0.75 seconds |
Started | Aug 09 07:13:29 PM PDT 24 |
Finished | Aug 09 07:13:30 PM PDT 24 |
Peak memory | 205268 kb |
Host | smart-4e97e2e7-1857-429e-a7b5-9866aeac52ee |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044929476 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.2044929476 |
Directory | /workspace/1.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.3171622228 |
Short name | T197 |
Test name | |
Test status | |
Simulation time | 2545841943 ps |
CPU time | 4.29 seconds |
Started | Aug 09 07:13:28 PM PDT 24 |
Finished | Aug 09 07:13:33 PM PDT 24 |
Peak memory | 213912 kb |
Host | smart-e3f8d77b-a221-441d-a108-52b4b16eab0c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3171622228 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.3171622228 |
Directory | /workspace/1.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_busy.2123862027 |
Short name | T273 |
Test name | |
Test status | |
Simulation time | 519221421 ps |
CPU time | 2.16 seconds |
Started | Aug 09 07:13:29 PM PDT 24 |
Finished | Aug 09 07:13:31 PM PDT 24 |
Peak memory | 205292 kb |
Host | smart-27edbaba-6a9c-43d1-afb1-10a552f91ed5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2123862027 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.2123862027 |
Directory | /workspace/1.rv_dm_cmderr_busy/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.2963810774 |
Short name | T35 |
Test name | |
Test status | |
Simulation time | 366265806 ps |
CPU time | 1.73 seconds |
Started | Aug 09 07:13:29 PM PDT 24 |
Finished | Aug 09 07:13:32 PM PDT 24 |
Peak memory | 205264 kb |
Host | smart-a042dc04-885e-4ebe-9878-37664eccc99b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2963810774 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.2963810774 |
Directory | /workspace/1.rv_dm_cmderr_halt_resume/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_not_supported.1388859805 |
Short name | T243 |
Test name | |
Test status | |
Simulation time | 326356585 ps |
CPU time | 0.94 seconds |
Started | Aug 09 07:13:36 PM PDT 24 |
Finished | Aug 09 07:13:37 PM PDT 24 |
Peak memory | 205236 kb |
Host | smart-4302c4e3-15ec-438c-aa45-4b1117931da3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1388859805 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.1388859805 |
Directory | /workspace/1.rv_dm_cmderr_not_supported/latest |
Test location | /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.1605938884 |
Short name | T251 |
Test name | |
Test status | |
Simulation time | 115876408 ps |
CPU time | 0.87 seconds |
Started | Aug 09 07:13:29 PM PDT 24 |
Finished | Aug 09 07:13:30 PM PDT 24 |
Peak memory | 205244 kb |
Host | smart-18a50295-b4d6-430e-b29e-e03641d3406e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1605938884 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.1605938884 |
Directory | /workspace/1.rv_dm_dataaddr_rw_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.2346650013 |
Short name | T89 |
Test name | |
Test status | |
Simulation time | 1544559145 ps |
CPU time | 1.85 seconds |
Started | Aug 09 07:13:21 PM PDT 24 |
Finished | Aug 09 07:13:23 PM PDT 24 |
Peak memory | 205652 kb |
Host | smart-33b4c612-5d79-4a57-b644-a540ccc66b29 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2346650013 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t l_access.2346650013 |
Directory | /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_dmi_failed_op.2573874617 |
Short name | T51 |
Test name | |
Test status | |
Simulation time | 178286523 ps |
CPU time | 0.96 seconds |
Started | Aug 09 07:13:22 PM PDT 24 |
Finished | Aug 09 07:13:23 PM PDT 24 |
Peak memory | 205304 kb |
Host | smart-262609a6-4735-4886-92f5-a8ec9ef41d18 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2573874617 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dmi_failed_op.2573874617 |
Directory | /workspace/1.rv_dm_dmi_failed_op/latest |
Test location | /workspace/coverage/default/1.rv_dm_halt_resume_whereto.2632722317 |
Short name | T210 |
Test name | |
Test status | |
Simulation time | 396858193 ps |
CPU time | 0.98 seconds |
Started | Aug 09 07:13:36 PM PDT 24 |
Finished | Aug 09 07:13:37 PM PDT 24 |
Peak memory | 205216 kb |
Host | smart-aed9705c-dacb-4e40-882c-c6e12fd830c0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2632722317 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.2632722317 |
Directory | /workspace/1.rv_dm_halt_resume_whereto/latest |
Test location | /workspace/coverage/default/1.rv_dm_hart_unavail.2226174985 |
Short name | T227 |
Test name | |
Test status | |
Simulation time | 866160479 ps |
CPU time | 1.86 seconds |
Started | Aug 09 07:13:24 PM PDT 24 |
Finished | Aug 09 07:13:26 PM PDT 24 |
Peak memory | 205292 kb |
Host | smart-2430f539-5422-4ab5-9dc8-62542522b9f0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2226174985 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.2226174985 |
Directory | /workspace/1.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.1024304228 |
Short name | T276 |
Test name | |
Test status | |
Simulation time | 333273886 ps |
CPU time | 1.39 seconds |
Started | Aug 09 07:13:25 PM PDT 24 |
Finished | Aug 09 07:13:27 PM PDT 24 |
Peak memory | 205256 kb |
Host | smart-4d73c3fb-4afb-4431-abdc-c2bc9df9870e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1024304228 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.1024304228 |
Directory | /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.2506727445 |
Short name | T192 |
Test name | |
Test status | |
Simulation time | 2430958103 ps |
CPU time | 2.2 seconds |
Started | Aug 09 07:13:26 PM PDT 24 |
Finished | Aug 09 07:13:28 PM PDT 24 |
Peak memory | 205252 kb |
Host | smart-ee2ad91f-df72-4e98-8a8d-594e40769e31 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2506727445 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.2506727445 |
Directory | /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.2629723075 |
Short name | T264 |
Test name | |
Test status | |
Simulation time | 537606862 ps |
CPU time | 1.28 seconds |
Started | Aug 09 07:13:29 PM PDT 24 |
Finished | Aug 09 07:13:31 PM PDT 24 |
Peak memory | 205236 kb |
Host | smart-b35bab21-c235-476e-adb8-d045d9b13455 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2629723075 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.2629723075 |
Directory | /workspace/1.rv_dm_jtag_dtm_hard_reset/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.3048368539 |
Short name | T70 |
Test name | |
Test status | |
Simulation time | 600857313 ps |
CPU time | 0.93 seconds |
Started | Aug 09 07:13:22 PM PDT 24 |
Finished | Aug 09 07:13:23 PM PDT 24 |
Peak memory | 205244 kb |
Host | smart-23d8c9af-c28d-42d7-82fa-12d517a78a81 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3048368539 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.3048368539 |
Directory | /workspace/1.rv_dm_jtag_dtm_idle_hint/latest |
Test location | /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.2345957290 |
Short name | T2 |
Test name | |
Test status | |
Simulation time | 109307034 ps |
CPU time | 0.84 seconds |
Started | Aug 09 07:13:37 PM PDT 24 |
Finished | Aug 09 07:13:37 PM PDT 24 |
Peak memory | 205276 kb |
Host | smart-cb4a76d1-c81f-406c-ac15-baa15a7ed110 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2345957290 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.2345957290 |
Directory | /workspace/1.rv_dm_mem_tl_access_halted/latest |
Test location | /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.2089383171 |
Short name | T299 |
Test name | |
Test status | |
Simulation time | 615433593 ps |
CPU time | 1.07 seconds |
Started | Aug 09 07:13:23 PM PDT 24 |
Finished | Aug 09 07:13:24 PM PDT 24 |
Peak memory | 205272 kb |
Host | smart-28a122a9-ad3c-4cb4-81df-739d1f371c78 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2089383171 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.2089383171 |
Directory | /workspace/1.rv_dm_mem_tl_access_resuming/latest |
Test location | /workspace/coverage/default/1.rv_dm_ndmreset_req.1587102779 |
Short name | T179 |
Test name | |
Test status | |
Simulation time | 781195124 ps |
CPU time | 1.35 seconds |
Started | Aug 09 07:13:22 PM PDT 24 |
Finished | Aug 09 07:13:23 PM PDT 24 |
Peak memory | 213508 kb |
Host | smart-bc49b33c-4707-488f-bb56-c58b7b067a69 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1587102779 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.1587102779 |
Directory | /workspace/1.rv_dm_ndmreset_req/latest |
Test location | /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.2370231938 |
Short name | T265 |
Test name | |
Test status | |
Simulation time | 1005473200 ps |
CPU time | 2.06 seconds |
Started | Aug 09 07:13:22 PM PDT 24 |
Finished | Aug 09 07:13:25 PM PDT 24 |
Peak memory | 205304 kb |
Host | smart-460ed23e-3d8d-4a57-8184-c0212acbc12e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2370231938 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.2370231938 |
Directory | /workspace/1.rv_dm_progbuf_read_write_execute/latest |
Test location | /workspace/coverage/default/1.rv_dm_rom_read_access.2052384431 |
Short name | T39 |
Test name | |
Test status | |
Simulation time | 148506692 ps |
CPU time | 1.15 seconds |
Started | Aug 09 07:13:25 PM PDT 24 |
Finished | Aug 09 07:13:26 PM PDT 24 |
Peak memory | 213520 kb |
Host | smart-4b11aa51-e227-41f2-acb5-b006fecd9e3f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2052384431 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.2052384431 |
Directory | /workspace/1.rv_dm_rom_read_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_sba_tl_access.1974986370 |
Short name | T223 |
Test name | |
Test status | |
Simulation time | 2346041101 ps |
CPU time | 7.78 seconds |
Started | Aug 09 07:13:28 PM PDT 24 |
Finished | Aug 09 07:13:36 PM PDT 24 |
Peak memory | 213928 kb |
Host | smart-df43b7a1-d359-4f77-bba9-cedb6ea98f8f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1974986370 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.1974986370 |
Directory | /workspace/1.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_sec_cm.1376588849 |
Short name | T65 |
Test name | |
Test status | |
Simulation time | 460027438 ps |
CPU time | 2.21 seconds |
Started | Aug 09 07:13:26 PM PDT 24 |
Finished | Aug 09 07:13:28 PM PDT 24 |
Peak memory | 229588 kb |
Host | smart-0676b03a-48da-480a-8e34-5f89cc21292f |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376588849 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.1376588849 |
Directory | /workspace/1.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/1.rv_dm_smoke.687747740 |
Short name | T67 |
Test name | |
Test status | |
Simulation time | 1998148958 ps |
CPU time | 3.86 seconds |
Started | Aug 09 07:13:26 PM PDT 24 |
Finished | Aug 09 07:13:30 PM PDT 24 |
Peak memory | 205476 kb |
Host | smart-399630ae-6579-4735-a128-62b25459906a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=687747740 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.687747740 |
Directory | /workspace/1.rv_dm_smoke/latest |
Test location | /workspace/coverage/default/1.rv_dm_stress_all.1927571045 |
Short name | T41 |
Test name | |
Test status | |
Simulation time | 7669950776 ps |
CPU time | 18.71 seconds |
Started | Aug 09 07:13:24 PM PDT 24 |
Finished | Aug 09 07:13:44 PM PDT 24 |
Peak memory | 215156 kb |
Host | smart-71e98124-a45e-4361-9d56-f516c353bbbc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927571045 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.1927571045 |
Directory | /workspace/1.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/10.rv_dm_alert_test.1227999377 |
Short name | T68 |
Test name | |
Test status | |
Simulation time | 64032818 ps |
CPU time | 0.8 seconds |
Started | Aug 09 07:13:46 PM PDT 24 |
Finished | Aug 09 07:13:47 PM PDT 24 |
Peak memory | 205292 kb |
Host | smart-efeedeec-aadd-4bc6-bf9d-53695ad8419c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227999377 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.1227999377 |
Directory | /workspace/10.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.646372470 |
Short name | T286 |
Test name | |
Test status | |
Simulation time | 893720902 ps |
CPU time | 1.64 seconds |
Started | Aug 09 07:13:44 PM PDT 24 |
Finished | Aug 09 07:13:46 PM PDT 24 |
Peak memory | 213832 kb |
Host | smart-c955ed5a-a635-48f3-a952-42e004424e86 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=646372470 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.646372470 |
Directory | /workspace/10.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.2077029324 |
Short name | T270 |
Test name | |
Test status | |
Simulation time | 10287588968 ps |
CPU time | 6.33 seconds |
Started | Aug 09 07:13:41 PM PDT 24 |
Finished | Aug 09 07:13:48 PM PDT 24 |
Peak memory | 222108 kb |
Host | smart-0e81db46-e365-42ce-be02-4fb3df883fa2 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2077029324 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_ tl_access.2077029324 |
Directory | /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/10.rv_dm_sba_tl_access.2767825928 |
Short name | T239 |
Test name | |
Test status | |
Simulation time | 1702505359 ps |
CPU time | 5.69 seconds |
Started | Aug 09 07:13:40 PM PDT 24 |
Finished | Aug 09 07:13:46 PM PDT 24 |
Peak memory | 205580 kb |
Host | smart-dada6e0f-1709-4356-bbec-e4e6a6ab2afc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2767825928 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.2767825928 |
Directory | /workspace/10.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/10.rv_dm_stress_all.726820530 |
Short name | T23 |
Test name | |
Test status | |
Simulation time | 3272733738 ps |
CPU time | 8.68 seconds |
Started | Aug 09 07:13:42 PM PDT 24 |
Finished | Aug 09 07:13:51 PM PDT 24 |
Peak memory | 205872 kb |
Host | smart-1d20051f-0b36-4fb2-be21-7566c525a31c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726820530 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.726820530 |
Directory | /workspace/10.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/11.rv_dm_alert_test.1940661252 |
Short name | T31 |
Test name | |
Test status | |
Simulation time | 133509156 ps |
CPU time | 0.79 seconds |
Started | Aug 09 07:13:44 PM PDT 24 |
Finished | Aug 09 07:13:45 PM PDT 24 |
Peak memory | 205512 kb |
Host | smart-8f624ee1-03fd-40f3-ae6f-3fcc4f07dce9 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940661252 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.1940661252 |
Directory | /workspace/11.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.4273746864 |
Short name | T173 |
Test name | |
Test status | |
Simulation time | 4915947158 ps |
CPU time | 4.15 seconds |
Started | Aug 09 07:13:39 PM PDT 24 |
Finished | Aug 09 07:13:43 PM PDT 24 |
Peak memory | 222056 kb |
Host | smart-812455fe-d5f8-4340-b4bb-9c69c8670ea2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4273746864 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.4273746864 |
Directory | /workspace/11.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.1545373403 |
Short name | T255 |
Test name | |
Test status | |
Simulation time | 1976200759 ps |
CPU time | 6.39 seconds |
Started | Aug 09 07:13:42 PM PDT 24 |
Finished | Aug 09 07:13:49 PM PDT 24 |
Peak memory | 205664 kb |
Host | smart-b321a9df-b298-4da2-95c1-be25297267fc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1545373403 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.1545373403 |
Directory | /workspace/11.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.381440897 |
Short name | T193 |
Test name | |
Test status | |
Simulation time | 5493194317 ps |
CPU time | 7.36 seconds |
Started | Aug 09 07:13:46 PM PDT 24 |
Finished | Aug 09 07:13:54 PM PDT 24 |
Peak memory | 214004 kb |
Host | smart-c72beb7e-8142-4b8e-bc23-de9744623d3c |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=381440897 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_t l_access.381440897 |
Directory | /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/11.rv_dm_sba_tl_access.2210760988 |
Short name | T225 |
Test name | |
Test status | |
Simulation time | 726142078 ps |
CPU time | 1.5 seconds |
Started | Aug 09 07:13:43 PM PDT 24 |
Finished | Aug 09 07:13:44 PM PDT 24 |
Peak memory | 205612 kb |
Host | smart-205a7cd2-55a1-4605-8b99-16a34b1698a9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2210760988 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.2210760988 |
Directory | /workspace/11.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/11.rv_dm_stress_all.3233944206 |
Short name | T287 |
Test name | |
Test status | |
Simulation time | 4894256601 ps |
CPU time | 5.06 seconds |
Started | Aug 09 07:13:42 PM PDT 24 |
Finished | Aug 09 07:13:48 PM PDT 24 |
Peak memory | 214036 kb |
Host | smart-0939ec0b-afcc-475e-9962-fb66a785babe |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233944206 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.3233944206 |
Directory | /workspace/11.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/12.rv_dm_alert_test.1052336972 |
Short name | T254 |
Test name | |
Test status | |
Simulation time | 56121977 ps |
CPU time | 0.68 seconds |
Started | Aug 09 07:13:40 PM PDT 24 |
Finished | Aug 09 07:13:41 PM PDT 24 |
Peak memory | 205224 kb |
Host | smart-f5c4b319-0b0a-46e4-a2de-e5df4ce72d4e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052336972 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.1052336972 |
Directory | /workspace/12.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.877329099 |
Short name | T295 |
Test name | |
Test status | |
Simulation time | 1198479917 ps |
CPU time | 1.26 seconds |
Started | Aug 09 07:13:41 PM PDT 24 |
Finished | Aug 09 07:13:42 PM PDT 24 |
Peak memory | 213856 kb |
Host | smart-e03d4b5f-b041-4609-9771-0dde0d7b6fd5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=877329099 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.877329099 |
Directory | /workspace/12.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.416565314 |
Short name | T266 |
Test name | |
Test status | |
Simulation time | 8945236861 ps |
CPU time | 12.42 seconds |
Started | Aug 09 07:13:40 PM PDT 24 |
Finished | Aug 09 07:13:53 PM PDT 24 |
Peak memory | 214032 kb |
Host | smart-69e88e8b-0f6a-4c01-a580-f1c9240a0c3c |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=416565314 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_t l_access.416565314 |
Directory | /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/12.rv_dm_sba_tl_access.696925932 |
Short name | T205 |
Test name | |
Test status | |
Simulation time | 2145876274 ps |
CPU time | 6.65 seconds |
Started | Aug 09 07:13:42 PM PDT 24 |
Finished | Aug 09 07:13:49 PM PDT 24 |
Peak memory | 205644 kb |
Host | smart-4aa3c4cb-3264-4759-a5be-fe8a892d2661 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=696925932 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.696925932 |
Directory | /workspace/12.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/12.rv_dm_stress_all.53644368 |
Short name | T19 |
Test name | |
Test status | |
Simulation time | 4860082584 ps |
CPU time | 9.74 seconds |
Started | Aug 09 07:13:41 PM PDT 24 |
Finished | Aug 09 07:13:51 PM PDT 24 |
Peak memory | 213776 kb |
Host | smart-6dce66a9-d74e-4e07-90aa-5bd9ed02eb8d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53644368 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.53644368 |
Directory | /workspace/12.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/13.rv_dm_alert_test.1255768770 |
Short name | T247 |
Test name | |
Test status | |
Simulation time | 69120897 ps |
CPU time | 0.76 seconds |
Started | Aug 09 07:13:42 PM PDT 24 |
Finished | Aug 09 07:13:43 PM PDT 24 |
Peak memory | 205252 kb |
Host | smart-a28c05c8-30bb-43c7-a305-51e1feaab67d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255768770 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.1255768770 |
Directory | /workspace/13.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.2163822525 |
Short name | T214 |
Test name | |
Test status | |
Simulation time | 1188408042 ps |
CPU time | 2.02 seconds |
Started | Aug 09 07:13:41 PM PDT 24 |
Finished | Aug 09 07:13:43 PM PDT 24 |
Peak memory | 213908 kb |
Host | smart-beafdd81-bcaf-4344-9fca-bf747fbfddfc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2163822525 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.2163822525 |
Directory | /workspace/13.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.534523555 |
Short name | T230 |
Test name | |
Test status | |
Simulation time | 4446653138 ps |
CPU time | 4.18 seconds |
Started | Aug 09 07:13:40 PM PDT 24 |
Finished | Aug 09 07:13:45 PM PDT 24 |
Peak memory | 205808 kb |
Host | smart-f16a99ae-9ba7-43b7-809d-e3ddce57a8d0 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=534523555 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_t l_access.534523555 |
Directory | /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/13.rv_dm_sba_tl_access.734571501 |
Short name | T236 |
Test name | |
Test status | |
Simulation time | 2174104401 ps |
CPU time | 2.4 seconds |
Started | Aug 09 07:13:43 PM PDT 24 |
Finished | Aug 09 07:13:46 PM PDT 24 |
Peak memory | 205776 kb |
Host | smart-bca3ac5f-6084-4f13-8e0b-6248c5f4b131 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=734571501 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.734571501 |
Directory | /workspace/13.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/13.rv_dm_stress_all.1664495541 |
Short name | T167 |
Test name | |
Test status | |
Simulation time | 4700366865 ps |
CPU time | 12.26 seconds |
Started | Aug 09 07:13:41 PM PDT 24 |
Finished | Aug 09 07:13:54 PM PDT 24 |
Peak memory | 213808 kb |
Host | smart-d481d559-ab08-400f-8915-db50dfc7d03b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664495541 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.1664495541 |
Directory | /workspace/13.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/14.rv_dm_alert_test.2530684819 |
Short name | T187 |
Test name | |
Test status | |
Simulation time | 71019159 ps |
CPU time | 0.7 seconds |
Started | Aug 09 07:13:41 PM PDT 24 |
Finished | Aug 09 07:13:42 PM PDT 24 |
Peak memory | 205300 kb |
Host | smart-63122eb1-a99d-4c3c-b821-07270bf5e43d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530684819 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.2530684819 |
Directory | /workspace/14.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.2843552831 |
Short name | T171 |
Test name | |
Test status | |
Simulation time | 15015764910 ps |
CPU time | 16.52 seconds |
Started | Aug 09 07:13:41 PM PDT 24 |
Finished | Aug 09 07:13:58 PM PDT 24 |
Peak memory | 213944 kb |
Host | smart-0ffae13f-1791-415a-9a3d-ac31eb44cb8a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2843552831 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.2843552831 |
Directory | /workspace/14.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.4013673114 |
Short name | T135 |
Test name | |
Test status | |
Simulation time | 4408579660 ps |
CPU time | 4.35 seconds |
Started | Aug 09 07:13:40 PM PDT 24 |
Finished | Aug 09 07:13:45 PM PDT 24 |
Peak memory | 205716 kb |
Host | smart-2e1e3ab1-3fc0-4a26-b615-bfbb052665dc |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4013673114 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_ tl_access.4013673114 |
Directory | /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/14.rv_dm_sba_tl_access.277355234 |
Short name | T301 |
Test name | |
Test status | |
Simulation time | 5188694295 ps |
CPU time | 5.24 seconds |
Started | Aug 09 07:13:43 PM PDT 24 |
Finished | Aug 09 07:13:48 PM PDT 24 |
Peak memory | 205828 kb |
Host | smart-ef3d0e34-bfa9-4b40-a057-c4656b61754d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=277355234 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.277355234 |
Directory | /workspace/14.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/14.rv_dm_stress_all.1762232653 |
Short name | T18 |
Test name | |
Test status | |
Simulation time | 2393074782 ps |
CPU time | 6.73 seconds |
Started | Aug 09 07:13:42 PM PDT 24 |
Finished | Aug 09 07:13:48 PM PDT 24 |
Peak memory | 213856 kb |
Host | smart-1a68a34c-573e-4462-8bff-7347a08e935b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762232653 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.1762232653 |
Directory | /workspace/14.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/15.rv_dm_alert_test.1584237948 |
Short name | T175 |
Test name | |
Test status | |
Simulation time | 48528547 ps |
CPU time | 0.8 seconds |
Started | Aug 09 07:13:46 PM PDT 24 |
Finished | Aug 09 07:13:47 PM PDT 24 |
Peak memory | 205296 kb |
Host | smart-52a4e09e-84b4-470e-a4b5-06b6852d9b5f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584237948 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.1584237948 |
Directory | /workspace/15.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.657403468 |
Short name | T125 |
Test name | |
Test status | |
Simulation time | 4129620673 ps |
CPU time | 3.62 seconds |
Started | Aug 09 07:13:43 PM PDT 24 |
Finished | Aug 09 07:13:46 PM PDT 24 |
Peak memory | 213964 kb |
Host | smart-19d8a62d-5a4a-4926-bdcd-f6d0fce888e3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=657403468 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.657403468 |
Directory | /workspace/15.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.2566573399 |
Short name | T201 |
Test name | |
Test status | |
Simulation time | 2117214287 ps |
CPU time | 6.37 seconds |
Started | Aug 09 07:13:44 PM PDT 24 |
Finished | Aug 09 07:13:51 PM PDT 24 |
Peak memory | 213924 kb |
Host | smart-9bd0bdfe-2210-45a3-acdd-0c2de5cc5b74 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2566573399 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.2566573399 |
Directory | /workspace/15.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.3176554618 |
Short name | T284 |
Test name | |
Test status | |
Simulation time | 2914006844 ps |
CPU time | 8.62 seconds |
Started | Aug 09 07:13:43 PM PDT 24 |
Finished | Aug 09 07:13:51 PM PDT 24 |
Peak memory | 213904 kb |
Host | smart-7dde2c9f-f66c-4430-8cbd-b26c06dc50c4 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3176554618 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_ tl_access.3176554618 |
Directory | /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/15.rv_dm_sba_tl_access.457241399 |
Short name | T52 |
Test name | |
Test status | |
Simulation time | 635243227 ps |
CPU time | 2.52 seconds |
Started | Aug 09 07:13:45 PM PDT 24 |
Finished | Aug 09 07:13:47 PM PDT 24 |
Peak memory | 205604 kb |
Host | smart-46d6ab8a-4a3a-4ebe-8584-163461757430 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=457241399 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.457241399 |
Directory | /workspace/15.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_alert_test.2814765984 |
Short name | T222 |
Test name | |
Test status | |
Simulation time | 41985439 ps |
CPU time | 0.82 seconds |
Started | Aug 09 07:13:40 PM PDT 24 |
Finished | Aug 09 07:13:41 PM PDT 24 |
Peak memory | 205288 kb |
Host | smart-95ab1042-c3e4-4d76-a3a9-33af7acffa34 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814765984 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.2814765984 |
Directory | /workspace/16.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.2903097601 |
Short name | T140 |
Test name | |
Test status | |
Simulation time | 32300241926 ps |
CPU time | 31.23 seconds |
Started | Aug 09 07:13:45 PM PDT 24 |
Finished | Aug 09 07:14:16 PM PDT 24 |
Peak memory | 214156 kb |
Host | smart-0f372312-66b7-4157-8d8a-f82c27baa15e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2903097601 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.2903097601 |
Directory | /workspace/16.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.2507162115 |
Short name | T279 |
Test name | |
Test status | |
Simulation time | 1839860689 ps |
CPU time | 2.53 seconds |
Started | Aug 09 07:13:45 PM PDT 24 |
Finished | Aug 09 07:13:47 PM PDT 24 |
Peak memory | 214508 kb |
Host | smart-2952d56a-badf-4739-ad9c-b408df693a7d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2507162115 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.2507162115 |
Directory | /workspace/16.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.2797632131 |
Short name | T296 |
Test name | |
Test status | |
Simulation time | 2734862876 ps |
CPU time | 8.73 seconds |
Started | Aug 09 07:13:40 PM PDT 24 |
Finished | Aug 09 07:13:49 PM PDT 24 |
Peak memory | 205740 kb |
Host | smart-95413878-fb02-4050-9caf-cc4449e567dc |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2797632131 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_ tl_access.2797632131 |
Directory | /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_sba_tl_access.1169653828 |
Short name | T72 |
Test name | |
Test status | |
Simulation time | 3616233924 ps |
CPU time | 3.26 seconds |
Started | Aug 09 07:13:42 PM PDT 24 |
Finished | Aug 09 07:13:45 PM PDT 24 |
Peak memory | 205696 kb |
Host | smart-52b3ca72-aa66-4199-9a3a-9c43bea75a7a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1169653828 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.1169653828 |
Directory | /workspace/16.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_stress_all.2244540047 |
Short name | T131 |
Test name | |
Test status | |
Simulation time | 6310485929 ps |
CPU time | 10.5 seconds |
Started | Aug 09 07:13:42 PM PDT 24 |
Finished | Aug 09 07:13:53 PM PDT 24 |
Peak memory | 205624 kb |
Host | smart-f5376320-74e9-45fa-bea8-2bcb44206291 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244540047 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.2244540047 |
Directory | /workspace/16.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/17.rv_dm_alert_test.3816409268 |
Short name | T245 |
Test name | |
Test status | |
Simulation time | 143447061 ps |
CPU time | 1.08 seconds |
Started | Aug 09 07:13:50 PM PDT 24 |
Finished | Aug 09 07:13:51 PM PDT 24 |
Peak memory | 205280 kb |
Host | smart-fdd3d8ae-62ca-4bd2-a934-d2bf8496d59e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816409268 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.3816409268 |
Directory | /workspace/17.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.1515030551 |
Short name | T199 |
Test name | |
Test status | |
Simulation time | 16052836469 ps |
CPU time | 40.83 seconds |
Started | Aug 09 07:13:41 PM PDT 24 |
Finished | Aug 09 07:14:22 PM PDT 24 |
Peak memory | 213972 kb |
Host | smart-9fc62410-4a70-44d3-a826-3bacbe5e9550 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1515030551 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.1515030551 |
Directory | /workspace/17.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.3634160779 |
Short name | T280 |
Test name | |
Test status | |
Simulation time | 5419597790 ps |
CPU time | 12.28 seconds |
Started | Aug 09 07:13:41 PM PDT 24 |
Finished | Aug 09 07:13:53 PM PDT 24 |
Peak memory | 213920 kb |
Host | smart-64072e2a-0750-47c4-a20e-c2dc43723328 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3634160779 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.3634160779 |
Directory | /workspace/17.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.254702756 |
Short name | T202 |
Test name | |
Test status | |
Simulation time | 12356321991 ps |
CPU time | 19.11 seconds |
Started | Aug 09 07:13:42 PM PDT 24 |
Finished | Aug 09 07:14:01 PM PDT 24 |
Peak memory | 213924 kb |
Host | smart-94884164-95d6-4748-ad5b-a1ba644fa61f |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=254702756 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_t l_access.254702756 |
Directory | /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/17.rv_dm_sba_tl_access.3492357862 |
Short name | T139 |
Test name | |
Test status | |
Simulation time | 4870781664 ps |
CPU time | 7.13 seconds |
Started | Aug 09 07:13:42 PM PDT 24 |
Finished | Aug 09 07:13:50 PM PDT 24 |
Peak memory | 205708 kb |
Host | smart-395b4fb7-d7ac-405c-bbeb-7bdbf5638955 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3492357862 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.3492357862 |
Directory | /workspace/17.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/17.rv_dm_stress_all.3305294363 |
Short name | T127 |
Test name | |
Test status | |
Simulation time | 11071182073 ps |
CPU time | 32.33 seconds |
Started | Aug 09 07:13:42 PM PDT 24 |
Finished | Aug 09 07:14:14 PM PDT 24 |
Peak memory | 205580 kb |
Host | smart-0e9388a0-3241-4da2-8738-bcdbed40043f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305294363 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.3305294363 |
Directory | /workspace/17.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/18.rv_dm_alert_test.1488304467 |
Short name | T55 |
Test name | |
Test status | |
Simulation time | 136646038 ps |
CPU time | 0.97 seconds |
Started | Aug 09 07:13:48 PM PDT 24 |
Finished | Aug 09 07:13:49 PM PDT 24 |
Peak memory | 205300 kb |
Host | smart-ce61034a-365d-432d-816e-238040304138 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488304467 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.1488304467 |
Directory | /workspace/18.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.770795484 |
Short name | T176 |
Test name | |
Test status | |
Simulation time | 9833821315 ps |
CPU time | 9.69 seconds |
Started | Aug 09 07:13:52 PM PDT 24 |
Finished | Aug 09 07:14:01 PM PDT 24 |
Peak memory | 214232 kb |
Host | smart-d0cae355-8a1c-476d-8d3d-e685675d9f86 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=770795484 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.770795484 |
Directory | /workspace/18.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.2719433934 |
Short name | T13 |
Test name | |
Test status | |
Simulation time | 4230351960 ps |
CPU time | 6.41 seconds |
Started | Aug 09 07:13:51 PM PDT 24 |
Finished | Aug 09 07:13:57 PM PDT 24 |
Peak memory | 214024 kb |
Host | smart-2607d876-6c83-4ea6-9733-6487e76f375c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2719433934 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.2719433934 |
Directory | /workspace/18.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.340602627 |
Short name | T297 |
Test name | |
Test status | |
Simulation time | 2528966403 ps |
CPU time | 8.22 seconds |
Started | Aug 09 07:13:50 PM PDT 24 |
Finished | Aug 09 07:13:59 PM PDT 24 |
Peak memory | 213988 kb |
Host | smart-d7c60f79-e302-483a-a2f6-14c24ab8c89a |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=340602627 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_t l_access.340602627 |
Directory | /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/18.rv_dm_sba_tl_access.1349351853 |
Short name | T147 |
Test name | |
Test status | |
Simulation time | 1063886193 ps |
CPU time | 1.53 seconds |
Started | Aug 09 07:13:48 PM PDT 24 |
Finished | Aug 09 07:13:50 PM PDT 24 |
Peak memory | 205596 kb |
Host | smart-8c1fec6c-dbe8-4940-8b09-38327a123c39 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1349351853 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.1349351853 |
Directory | /workspace/18.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/18.rv_dm_stress_all.1878468464 |
Short name | T141 |
Test name | |
Test status | |
Simulation time | 12687006567 ps |
CPU time | 5.74 seconds |
Started | Aug 09 07:13:53 PM PDT 24 |
Finished | Aug 09 07:13:59 PM PDT 24 |
Peak memory | 213784 kb |
Host | smart-2b72d914-136d-4bd7-b3ee-f5c28b251518 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878468464 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.1878468464 |
Directory | /workspace/18.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/19.rv_dm_alert_test.1073309463 |
Short name | T211 |
Test name | |
Test status | |
Simulation time | 50878716 ps |
CPU time | 0.71 seconds |
Started | Aug 09 07:13:50 PM PDT 24 |
Finished | Aug 09 07:13:51 PM PDT 24 |
Peak memory | 205296 kb |
Host | smart-c008e9b7-27b6-4bcb-9090-7025dfa71cfd |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073309463 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.1073309463 |
Directory | /workspace/19.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.709050097 |
Short name | T180 |
Test name | |
Test status | |
Simulation time | 45059061094 ps |
CPU time | 34.24 seconds |
Started | Aug 09 07:13:49 PM PDT 24 |
Finished | Aug 09 07:14:24 PM PDT 24 |
Peak memory | 222088 kb |
Host | smart-54b4e57a-0234-4768-8fc9-a44c887f37ed |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=709050097 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.709050097 |
Directory | /workspace/19.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.1790355050 |
Short name | T252 |
Test name | |
Test status | |
Simulation time | 1902169127 ps |
CPU time | 2.4 seconds |
Started | Aug 09 07:13:55 PM PDT 24 |
Finished | Aug 09 07:13:58 PM PDT 24 |
Peak memory | 213796 kb |
Host | smart-47f36caa-0fbd-43b6-963b-553e28e43105 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1790355050 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.1790355050 |
Directory | /workspace/19.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.977195342 |
Short name | T185 |
Test name | |
Test status | |
Simulation time | 1256858755 ps |
CPU time | 4.35 seconds |
Started | Aug 09 07:13:50 PM PDT 24 |
Finished | Aug 09 07:13:54 PM PDT 24 |
Peak memory | 205656 kb |
Host | smart-22ba8f07-9e27-4922-8bed-fcead173a237 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=977195342 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_t l_access.977195342 |
Directory | /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_sba_tl_access.3089618848 |
Short name | T300 |
Test name | |
Test status | |
Simulation time | 13782709779 ps |
CPU time | 37.33 seconds |
Started | Aug 09 07:13:48 PM PDT 24 |
Finished | Aug 09 07:14:26 PM PDT 24 |
Peak memory | 213948 kb |
Host | smart-b7f42406-cfa2-4bb9-b8e3-e8c3f7981565 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3089618848 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.3089618848 |
Directory | /workspace/19.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_stress_all.3397307708 |
Short name | T9 |
Test name | |
Test status | |
Simulation time | 13309902442 ps |
CPU time | 18.43 seconds |
Started | Aug 09 07:13:56 PM PDT 24 |
Finished | Aug 09 07:14:14 PM PDT 24 |
Peak memory | 213736 kb |
Host | smart-67e55185-4599-4336-af46-89b8674b0e58 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397307708 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.3397307708 |
Directory | /workspace/19.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/2.rv_dm_alert_test.91224425 |
Short name | T221 |
Test name | |
Test status | |
Simulation time | 142334251 ps |
CPU time | 0.85 seconds |
Started | Aug 09 07:13:34 PM PDT 24 |
Finished | Aug 09 07:13:35 PM PDT 24 |
Peak memory | 205276 kb |
Host | smart-2f8e75c7-5468-48dd-8d93-d1f5d49776e5 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91224425 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.91224425 |
Directory | /workspace/2.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.1222418505 |
Short name | T189 |
Test name | |
Test status | |
Simulation time | 42273091214 ps |
CPU time | 113.52 seconds |
Started | Aug 09 07:13:25 PM PDT 24 |
Finished | Aug 09 07:15:18 PM PDT 24 |
Peak memory | 213992 kb |
Host | smart-03c0722d-c016-40b2-a7af-6939b8f5bda3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1222418505 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.1222418505 |
Directory | /workspace/2.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.3556907534 |
Short name | T186 |
Test name | |
Test status | |
Simulation time | 3730552366 ps |
CPU time | 3.53 seconds |
Started | Aug 09 07:13:21 PM PDT 24 |
Finished | Aug 09 07:13:25 PM PDT 24 |
Peak memory | 213880 kb |
Host | smart-c09e1683-e2f6-4a52-a578-d9af1a26b59f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3556907534 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.3556907534 |
Directory | /workspace/2.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.458950705 |
Short name | T88 |
Test name | |
Test status | |
Simulation time | 3703905023 ps |
CPU time | 6.4 seconds |
Started | Aug 09 07:13:24 PM PDT 24 |
Finished | Aug 09 07:13:30 PM PDT 24 |
Peak memory | 205740 kb |
Host | smart-a0309be5-fd9a-431a-9eb9-0705820be60f |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=458950705 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_tl _access.458950705 |
Directory | /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_halt_resume_whereto.1563464284 |
Short name | T164 |
Test name | |
Test status | |
Simulation time | 675340231 ps |
CPU time | 0.87 seconds |
Started | Aug 09 07:13:26 PM PDT 24 |
Finished | Aug 09 07:13:27 PM PDT 24 |
Peak memory | 205248 kb |
Host | smart-1be88d76-1769-4f7b-b720-068d641f90da |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1563464284 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_halt_resume_whereto.1563464284 |
Directory | /workspace/2.rv_dm_halt_resume_whereto/latest |
Test location | /workspace/coverage/default/2.rv_dm_hart_unavail.632093576 |
Short name | T256 |
Test name | |
Test status | |
Simulation time | 968168068 ps |
CPU time | 3.26 seconds |
Started | Aug 09 07:13:28 PM PDT 24 |
Finished | Aug 09 07:13:32 PM PDT 24 |
Peak memory | 205264 kb |
Host | smart-3617901b-78de-4f53-8ca4-3bbb53cfa740 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=632093576 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.632093576 |
Directory | /workspace/2.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/2.rv_dm_sba_tl_access.2983068774 |
Short name | T281 |
Test name | |
Test status | |
Simulation time | 2197682140 ps |
CPU time | 2.75 seconds |
Started | Aug 09 07:13:24 PM PDT 24 |
Finished | Aug 09 07:13:28 PM PDT 24 |
Peak memory | 205800 kb |
Host | smart-bd78e83b-d46d-4d6c-b91b-815bf0988b0b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2983068774 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.2983068774 |
Directory | /workspace/2.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_sec_cm.1327860657 |
Short name | T47 |
Test name | |
Test status | |
Simulation time | 594950571 ps |
CPU time | 1.5 seconds |
Started | Aug 09 07:13:29 PM PDT 24 |
Finished | Aug 09 07:13:31 PM PDT 24 |
Peak memory | 229428 kb |
Host | smart-00f26009-b193-4361-89b9-b2a626ef676c |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327860657 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.1327860657 |
Directory | /workspace/2.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/2.rv_dm_stress_all.2629831119 |
Short name | T165 |
Test name | |
Test status | |
Simulation time | 3336105216 ps |
CPU time | 9.81 seconds |
Started | Aug 09 07:13:24 PM PDT 24 |
Finished | Aug 09 07:13:34 PM PDT 24 |
Peak memory | 213812 kb |
Host | smart-490f53f6-ab20-4a8d-9732-5f404bd00af6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629831119 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.2629831119 |
Directory | /workspace/2.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/2.rv_dm_stress_all_with_rand_reset.1310967564 |
Short name | T21 |
Test name | |
Test status | |
Simulation time | 219133472553 ps |
CPU time | 714.73 seconds |
Started | Aug 09 07:13:23 PM PDT 24 |
Finished | Aug 09 07:25:18 PM PDT 24 |
Peak memory | 238396 kb |
Host | smart-630e1266-e348-419b-8d99-1f3b4b3f65ea |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310967564 -assert nopost proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all_with_rand_reset.1310967564 |
Directory | /workspace/2.rv_dm_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/20.rv_dm_alert_test.315668939 |
Short name | T224 |
Test name | |
Test status | |
Simulation time | 65612553 ps |
CPU time | 0.78 seconds |
Started | Aug 09 07:13:54 PM PDT 24 |
Finished | Aug 09 07:13:54 PM PDT 24 |
Peak memory | 205248 kb |
Host | smart-dac24f33-ca19-461a-b86d-fd9b79a17764 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315668939 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.315668939 |
Directory | /workspace/20.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/20.rv_dm_stress_all.2244423710 |
Short name | T145 |
Test name | |
Test status | |
Simulation time | 5963054135 ps |
CPU time | 10.75 seconds |
Started | Aug 09 07:13:49 PM PDT 24 |
Finished | Aug 09 07:14:00 PM PDT 24 |
Peak memory | 213776 kb |
Host | smart-b4d4f4ba-9303-49ee-9464-8edec0143bc9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244423710 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.2244423710 |
Directory | /workspace/20.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/21.rv_dm_alert_test.446692155 |
Short name | T219 |
Test name | |
Test status | |
Simulation time | 83206087 ps |
CPU time | 0.75 seconds |
Started | Aug 09 07:13:53 PM PDT 24 |
Finished | Aug 09 07:13:54 PM PDT 24 |
Peak memory | 205232 kb |
Host | smart-f0830943-3e47-46ca-90c8-8bbeb98b13d3 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446692155 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.446692155 |
Directory | /workspace/21.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/21.rv_dm_stress_all.1831080918 |
Short name | T129 |
Test name | |
Test status | |
Simulation time | 6728226037 ps |
CPU time | 19.5 seconds |
Started | Aug 09 07:13:52 PM PDT 24 |
Finished | Aug 09 07:14:11 PM PDT 24 |
Peak memory | 205640 kb |
Host | smart-b1366cde-b9ce-4735-be75-b7b94e56bb39 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831080918 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.1831080918 |
Directory | /workspace/21.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/22.rv_dm_alert_test.2465456846 |
Short name | T257 |
Test name | |
Test status | |
Simulation time | 34071599 ps |
CPU time | 0.77 seconds |
Started | Aug 09 07:13:52 PM PDT 24 |
Finished | Aug 09 07:13:52 PM PDT 24 |
Peak memory | 205284 kb |
Host | smart-c5aa9075-e769-4f08-a6f9-ec5f3bd55baa |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465456846 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.2465456846 |
Directory | /workspace/22.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/22.rv_dm_stress_all.1858927519 |
Short name | T44 |
Test name | |
Test status | |
Simulation time | 2362934053 ps |
CPU time | 1.66 seconds |
Started | Aug 09 07:13:51 PM PDT 24 |
Finished | Aug 09 07:13:53 PM PDT 24 |
Peak memory | 205840 kb |
Host | smart-cb4e63e8-5fa0-40be-b36e-5c51e66c50f1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858927519 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.1858927519 |
Directory | /workspace/22.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/23.rv_dm_alert_test.2071217625 |
Short name | T261 |
Test name | |
Test status | |
Simulation time | 35974780 ps |
CPU time | 0.74 seconds |
Started | Aug 09 07:13:52 PM PDT 24 |
Finished | Aug 09 07:13:53 PM PDT 24 |
Peak memory | 205292 kb |
Host | smart-161821a2-dbfe-43f8-b637-a724dbec9f0f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071217625 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.2071217625 |
Directory | /workspace/23.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/23.rv_dm_stress_all.2607883768 |
Short name | T143 |
Test name | |
Test status | |
Simulation time | 5027380321 ps |
CPU time | 13.16 seconds |
Started | Aug 09 07:13:50 PM PDT 24 |
Finished | Aug 09 07:14:03 PM PDT 24 |
Peak memory | 205632 kb |
Host | smart-ee788ea7-c15a-4d94-a470-f4d70406a1ca |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607883768 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.2607883768 |
Directory | /workspace/23.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/24.rv_dm_alert_test.32651841 |
Short name | T260 |
Test name | |
Test status | |
Simulation time | 112649832 ps |
CPU time | 0.71 seconds |
Started | Aug 09 07:13:54 PM PDT 24 |
Finished | Aug 09 07:13:55 PM PDT 24 |
Peak memory | 205264 kb |
Host | smart-a24cb10b-3e01-4f95-99e4-8642ac347eb7 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32651841 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.32651841 |
Directory | /workspace/24.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/24.rv_dm_stress_all.1539569169 |
Short name | T217 |
Test name | |
Test status | |
Simulation time | 3870774040 ps |
CPU time | 11.63 seconds |
Started | Aug 09 07:13:52 PM PDT 24 |
Finished | Aug 09 07:14:03 PM PDT 24 |
Peak memory | 205604 kb |
Host | smart-6e2bdb12-ddfe-4be8-936b-efb77d77f20b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539569169 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.1539569169 |
Directory | /workspace/24.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/25.rv_dm_alert_test.745136351 |
Short name | T220 |
Test name | |
Test status | |
Simulation time | 48077073 ps |
CPU time | 0.82 seconds |
Started | Aug 09 07:13:52 PM PDT 24 |
Finished | Aug 09 07:13:53 PM PDT 24 |
Peak memory | 205228 kb |
Host | smart-6109ddbe-5b1c-4cdb-90aa-52c3cac31112 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745136351 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.745136351 |
Directory | /workspace/25.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/26.rv_dm_alert_test.3198205838 |
Short name | T234 |
Test name | |
Test status | |
Simulation time | 56320621 ps |
CPU time | 0.81 seconds |
Started | Aug 09 07:13:56 PM PDT 24 |
Finished | Aug 09 07:13:57 PM PDT 24 |
Peak memory | 205232 kb |
Host | smart-af96f779-8857-4c12-9def-405d4036548a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198205838 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.3198205838 |
Directory | /workspace/26.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/26.rv_dm_stress_all.2704884769 |
Short name | T136 |
Test name | |
Test status | |
Simulation time | 1430470545 ps |
CPU time | 2.66 seconds |
Started | Aug 09 07:13:52 PM PDT 24 |
Finished | Aug 09 07:13:55 PM PDT 24 |
Peak memory | 205468 kb |
Host | smart-0a65d7a7-cff6-4455-9eb4-312f187dd1b7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704884769 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.2704884769 |
Directory | /workspace/26.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/27.rv_dm_alert_test.2257102606 |
Short name | T172 |
Test name | |
Test status | |
Simulation time | 107286276 ps |
CPU time | 0.75 seconds |
Started | Aug 09 07:13:54 PM PDT 24 |
Finished | Aug 09 07:13:55 PM PDT 24 |
Peak memory | 205272 kb |
Host | smart-2ec99749-9110-46a4-828b-e56477cd78fe |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257102606 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.2257102606 |
Directory | /workspace/27.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/27.rv_dm_stress_all.150924134 |
Short name | T14 |
Test name | |
Test status | |
Simulation time | 2982219777 ps |
CPU time | 4.87 seconds |
Started | Aug 09 07:13:56 PM PDT 24 |
Finished | Aug 09 07:14:01 PM PDT 24 |
Peak memory | 213732 kb |
Host | smart-c854d72d-b29c-4f87-a2b1-3afceab136ee |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150924134 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.150924134 |
Directory | /workspace/27.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/28.rv_dm_alert_test.3769013576 |
Short name | T64 |
Test name | |
Test status | |
Simulation time | 113972240 ps |
CPU time | 0.96 seconds |
Started | Aug 09 07:13:54 PM PDT 24 |
Finished | Aug 09 07:13:55 PM PDT 24 |
Peak memory | 205256 kb |
Host | smart-19712cbf-9b7b-4e4d-a5f2-2d9dbaa158ab |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769013576 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.3769013576 |
Directory | /workspace/28.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/28.rv_dm_stress_all.1205923075 |
Short name | T285 |
Test name | |
Test status | |
Simulation time | 4232505334 ps |
CPU time | 12.61 seconds |
Started | Aug 09 07:13:55 PM PDT 24 |
Finished | Aug 09 07:14:08 PM PDT 24 |
Peak memory | 205584 kb |
Host | smart-c289ed30-4f2e-4399-b9ea-04ec44c29fcc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205923075 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.1205923075 |
Directory | /workspace/28.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/29.rv_dm_alert_test.944411319 |
Short name | T183 |
Test name | |
Test status | |
Simulation time | 159086766 ps |
CPU time | 1.2 seconds |
Started | Aug 09 07:13:55 PM PDT 24 |
Finished | Aug 09 07:13:56 PM PDT 24 |
Peak memory | 205292 kb |
Host | smart-cf448d0a-58e5-420e-b2c8-e93cce3993b7 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944411319 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.944411319 |
Directory | /workspace/29.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/3.rv_dm_alert_test.3786719879 |
Short name | T73 |
Test name | |
Test status | |
Simulation time | 68401487 ps |
CPU time | 0.75 seconds |
Started | Aug 09 07:13:41 PM PDT 24 |
Finished | Aug 09 07:13:42 PM PDT 24 |
Peak memory | 205288 kb |
Host | smart-7e70e3fe-9e7e-4bc3-96a3-ec6e1972627e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786719879 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.3786719879 |
Directory | /workspace/3.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.1562810930 |
Short name | T271 |
Test name | |
Test status | |
Simulation time | 3681725340 ps |
CPU time | 5.55 seconds |
Started | Aug 09 07:13:38 PM PDT 24 |
Finished | Aug 09 07:13:43 PM PDT 24 |
Peak memory | 205772 kb |
Host | smart-cb93d7a5-0340-457d-b332-814851e851d0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1562810930 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.1562810930 |
Directory | /workspace/3.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.3830385374 |
Short name | T288 |
Test name | |
Test status | |
Simulation time | 1601717705 ps |
CPU time | 3.88 seconds |
Started | Aug 09 07:13:34 PM PDT 24 |
Finished | Aug 09 07:13:38 PM PDT 24 |
Peak memory | 213880 kb |
Host | smart-9656c19c-aba7-4975-ae7b-3dc51a034003 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3830385374 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.3830385374 |
Directory | /workspace/3.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.1530336318 |
Short name | T196 |
Test name | |
Test status | |
Simulation time | 7994995943 ps |
CPU time | 9.71 seconds |
Started | Aug 09 07:13:29 PM PDT 24 |
Finished | Aug 09 07:13:39 PM PDT 24 |
Peak memory | 213888 kb |
Host | smart-71e3fdf7-04cb-4d7b-9415-d347908c4e35 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1530336318 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t l_access.1530336318 |
Directory | /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_halt_resume_whereto.382158679 |
Short name | T194 |
Test name | |
Test status | |
Simulation time | 216976185 ps |
CPU time | 0.88 seconds |
Started | Aug 09 07:13:29 PM PDT 24 |
Finished | Aug 09 07:13:30 PM PDT 24 |
Peak memory | 205232 kb |
Host | smart-209aba1f-121a-48c1-a984-2539caa49fa8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=382158679 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_halt_resume_whereto.382158679 |
Directory | /workspace/3.rv_dm_halt_resume_whereto/latest |
Test location | /workspace/coverage/default/3.rv_dm_hart_unavail.1533338276 |
Short name | T174 |
Test name | |
Test status | |
Simulation time | 905945376 ps |
CPU time | 3.1 seconds |
Started | Aug 09 07:13:26 PM PDT 24 |
Finished | Aug 09 07:13:29 PM PDT 24 |
Peak memory | 205276 kb |
Host | smart-7b03e286-b86a-4ee7-b665-2ac90ee31cfd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1533338276 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.1533338276 |
Directory | /workspace/3.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/3.rv_dm_sba_tl_access.4078396540 |
Short name | T215 |
Test name | |
Test status | |
Simulation time | 915823588 ps |
CPU time | 1.1 seconds |
Started | Aug 09 07:13:29 PM PDT 24 |
Finished | Aug 09 07:13:30 PM PDT 24 |
Peak memory | 205564 kb |
Host | smart-c98db465-4af9-445b-a801-f816a22e9486 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4078396540 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.4078396540 |
Directory | /workspace/3.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_sec_cm.4173855828 |
Short name | T48 |
Test name | |
Test status | |
Simulation time | 356669581 ps |
CPU time | 1.45 seconds |
Started | Aug 09 07:13:33 PM PDT 24 |
Finished | Aug 09 07:13:34 PM PDT 24 |
Peak memory | 229868 kb |
Host | smart-f1bc9526-92e6-4aa9-92b3-3f905a7359a3 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173855828 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.4173855828 |
Directory | /workspace/3.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/3.rv_dm_stress_all.3165808754 |
Short name | T15 |
Test name | |
Test status | |
Simulation time | 1020066841 ps |
CPU time | 3.92 seconds |
Started | Aug 09 07:13:32 PM PDT 24 |
Finished | Aug 09 07:13:36 PM PDT 24 |
Peak memory | 205720 kb |
Host | smart-863cd16d-d0a3-4968-9ea3-2177a654f19a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165808754 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.3165808754 |
Directory | /workspace/3.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/3.rv_dm_stress_all_with_rand_reset.1124419437 |
Short name | T75 |
Test name | |
Test status | |
Simulation time | 43460551294 ps |
CPU time | 669.45 seconds |
Started | Aug 09 07:13:31 PM PDT 24 |
Finished | Aug 09 07:24:41 PM PDT 24 |
Peak memory | 228144 kb |
Host | smart-73b0cce3-1498-43b1-ac1e-504c471e00a6 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124419437 -assert nopost proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all_with_rand_reset.1124419437 |
Directory | /workspace/3.rv_dm_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/30.rv_dm_alert_test.1659745422 |
Short name | T63 |
Test name | |
Test status | |
Simulation time | 136182722 ps |
CPU time | 1.15 seconds |
Started | Aug 09 07:13:55 PM PDT 24 |
Finished | Aug 09 07:13:56 PM PDT 24 |
Peak memory | 205316 kb |
Host | smart-61d2f898-f87a-4562-a73f-3edcc40ece0c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659745422 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.1659745422 |
Directory | /workspace/30.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/30.rv_dm_stress_all.839299154 |
Short name | T304 |
Test name | |
Test status | |
Simulation time | 5691652570 ps |
CPU time | 15.37 seconds |
Started | Aug 09 07:13:52 PM PDT 24 |
Finished | Aug 09 07:14:07 PM PDT 24 |
Peak memory | 205568 kb |
Host | smart-126081bb-b1a6-456c-ba32-9da156988eab |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839299154 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.839299154 |
Directory | /workspace/30.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/31.rv_dm_alert_test.1743868217 |
Short name | T200 |
Test name | |
Test status | |
Simulation time | 69277510 ps |
CPU time | 0.78 seconds |
Started | Aug 09 07:13:55 PM PDT 24 |
Finished | Aug 09 07:13:56 PM PDT 24 |
Peak memory | 205260 kb |
Host | smart-976f4341-d2ab-4a47-b804-373e2275eead |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743868217 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.1743868217 |
Directory | /workspace/31.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/31.rv_dm_stress_all.1820295951 |
Short name | T133 |
Test name | |
Test status | |
Simulation time | 6435153422 ps |
CPU time | 9.56 seconds |
Started | Aug 09 07:13:55 PM PDT 24 |
Finished | Aug 09 07:14:04 PM PDT 24 |
Peak memory | 205588 kb |
Host | smart-fa523aee-2b5e-4f99-a5c3-2e5d929c9bd0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820295951 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.1820295951 |
Directory | /workspace/31.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/32.rv_dm_alert_test.92720399 |
Short name | T241 |
Test name | |
Test status | |
Simulation time | 114766170 ps |
CPU time | 0.77 seconds |
Started | Aug 09 07:13:55 PM PDT 24 |
Finished | Aug 09 07:13:56 PM PDT 24 |
Peak memory | 205248 kb |
Host | smart-adaebaa8-1806-4922-86b4-6e47a13de7bb |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92720399 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.92720399 |
Directory | /workspace/32.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/33.rv_dm_alert_test.1718526715 |
Short name | T259 |
Test name | |
Test status | |
Simulation time | 237745211 ps |
CPU time | 0.83 seconds |
Started | Aug 09 07:13:52 PM PDT 24 |
Finished | Aug 09 07:13:53 PM PDT 24 |
Peak memory | 205276 kb |
Host | smart-202e4d1e-5150-4ec8-a559-46a0f4375be4 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718526715 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.1718526715 |
Directory | /workspace/33.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/34.rv_dm_alert_test.1278248658 |
Short name | T212 |
Test name | |
Test status | |
Simulation time | 69057294 ps |
CPU time | 0.76 seconds |
Started | Aug 09 07:13:54 PM PDT 24 |
Finished | Aug 09 07:13:55 PM PDT 24 |
Peak memory | 205264 kb |
Host | smart-1b4847f8-f8c4-4199-b638-5bbb74cb1367 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278248658 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.1278248658 |
Directory | /workspace/34.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/34.rv_dm_stress_all.3642915441 |
Short name | T1 |
Test name | |
Test status | |
Simulation time | 4291323728 ps |
CPU time | 2.73 seconds |
Started | Aug 09 07:13:52 PM PDT 24 |
Finished | Aug 09 07:13:55 PM PDT 24 |
Peak memory | 213728 kb |
Host | smart-54033146-9bee-40db-9c71-2dbafa56f734 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642915441 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.3642915441 |
Directory | /workspace/34.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/35.rv_dm_stress_all.2075964852 |
Short name | T43 |
Test name | |
Test status | |
Simulation time | 2946520833 ps |
CPU time | 2.09 seconds |
Started | Aug 09 07:13:54 PM PDT 24 |
Finished | Aug 09 07:13:56 PM PDT 24 |
Peak memory | 205632 kb |
Host | smart-4f9b0884-d06b-4494-91a6-c223d6f02a5c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075964852 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.2075964852 |
Directory | /workspace/35.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/36.rv_dm_alert_test.1085845247 |
Short name | T240 |
Test name | |
Test status | |
Simulation time | 65778207 ps |
CPU time | 0.72 seconds |
Started | Aug 09 07:13:53 PM PDT 24 |
Finished | Aug 09 07:13:53 PM PDT 24 |
Peak memory | 205192 kb |
Host | smart-cc0a5546-f93c-4195-8cf3-cd80ce7a69d0 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085845247 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.1085845247 |
Directory | /workspace/36.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/36.rv_dm_stress_all.329648163 |
Short name | T283 |
Test name | |
Test status | |
Simulation time | 6432313264 ps |
CPU time | 8.82 seconds |
Started | Aug 09 07:14:00 PM PDT 24 |
Finished | Aug 09 07:14:08 PM PDT 24 |
Peak memory | 214492 kb |
Host | smart-b2c700e6-5645-4f6a-a774-84f83546b4f4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329648163 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.329648163 |
Directory | /workspace/36.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/37.rv_dm_alert_test.2265134957 |
Short name | T3 |
Test name | |
Test status | |
Simulation time | 142747369 ps |
CPU time | 0.9 seconds |
Started | Aug 09 07:13:58 PM PDT 24 |
Finished | Aug 09 07:13:59 PM PDT 24 |
Peak memory | 205276 kb |
Host | smart-bd8500a4-9256-4338-bd28-1cc207d4be4c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265134957 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.2265134957 |
Directory | /workspace/37.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/37.rv_dm_stress_all.4191459891 |
Short name | T275 |
Test name | |
Test status | |
Simulation time | 1219633641 ps |
CPU time | 3.91 seconds |
Started | Aug 09 07:13:59 PM PDT 24 |
Finished | Aug 09 07:14:03 PM PDT 24 |
Peak memory | 205500 kb |
Host | smart-c1c85286-acfc-47de-832a-772d89a874c6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191459891 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.4191459891 |
Directory | /workspace/37.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/38.rv_dm_alert_test.2042995480 |
Short name | T170 |
Test name | |
Test status | |
Simulation time | 44857356 ps |
CPU time | 0.8 seconds |
Started | Aug 09 07:13:57 PM PDT 24 |
Finished | Aug 09 07:13:58 PM PDT 24 |
Peak memory | 205508 kb |
Host | smart-2abfac06-b7bb-4d99-b76f-f720dbe94aad |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042995480 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.2042995480 |
Directory | /workspace/38.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/38.rv_dm_stress_all.4207361873 |
Short name | T37 |
Test name | |
Test status | |
Simulation time | 8313886611 ps |
CPU time | 6.44 seconds |
Started | Aug 09 07:14:00 PM PDT 24 |
Finished | Aug 09 07:14:06 PM PDT 24 |
Peak memory | 213820 kb |
Host | smart-e1dc6374-9145-4c71-9885-daa699dbfd58 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207361873 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.4207361873 |
Directory | /workspace/38.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/39.rv_dm_alert_test.630782579 |
Short name | T277 |
Test name | |
Test status | |
Simulation time | 51849492 ps |
CPU time | 0.75 seconds |
Started | Aug 09 07:13:57 PM PDT 24 |
Finished | Aug 09 07:13:58 PM PDT 24 |
Peak memory | 205240 kb |
Host | smart-109696dd-1de5-4cad-a268-4b1263727df5 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630782579 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.630782579 |
Directory | /workspace/39.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/39.rv_dm_stress_all.17563561 |
Short name | T49 |
Test name | |
Test status | |
Simulation time | 2916181321 ps |
CPU time | 2.1 seconds |
Started | Aug 09 07:13:57 PM PDT 24 |
Finished | Aug 09 07:13:59 PM PDT 24 |
Peak memory | 205544 kb |
Host | smart-e314d0ee-cc91-495b-b67f-b1854b0dc97d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17563561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.17563561 |
Directory | /workspace/39.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/4.rv_dm_alert_test.1315105414 |
Short name | T184 |
Test name | |
Test status | |
Simulation time | 103762230 ps |
CPU time | 0.7 seconds |
Started | Aug 09 07:13:31 PM PDT 24 |
Finished | Aug 09 07:13:32 PM PDT 24 |
Peak memory | 205272 kb |
Host | smart-328757c5-7adf-4fc0-a299-ea52195df5d7 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315105414 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.1315105414 |
Directory | /workspace/4.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.2748488439 |
Short name | T29 |
Test name | |
Test status | |
Simulation time | 21643498393 ps |
CPU time | 16.45 seconds |
Started | Aug 09 07:13:33 PM PDT 24 |
Finished | Aug 09 07:13:49 PM PDT 24 |
Peak memory | 213952 kb |
Host | smart-68cbea0f-cd09-467b-b1a4-a769dafd9892 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2748488439 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.2748488439 |
Directory | /workspace/4.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.2210146568 |
Short name | T293 |
Test name | |
Test status | |
Simulation time | 1164875762 ps |
CPU time | 4.11 seconds |
Started | Aug 09 07:13:42 PM PDT 24 |
Finished | Aug 09 07:13:47 PM PDT 24 |
Peak memory | 205600 kb |
Host | smart-78bdc3ad-3f8b-44ed-ac7d-9f70f16acbc7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2210146568 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.2210146568 |
Directory | /workspace/4.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.2017823790 |
Short name | T168 |
Test name | |
Test status | |
Simulation time | 738260711 ps |
CPU time | 1.49 seconds |
Started | Aug 09 07:13:31 PM PDT 24 |
Finished | Aug 09 07:13:33 PM PDT 24 |
Peak memory | 205656 kb |
Host | smart-d6fed671-123f-4a01-bd1f-bcb0f68b78b6 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2017823790 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t l_access.2017823790 |
Directory | /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_halt_resume_whereto.1320116270 |
Short name | T162 |
Test name | |
Test status | |
Simulation time | 1246434288 ps |
CPU time | 1.57 seconds |
Started | Aug 09 07:13:37 PM PDT 24 |
Finished | Aug 09 07:13:38 PM PDT 24 |
Peak memory | 205256 kb |
Host | smart-a9bcf7b8-bbd4-4577-8303-ec9401074eec |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1320116270 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_halt_resume_whereto.1320116270 |
Directory | /workspace/4.rv_dm_halt_resume_whereto/latest |
Test location | /workspace/coverage/default/4.rv_dm_hart_unavail.1145016164 |
Short name | T69 |
Test name | |
Test status | |
Simulation time | 296403292 ps |
CPU time | 0.89 seconds |
Started | Aug 09 07:13:32 PM PDT 24 |
Finished | Aug 09 07:13:33 PM PDT 24 |
Peak memory | 205508 kb |
Host | smart-3b157f13-c156-4435-8df2-02c451e28193 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1145016164 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.1145016164 |
Directory | /workspace/4.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/4.rv_dm_sba_tl_access.3992246393 |
Short name | T233 |
Test name | |
Test status | |
Simulation time | 6116800945 ps |
CPU time | 19.35 seconds |
Started | Aug 09 07:13:34 PM PDT 24 |
Finished | Aug 09 07:13:53 PM PDT 24 |
Peak memory | 213892 kb |
Host | smart-5153a06c-26c0-453a-9b87-478525d6fb09 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3992246393 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.3992246393 |
Directory | /workspace/4.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_sec_cm.1791357720 |
Short name | T46 |
Test name | |
Test status | |
Simulation time | 1885695371 ps |
CPU time | 4.84 seconds |
Started | Aug 09 07:13:41 PM PDT 24 |
Finished | Aug 09 07:13:46 PM PDT 24 |
Peak memory | 229440 kb |
Host | smart-31688c79-e71c-4765-8b5b-5cf181ed95c5 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791357720 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.1791357720 |
Directory | /workspace/4.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/4.rv_dm_stress_all_with_rand_reset.2305290796 |
Short name | T10 |
Test name | |
Test status | |
Simulation time | 537492608707 ps |
CPU time | 491.97 seconds |
Started | Aug 09 07:13:37 PM PDT 24 |
Finished | Aug 09 07:21:49 PM PDT 24 |
Peak memory | 238476 kb |
Host | smart-a9d9907a-e809-4f9a-9c0a-706bc7b88e3b |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305290796 -assert nopost proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all_with_rand_reset.2305290796 |
Directory | /workspace/4.rv_dm_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/40.rv_dm_alert_test.574848086 |
Short name | T178 |
Test name | |
Test status | |
Simulation time | 72346596 ps |
CPU time | 0.86 seconds |
Started | Aug 09 07:14:00 PM PDT 24 |
Finished | Aug 09 07:14:01 PM PDT 24 |
Peak memory | 205288 kb |
Host | smart-d0d7684a-40a0-496b-877b-dca981b41ee9 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574848086 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.574848086 |
Directory | /workspace/40.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/40.rv_dm_stress_all.1184630663 |
Short name | T262 |
Test name | |
Test status | |
Simulation time | 2980246007 ps |
CPU time | 3.74 seconds |
Started | Aug 09 07:14:00 PM PDT 24 |
Finished | Aug 09 07:14:04 PM PDT 24 |
Peak memory | 205384 kb |
Host | smart-c78b7f0e-73ca-49c3-babc-84751394e416 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184630663 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.1184630663 |
Directory | /workspace/40.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/41.rv_dm_alert_test.3962271679 |
Short name | T226 |
Test name | |
Test status | |
Simulation time | 51353200 ps |
CPU time | 0.72 seconds |
Started | Aug 09 07:13:58 PM PDT 24 |
Finished | Aug 09 07:13:59 PM PDT 24 |
Peak memory | 205300 kb |
Host | smart-6177f54a-cc9d-4232-8414-ac35dfd106c3 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962271679 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.3962271679 |
Directory | /workspace/41.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/41.rv_dm_stress_all.356144964 |
Short name | T290 |
Test name | |
Test status | |
Simulation time | 4190440724 ps |
CPU time | 3.86 seconds |
Started | Aug 09 07:13:57 PM PDT 24 |
Finished | Aug 09 07:14:01 PM PDT 24 |
Peak memory | 213724 kb |
Host | smart-09e91dec-3f4a-4417-8425-17ad3893139f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356144964 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.356144964 |
Directory | /workspace/41.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/42.rv_dm_alert_test.1098766430 |
Short name | T203 |
Test name | |
Test status | |
Simulation time | 70265811 ps |
CPU time | 0.75 seconds |
Started | Aug 09 07:13:56 PM PDT 24 |
Finished | Aug 09 07:13:57 PM PDT 24 |
Peak memory | 205300 kb |
Host | smart-8de3503a-0063-46bc-b340-967c2276f732 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098766430 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.1098766430 |
Directory | /workspace/42.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/42.rv_dm_stress_all.1399103727 |
Short name | T291 |
Test name | |
Test status | |
Simulation time | 4737617312 ps |
CPU time | 3.91 seconds |
Started | Aug 09 07:14:00 PM PDT 24 |
Finished | Aug 09 07:14:04 PM PDT 24 |
Peak memory | 213860 kb |
Host | smart-c6f82228-5105-420e-9922-a10756eda0c4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399103727 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.1399103727 |
Directory | /workspace/42.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/43.rv_dm_alert_test.2726021287 |
Short name | T169 |
Test name | |
Test status | |
Simulation time | 65569414 ps |
CPU time | 0.88 seconds |
Started | Aug 09 07:13:59 PM PDT 24 |
Finished | Aug 09 07:14:00 PM PDT 24 |
Peak memory | 205296 kb |
Host | smart-09563c57-9b79-4bcd-b2f8-1c51ec82d5a0 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726021287 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.2726021287 |
Directory | /workspace/43.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/43.rv_dm_stress_all.3088133066 |
Short name | T36 |
Test name | |
Test status | |
Simulation time | 6073155813 ps |
CPU time | 2.38 seconds |
Started | Aug 09 07:13:56 PM PDT 24 |
Finished | Aug 09 07:13:59 PM PDT 24 |
Peak memory | 213768 kb |
Host | smart-55a23d9a-8b17-499f-ad1b-a2102a166ef0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088133066 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.3088133066 |
Directory | /workspace/43.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/44.rv_dm_alert_test.2155378576 |
Short name | T54 |
Test name | |
Test status | |
Simulation time | 55721608 ps |
CPU time | 0.75 seconds |
Started | Aug 09 07:13:56 PM PDT 24 |
Finished | Aug 09 07:13:57 PM PDT 24 |
Peak memory | 205324 kb |
Host | smart-a39bc8ca-3a88-47ee-9e0b-ac4ef9c18438 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155378576 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.2155378576 |
Directory | /workspace/44.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/44.rv_dm_stress_all.3850694299 |
Short name | T134 |
Test name | |
Test status | |
Simulation time | 2928699398 ps |
CPU time | 4.82 seconds |
Started | Aug 09 07:13:57 PM PDT 24 |
Finished | Aug 09 07:14:02 PM PDT 24 |
Peak memory | 205872 kb |
Host | smart-a8285aee-4fa2-4a6b-820c-4017fcbb851b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850694299 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.3850694299 |
Directory | /workspace/44.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/45.rv_dm_alert_test.4027926170 |
Short name | T258 |
Test name | |
Test status | |
Simulation time | 87464174 ps |
CPU time | 0.79 seconds |
Started | Aug 09 07:14:03 PM PDT 24 |
Finished | Aug 09 07:14:04 PM PDT 24 |
Peak memory | 205264 kb |
Host | smart-92b5b32e-98bd-4610-9208-9fd71899070b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027926170 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.4027926170 |
Directory | /workspace/45.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/45.rv_dm_stress_all.1283417959 |
Short name | T163 |
Test name | |
Test status | |
Simulation time | 7452596024 ps |
CPU time | 5.88 seconds |
Started | Aug 09 07:13:58 PM PDT 24 |
Finished | Aug 09 07:14:04 PM PDT 24 |
Peak memory | 205576 kb |
Host | smart-0f0cc311-1cca-47dc-93b7-75a385095102 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283417959 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.1283417959 |
Directory | /workspace/45.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/46.rv_dm_alert_test.1196919385 |
Short name | T249 |
Test name | |
Test status | |
Simulation time | 41078476 ps |
CPU time | 0.75 seconds |
Started | Aug 09 07:13:59 PM PDT 24 |
Finished | Aug 09 07:14:00 PM PDT 24 |
Peak memory | 205312 kb |
Host | smart-2d18c4b8-4efc-4f70-bc82-00308e7e76ff |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196919385 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.1196919385 |
Directory | /workspace/46.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/46.rv_dm_stress_all.137955655 |
Short name | T122 |
Test name | |
Test status | |
Simulation time | 5679455425 ps |
CPU time | 4.93 seconds |
Started | Aug 09 07:14:02 PM PDT 24 |
Finished | Aug 09 07:14:07 PM PDT 24 |
Peak memory | 213660 kb |
Host | smart-c8fbbace-dfe1-4800-bca7-db253b772c3e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137955655 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.137955655 |
Directory | /workspace/46.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/47.rv_dm_alert_test.1938329520 |
Short name | T244 |
Test name | |
Test status | |
Simulation time | 48400512 ps |
CPU time | 0.75 seconds |
Started | Aug 09 07:13:56 PM PDT 24 |
Finished | Aug 09 07:13:57 PM PDT 24 |
Peak memory | 205276 kb |
Host | smart-862a5b4f-c8b8-44ad-8f0b-9f8ce749b39b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938329520 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.1938329520 |
Directory | /workspace/47.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/47.rv_dm_stress_all.4070169695 |
Short name | T274 |
Test name | |
Test status | |
Simulation time | 6165909087 ps |
CPU time | 17.62 seconds |
Started | Aug 09 07:13:58 PM PDT 24 |
Finished | Aug 09 07:14:16 PM PDT 24 |
Peak memory | 213860 kb |
Host | smart-fb3b4a51-7be6-4dec-9165-b3193d1bd66b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070169695 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.4070169695 |
Directory | /workspace/47.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/48.rv_dm_alert_test.4123821353 |
Short name | T231 |
Test name | |
Test status | |
Simulation time | 119055753 ps |
CPU time | 0.87 seconds |
Started | Aug 09 07:13:57 PM PDT 24 |
Finished | Aug 09 07:13:58 PM PDT 24 |
Peak memory | 205276 kb |
Host | smart-5070c6a9-7efa-415f-8826-34481650b0aa |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123821353 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.4123821353 |
Directory | /workspace/48.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/48.rv_dm_stress_all.3678335977 |
Short name | T253 |
Test name | |
Test status | |
Simulation time | 2258663964 ps |
CPU time | 4.46 seconds |
Started | Aug 09 07:13:57 PM PDT 24 |
Finished | Aug 09 07:14:01 PM PDT 24 |
Peak memory | 212652 kb |
Host | smart-d1bec11c-5513-421f-bf30-91b6924e746c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678335977 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.3678335977 |
Directory | /workspace/48.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/49.rv_dm_alert_test.1729869442 |
Short name | T32 |
Test name | |
Test status | |
Simulation time | 50882176 ps |
CPU time | 0.74 seconds |
Started | Aug 09 07:13:56 PM PDT 24 |
Finished | Aug 09 07:13:57 PM PDT 24 |
Peak memory | 205316 kb |
Host | smart-266651d5-0294-4c1d-81e3-d883fba5a291 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729869442 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.1729869442 |
Directory | /workspace/49.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/49.rv_dm_stress_all.1849601805 |
Short name | T238 |
Test name | |
Test status | |
Simulation time | 7828017749 ps |
CPU time | 7.37 seconds |
Started | Aug 09 07:14:00 PM PDT 24 |
Finished | Aug 09 07:14:08 PM PDT 24 |
Peak memory | 205588 kb |
Host | smart-2f6d5054-754f-446e-821c-65493ff3360c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849601805 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.1849601805 |
Directory | /workspace/49.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/5.rv_dm_alert_test.1699408751 |
Short name | T209 |
Test name | |
Test status | |
Simulation time | 111905561 ps |
CPU time | 0.77 seconds |
Started | Aug 09 07:13:31 PM PDT 24 |
Finished | Aug 09 07:13:32 PM PDT 24 |
Peak memory | 205268 kb |
Host | smart-e03314f6-66bd-430d-9fef-175f96416858 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699408751 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.1699408751 |
Directory | /workspace/5.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.1335044780 |
Short name | T137 |
Test name | |
Test status | |
Simulation time | 4771753471 ps |
CPU time | 4.94 seconds |
Started | Aug 09 07:13:40 PM PDT 24 |
Finished | Aug 09 07:13:45 PM PDT 24 |
Peak memory | 213988 kb |
Host | smart-94bc21ec-be48-4a08-9200-79212579d6f7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1335044780 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.1335044780 |
Directory | /workspace/5.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.2448572496 |
Short name | T71 |
Test name | |
Test status | |
Simulation time | 4760342607 ps |
CPU time | 12.52 seconds |
Started | Aug 09 07:13:33 PM PDT 24 |
Finished | Aug 09 07:13:46 PM PDT 24 |
Peak memory | 213872 kb |
Host | smart-8c047ebf-3404-459a-8f0f-4eab89f3bcac |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2448572496 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.2448572496 |
Directory | /workspace/5.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.1062908416 |
Short name | T198 |
Test name | |
Test status | |
Simulation time | 6351219430 ps |
CPU time | 9.4 seconds |
Started | Aug 09 07:13:34 PM PDT 24 |
Finished | Aug 09 07:13:43 PM PDT 24 |
Peak memory | 213920 kb |
Host | smart-8eecfa32-073d-4f53-a146-5a717e947047 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1062908416 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t l_access.1062908416 |
Directory | /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/5.rv_dm_halt_resume_whereto.2690551542 |
Short name | T40 |
Test name | |
Test status | |
Simulation time | 957488535 ps |
CPU time | 1.35 seconds |
Started | Aug 09 07:13:41 PM PDT 24 |
Finished | Aug 09 07:13:43 PM PDT 24 |
Peak memory | 205104 kb |
Host | smart-71e78992-d20e-4bb7-9984-f6d2092cf0cc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2690551542 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_halt_resume_whereto.2690551542 |
Directory | /workspace/5.rv_dm_halt_resume_whereto/latest |
Test location | /workspace/coverage/default/5.rv_dm_sba_tl_access.1695620506 |
Short name | T204 |
Test name | |
Test status | |
Simulation time | 2969941168 ps |
CPU time | 4.72 seconds |
Started | Aug 09 07:13:31 PM PDT 24 |
Finished | Aug 09 07:13:36 PM PDT 24 |
Peak memory | 205692 kb |
Host | smart-306a57a3-c0e2-4498-8797-7f94fa09abb3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1695620506 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.1695620506 |
Directory | /workspace/5.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/5.rv_dm_stress_all.3972825407 |
Short name | T282 |
Test name | |
Test status | |
Simulation time | 7366025748 ps |
CPU time | 14.69 seconds |
Started | Aug 09 07:13:33 PM PDT 24 |
Finished | Aug 09 07:13:47 PM PDT 24 |
Peak memory | 205612 kb |
Host | smart-880efa9f-895d-4e27-8977-8d823846681d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972825407 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.3972825407 |
Directory | /workspace/5.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/6.rv_dm_alert_test.2601918738 |
Short name | T242 |
Test name | |
Test status | |
Simulation time | 105949909 ps |
CPU time | 1.01 seconds |
Started | Aug 09 07:13:41 PM PDT 24 |
Finished | Aug 09 07:13:42 PM PDT 24 |
Peak memory | 205288 kb |
Host | smart-cfcdded4-62a9-4d18-a390-6932138457a0 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601918738 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.2601918738 |
Directory | /workspace/6.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.769343001 |
Short name | T207 |
Test name | |
Test status | |
Simulation time | 142418489773 ps |
CPU time | 200.17 seconds |
Started | Aug 09 07:13:33 PM PDT 24 |
Finished | Aug 09 07:16:54 PM PDT 24 |
Peak memory | 221992 kb |
Host | smart-67b51a8d-9665-4d5c-8f6e-341b403a9b4a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=769343001 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.769343001 |
Directory | /workspace/6.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.3942686570 |
Short name | T267 |
Test name | |
Test status | |
Simulation time | 8480978114 ps |
CPU time | 9.66 seconds |
Started | Aug 09 07:13:31 PM PDT 24 |
Finished | Aug 09 07:13:41 PM PDT 24 |
Peak memory | 213956 kb |
Host | smart-9cf4d3f8-49bc-4de3-89f9-ce793f763b79 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3942686570 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.3942686570 |
Directory | /workspace/6.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.3820632325 |
Short name | T195 |
Test name | |
Test status | |
Simulation time | 2390587758 ps |
CPU time | 7.24 seconds |
Started | Aug 09 07:13:37 PM PDT 24 |
Finished | Aug 09 07:13:45 PM PDT 24 |
Peak memory | 205640 kb |
Host | smart-f55f8058-05fb-48a1-852d-92ff58b629a7 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3820632325 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t l_access.3820632325 |
Directory | /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/6.rv_dm_halt_resume_whereto.2950927886 |
Short name | T42 |
Test name | |
Test status | |
Simulation time | 1142850221 ps |
CPU time | 2.37 seconds |
Started | Aug 09 07:13:31 PM PDT 24 |
Finished | Aug 09 07:13:34 PM PDT 24 |
Peak memory | 205292 kb |
Host | smart-75569220-dbdf-47b9-ad32-35cf6cdc5f1a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2950927886 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_halt_resume_whereto.2950927886 |
Directory | /workspace/6.rv_dm_halt_resume_whereto/latest |
Test location | /workspace/coverage/default/6.rv_dm_sba_tl_access.4084989325 |
Short name | T128 |
Test name | |
Test status | |
Simulation time | 2132903571 ps |
CPU time | 3.98 seconds |
Started | Aug 09 07:13:40 PM PDT 24 |
Finished | Aug 09 07:13:45 PM PDT 24 |
Peak memory | 213856 kb |
Host | smart-41fa8b21-a8a9-4f41-95e7-48f00c0f20ab |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4084989325 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.4084989325 |
Directory | /workspace/6.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/6.rv_dm_stress_all.1273548095 |
Short name | T298 |
Test name | |
Test status | |
Simulation time | 6338752927 ps |
CPU time | 8.46 seconds |
Started | Aug 09 07:13:31 PM PDT 24 |
Finished | Aug 09 07:13:40 PM PDT 24 |
Peak memory | 205672 kb |
Host | smart-40b1e42d-f8ff-4930-b331-8a34fe8e16d0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273548095 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.1273548095 |
Directory | /workspace/6.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/7.rv_dm_alert_test.2494625212 |
Short name | T303 |
Test name | |
Test status | |
Simulation time | 106424563 ps |
CPU time | 0.76 seconds |
Started | Aug 09 07:13:35 PM PDT 24 |
Finished | Aug 09 07:13:36 PM PDT 24 |
Peak memory | 205236 kb |
Host | smart-70a41ef2-755a-423f-85e2-60af2a2810b7 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494625212 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.2494625212 |
Directory | /workspace/7.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.419731584 |
Short name | T27 |
Test name | |
Test status | |
Simulation time | 8362239073 ps |
CPU time | 21.96 seconds |
Started | Aug 09 07:13:33 PM PDT 24 |
Finished | Aug 09 07:13:55 PM PDT 24 |
Peak memory | 216104 kb |
Host | smart-f3e2af55-23e1-4aa8-abfa-bda0353850fa |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=419731584 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.419731584 |
Directory | /workspace/7.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.1163019358 |
Short name | T123 |
Test name | |
Test status | |
Simulation time | 1734176426 ps |
CPU time | 1.61 seconds |
Started | Aug 09 07:13:33 PM PDT 24 |
Finished | Aug 09 07:13:35 PM PDT 24 |
Peak memory | 214780 kb |
Host | smart-a99756b6-fa38-4b65-983e-9dffed267980 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1163019358 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.1163019358 |
Directory | /workspace/7.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.3069545386 |
Short name | T208 |
Test name | |
Test status | |
Simulation time | 4683156919 ps |
CPU time | 7.08 seconds |
Started | Aug 09 07:13:29 PM PDT 24 |
Finished | Aug 09 07:13:37 PM PDT 24 |
Peak memory | 205748 kb |
Host | smart-b64a0ffa-f7d0-4a92-9dd4-509727b88e88 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3069545386 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t l_access.3069545386 |
Directory | /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_halt_resume_whereto.3865426145 |
Short name | T232 |
Test name | |
Test status | |
Simulation time | 343112399 ps |
CPU time | 1 seconds |
Started | Aug 09 07:13:32 PM PDT 24 |
Finished | Aug 09 07:13:33 PM PDT 24 |
Peak memory | 205300 kb |
Host | smart-23ced4be-c93f-4b1a-8de2-45df24e0d8b5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3865426145 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_halt_resume_whereto.3865426145 |
Directory | /workspace/7.rv_dm_halt_resume_whereto/latest |
Test location | /workspace/coverage/default/7.rv_dm_sba_tl_access.2149497148 |
Short name | T191 |
Test name | |
Test status | |
Simulation time | 2488832747 ps |
CPU time | 5.83 seconds |
Started | Aug 09 07:13:34 PM PDT 24 |
Finished | Aug 09 07:13:40 PM PDT 24 |
Peak memory | 213956 kb |
Host | smart-b2c0d0b7-1f18-46a9-889c-cbd1fc4bb8e5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2149497148 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.2149497148 |
Directory | /workspace/7.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_stress_all.3272016589 |
Short name | T62 |
Test name | |
Test status | |
Simulation time | 3380751937 ps |
CPU time | 3.64 seconds |
Started | Aug 09 07:13:34 PM PDT 24 |
Finished | Aug 09 07:13:38 PM PDT 24 |
Peak memory | 213776 kb |
Host | smart-46ae4e64-87b1-4354-ac4f-a0be983eef4f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272016589 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.3272016589 |
Directory | /workspace/7.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/8.rv_dm_alert_test.2120541089 |
Short name | T269 |
Test name | |
Test status | |
Simulation time | 111702866 ps |
CPU time | 0.78 seconds |
Started | Aug 09 07:13:41 PM PDT 24 |
Finished | Aug 09 07:13:42 PM PDT 24 |
Peak memory | 205260 kb |
Host | smart-8a398ea8-e771-4fef-a841-205a34abeef0 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120541089 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.2120541089 |
Directory | /workspace/8.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.2867152112 |
Short name | T28 |
Test name | |
Test status | |
Simulation time | 132034213228 ps |
CPU time | 61.52 seconds |
Started | Aug 09 07:13:40 PM PDT 24 |
Finished | Aug 09 07:14:42 PM PDT 24 |
Peak memory | 221888 kb |
Host | smart-ac6b2707-61da-4a94-a9a1-c653ad7712bb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2867152112 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.2867152112 |
Directory | /workspace/8.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.1489416832 |
Short name | T228 |
Test name | |
Test status | |
Simulation time | 2285133305 ps |
CPU time | 1.98 seconds |
Started | Aug 09 07:13:31 PM PDT 24 |
Finished | Aug 09 07:13:33 PM PDT 24 |
Peak memory | 213988 kb |
Host | smart-9d92f9b3-1c62-48bc-aea6-9c671c9ea666 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1489416832 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.1489416832 |
Directory | /workspace/8.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.3809047317 |
Short name | T181 |
Test name | |
Test status | |
Simulation time | 7346206081 ps |
CPU time | 21.44 seconds |
Started | Aug 09 07:13:40 PM PDT 24 |
Finished | Aug 09 07:14:02 PM PDT 24 |
Peak memory | 213932 kb |
Host | smart-095bfa40-d34c-45be-989e-af9dc6238b99 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3809047317 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_t l_access.3809047317 |
Directory | /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/8.rv_dm_sba_tl_access.3089705116 |
Short name | T294 |
Test name | |
Test status | |
Simulation time | 7800377002 ps |
CPU time | 7.24 seconds |
Started | Aug 09 07:13:40 PM PDT 24 |
Finished | Aug 09 07:13:47 PM PDT 24 |
Peak memory | 205688 kb |
Host | smart-27325832-db9e-47b7-aff0-9f7eb3d2571f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3089705116 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.3089705116 |
Directory | /workspace/8.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/8.rv_dm_stress_all.2375334166 |
Short name | T213 |
Test name | |
Test status | |
Simulation time | 3228624905 ps |
CPU time | 9.67 seconds |
Started | Aug 09 07:13:35 PM PDT 24 |
Finished | Aug 09 07:13:45 PM PDT 24 |
Peak memory | 205552 kb |
Host | smart-33ec0d42-65c9-4913-9528-53f5168e9994 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375334166 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.2375334166 |
Directory | /workspace/8.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/9.rv_dm_alert_test.4236680596 |
Short name | T289 |
Test name | |
Test status | |
Simulation time | 220997122 ps |
CPU time | 0.77 seconds |
Started | Aug 09 07:13:42 PM PDT 24 |
Finished | Aug 09 07:13:42 PM PDT 24 |
Peak memory | 205264 kb |
Host | smart-7e25d94e-4039-4df8-9538-4c643285c889 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236680596 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.4236680596 |
Directory | /workspace/9.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.3560253630 |
Short name | T248 |
Test name | |
Test status | |
Simulation time | 5632869709 ps |
CPU time | 5.46 seconds |
Started | Aug 09 07:13:34 PM PDT 24 |
Finished | Aug 09 07:13:39 PM PDT 24 |
Peak memory | 216208 kb |
Host | smart-23abb026-433a-46f2-987d-8c31a01fd558 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3560253630 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.3560253630 |
Directory | /workspace/9.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.4140409691 |
Short name | T11 |
Test name | |
Test status | |
Simulation time | 1266103737 ps |
CPU time | 4.46 seconds |
Started | Aug 09 07:13:40 PM PDT 24 |
Finished | Aug 09 07:13:45 PM PDT 24 |
Peak memory | 213748 kb |
Host | smart-8a330d6e-fcbd-4575-b0ec-c89ecf4d89ce |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4140409691 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.4140409691 |
Directory | /workspace/9.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.143107752 |
Short name | T278 |
Test name | |
Test status | |
Simulation time | 11235757812 ps |
CPU time | 34.53 seconds |
Started | Aug 09 07:13:33 PM PDT 24 |
Finished | Aug 09 07:14:08 PM PDT 24 |
Peak memory | 213928 kb |
Host | smart-de9ff369-23a5-47d5-b2de-3014956fc96f |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=143107752 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_tl _access.143107752 |
Directory | /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_sba_tl_access.576908297 |
Short name | T216 |
Test name | |
Test status | |
Simulation time | 5045304971 ps |
CPU time | 12.87 seconds |
Started | Aug 09 07:13:41 PM PDT 24 |
Finished | Aug 09 07:13:54 PM PDT 24 |
Peak memory | 213968 kb |
Host | smart-2b4b6b0a-ce61-4487-b2fe-955d27f8c4f7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=576908297 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.576908297 |
Directory | /workspace/9.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_stress_all.2844779839 |
Short name | T177 |
Test name | |
Test status | |
Simulation time | 4275876240 ps |
CPU time | 11.57 seconds |
Started | Aug 09 07:13:41 PM PDT 24 |
Finished | Aug 09 07:13:52 PM PDT 24 |
Peak memory | 213800 kb |
Host | smart-c2d2eeba-e45f-435b-8a2c-63d52390745d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844779839 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.2844779839 |
Directory | /workspace/9.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/9.rv_dm_stress_all_with_rand_reset.1944320165 |
Short name | T8 |
Test name | |
Test status | |
Simulation time | 149467333850 ps |
CPU time | 654.51 seconds |
Started | Aug 09 07:13:33 PM PDT 24 |
Finished | Aug 09 07:24:28 PM PDT 24 |
Peak memory | 230904 kb |
Host | smart-ac38d3bc-7a13-406a-ba06-139cd36f9aea |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944320165 -assert nopost proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all_with_rand_reset.1944320165 |
Directory | /workspace/9.rv_dm_stress_all_with_rand_reset/latest |
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