Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	462702	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

787515

1

T3

7

T5

4

T6

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	576807	1			T3	4		T5	3		T6	3
values[0x0]	237614	1			T3	11		T4	1		T5	3
values[0x1]	435796	1			T3	10		T4	3		T5	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	255597	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

994620

1

T3

10

T5

4

T6

5

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4451	1			T20	448		T24	1		T151	1
valid_sources[0x01]	4812	1			T20	466		T10	1		T21	109
valid_sources[0x02]	4497	1			T37	1		T20	441		T10	1
valid_sources[0x03]	5419	1			T37	1		T20	419		T21	80
valid_sources[0x04]	4784	1			T20	412		T144	1		T21	117
valid_sources[0x05]	4652	1			T20	462		T21	104		T42	405
valid_sources[0x06]	4975	1			T37	1		T20	428		T21	139
valid_sources[0x07]	4347	1			T37	1		T20	440		T21	128
valid_sources[0x08]	4692	1			T20	467		T21	124		T42	383
valid_sources[0x09]	5330	1			T20	493		T21	130		T42	392
valid_sources[0x0a]	4584	1			T20	423		T21	151		T172	5
valid_sources[0x0b]	5661	1			T20	442		T136	1		T151	1
valid_sources[0x0c]	4747	1			T19	13		T20	493		T144	1
valid_sources[0x0d]	4444	1			T20	456		T43	2		T21	45
valid_sources[0x0e]	4797	1			T6	2		T37	1		T20	468
valid_sources[0x0f]	4596	1			T20	471		T21	110		T42	430
valid_sources[0x10]	4597	1			T20	404		T40	5		T12	1
valid_sources[0x11]	4763	1			T37	1		T20	424		T21	79
valid_sources[0x12]	5085	1			T3	4		T20	446		T151	1
valid_sources[0x13]	4986	1			T20	451		T10	1		T136	1
valid_sources[0x14]	5599	1			T20	467		T40	6		T21	195
valid_sources[0x15]	4733	1			T37	2		T20	450		T151	1
valid_sources[0x16]	4733	1			T20	451		T136	1		T21	101
valid_sources[0x17]	4640	1			T37	1		T20	454		T36	4
valid_sources[0x18]	4745	1			T20	453		T21	155		T42	439
valid_sources[0x19]	4495	1			T20	470		T21	124		T42	281
valid_sources[0x1a]	4393	1			T20	437		T21	138		T173	1
valid_sources[0x1b]	4831	1			T37	1		T20	498		T40	1
valid_sources[0x1c]	5305	1			T20	480		T24	1		T21	93
valid_sources[0x1d]	10032	1			T20	469		T21	84		T8	1
valid_sources[0x1e]	4748	1			T37	1		T20	451		T21	92
valid_sources[0x1f]	4637	1			T20	451		T151	2		T21	112
valid_sources[0x20]	4188	1			T37	1		T20	423		T21	135
valid_sources[0x21]	4634	1			T20	499		T10	1		T21	159
valid_sources[0x22]	4367	1			T20	451		T136	1		T151	2
valid_sources[0x23]	4885	1			T20	419		T151	2		T21	146
valid_sources[0x24]	4869	1			T6	1		T20	449		T144	1
valid_sources[0x25]	4557	1			T20	441		T21	209		T42	443
valid_sources[0x26]	4804	1			T20	399		T144	1		T21	165
valid_sources[0x27]	4739	1			T20	483		T21	142		T42	536
valid_sources[0x28]	5324	1			T20	444		T21	146		T42	523
valid_sources[0x29]	4724	1			T20	472		T24	1		T12	1
valid_sources[0x2a]	4334	1			T20	479		T21	68		T42	403
valid_sources[0x2b]	4783	1			T20	479		T21	147		T42	422
valid_sources[0x2c]	4398	1			T37	1		T20	436		T136	4
valid_sources[0x2d]	4466	1			T20	451		T151	1		T21	101
valid_sources[0x2e]	5219	1			T20	465		T21	79		T42	408
valid_sources[0x2f]	5085	1			T37	1		T20	471		T40	3
valid_sources[0x30]	4691	1			T23	2		T20	456		T151	1
valid_sources[0x31]	4623	1			T37	1		T20	444		T36	1
valid_sources[0x32]	4734	1			T20	476		T141	4		T21	85
valid_sources[0x33]	5040	1			T20	476		T10	2		T21	110
valid_sources[0x34]	4692	1			T20	449		T174	10		T21	182
valid_sources[0x35]	4104	1			T20	465		T21	128		T175	2
valid_sources[0x36]	4710	1			T37	2		T20	428		T21	144
valid_sources[0x37]	5540	1			T20	456		T21	133		T42	582
valid_sources[0x38]	4593	1			T37	1		T20	440		T144	2
valid_sources[0x39]	4885	1			T3	3		T37	1		T20	462
valid_sources[0x3a]	4665	1			T37	1		T20	451		T21	95
valid_sources[0x3b]	4933	1			T20	428		T21	119		T42	403
valid_sources[0x3c]	5713	1			T23	1		T20	430		T21	113
valid_sources[0x3d]	4722	1			T3	4		T20	485		T144	6
valid_sources[0x3e]	5275	1			T20	439		T21	115		T42	515
valid_sources[0x3f]	11222	1			T20	457		T40	8		T21	91
valid_sources[0x40]	4418	1			T20	433		T136	1		T21	138
valid_sources[0x41]	4601	1			T20	444		T21	86		T42	400
valid_sources[0x42]	5040	1			T20	437		T12	1		T21	62
valid_sources[0x43]	5174	1			T37	2		T20	464		T21	61
valid_sources[0x44]	4934	1			T20	474		T21	126		T42	359
valid_sources[0x45]	4698	1			T20	467		T10	1		T21	133
valid_sources[0x46]	4723	1			T3	3		T20	470		T10	1
valid_sources[0x47]	5160	1			T20	466		T21	112		T42	609
valid_sources[0x48]	5003	1			T20	457		T21	188		T42	782
valid_sources[0x49]	4659	1			T20	454		T176	2		T21	138
valid_sources[0x4a]	4510	1			T20	528		T21	70		T42	456
valid_sources[0x4b]	4877	1			T20	440		T144	2		T21	189
valid_sources[0x4c]	4916	1			T20	460		T151	2		T21	159
valid_sources[0x4d]	4945	1			T37	1		T20	451		T21	105
valid_sources[0x4e]	4750	1			T20	469		T21	58		T42	567
valid_sources[0x4f]	5041	1			T20	450		T21	154		T47	11
valid_sources[0x50]	5253	1			T20	441		T144	1		T21	173
valid_sources[0x51]	4446	1			T20	413		T144	1		T21	185
valid_sources[0x52]	4762	1			T20	462		T177	2		T144	2
valid_sources[0x53]	4327	1			T20	450		T21	135		T42	308
valid_sources[0x54]	4510	1			T5	2		T20	438		T144	2
valid_sources[0x55]	4384	1			T20	447		T21	118		T178	1
valid_sources[0x56]	4742	1			T20	446		T21	83		T42	486
valid_sources[0x57]	4902	1			T20	438		T21	132		T42	515
valid_sources[0x58]	4619	1			T20	475		T21	104		T42	665
valid_sources[0x59]	4734	1			T37	1		T20	451		T21	141
valid_sources[0x5a]	4509	1			T20	453		T21	116		T17	1
valid_sources[0x5b]	5113	1			T20	478		T12	1		T21	81
valid_sources[0x5c]	5021	1			T6	1		T20	456		T21	80
valid_sources[0x5d]	5581	1			T5	1		T20	476		T21	154
valid_sources[0x5e]	4834	1			T37	2		T20	477		T21	117
valid_sources[0x5f]	4844	1			T20	504		T61	1		T40	6
valid_sources[0x60]	4338	1			T37	2		T20	462		T21	80
valid_sources[0x61]	4510	1			T3	4		T37	1		T20	452
valid_sources[0x62]	4582	1			T20	462		T36	3		T136	1
valid_sources[0x63]	6181	1			T39	1		T37	1		T20	491
valid_sources[0x64]	4840	1			T20	470		T21	150		T42	250
valid_sources[0x65]	4988	1			T37	4		T20	460		T21	167
valid_sources[0x66]	5156	1			T20	491		T21	160		T42	419
valid_sources[0x67]	5137	1			T20	448		T21	130		T42	591
valid_sources[0x68]	5556	1			T37	1		T20	425		T21	249
valid_sources[0x69]	4571	1			T20	435		T24	1		T21	81
valid_sources[0x6a]	4615	1			T20	462		T144	1		T21	120
valid_sources[0x6b]	4575	1			T20	460		T25	2		T21	106
valid_sources[0x6c]	4389	1			T20	428		T21	74		T42	342
valid_sources[0x6d]	4827	1			T20	466		T21	115		T173	2
valid_sources[0x6e]	4564	1			T37	2		T20	480		T21	173
valid_sources[0x6f]	4942	1			T20	488		T21	123		T42	600
valid_sources[0x70]	4782	1			T20	483		T21	137		T42	353
valid_sources[0x71]	4848	1			T37	2		T20	430		T21	95
valid_sources[0x72]	4613	1			T20	454		T21	77		T178	1
valid_sources[0x73]	5523	1			T20	489		T21	219		T42	407
valid_sources[0x74]	5092	1			T20	498		T21	91		T179	3
valid_sources[0x75]	4925	1			T23	1		T20	475		T21	135
valid_sources[0x76]	4781	1			T37	1		T20	471		T21	143
valid_sources[0x77]	5060	1			T20	491		T25	2		T21	126
valid_sources[0x78]	4982	1			T20	415		T11	13		T21	215
valid_sources[0x79]	5023	1			T37	1		T20	487		T136	1
valid_sources[0x7a]	5363	1			T20	463		T21	46		T173	1
valid_sources[0x7b]	4741	1			T20	426		T21	168		T42	490
valid_sources[0x7c]	4674	1			T20	507		T21	84		T42	534
valid_sources[0x7d]	4918	1			T20	442		T41	9		T21	193
valid_sources[0x7e]	5320	1			T20	445		T21	115		T153	1
valid_sources[0x7f]	4716	1			T20	484		T136	1		T21	143
valid_sources[0x80]	4840	1			T39	2		T20	476		T21	175

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

359139

1

T3

3

T5

3

T6

1

values[0x0]

all_enables

biggest_size

214550

1

T3

1

T5

1

T6

2

values[0x1]

all_enables

biggest_size

213826

1

T3

3

T39

1

T19

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	17921	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

333219

1

T1

2

T2

1

T3

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	93321	1			T20	22085		T21	5394		T42	21124
values[0x0]	125856	1			T1	4		T2	1		T3	4
values[0x1]	131963	1			T1	2		T3	3		T7	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	10400	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

340740

1

T1

2

T2

1

T3

7

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1408	1			T20	362		T180	1		T181	3
valid_sources[0x01]	1375	1			T20	325		T49	1		T21	87
valid_sources[0x02]	1341	1			T20	310		T182	1		T21	104
valid_sources[0x03]	1375	1			T20	319		T21	54		T156	1
valid_sources[0x04]	1283	1			T20	320		T24	2		T21	41
valid_sources[0x05]	1318	1			T20	317		T21	108		T42	278
valid_sources[0x06]	1307	1			T20	342		T21	44		T183	1
valid_sources[0x07]	1261	1			T19	1		T20	320		T181	2
valid_sources[0x08]	1384	1			T20	310		T21	48		T184	1
valid_sources[0x09]	1365	1			T20	363		T21	93		T42	340
valid_sources[0x0a]	1424	1			T20	381		T21	108		T173	1
valid_sources[0x0b]	1298	1			T20	343		T21	45		T42	325
valid_sources[0x0c]	1372	1			T20	357		T21	83		T185	1
valid_sources[0x0d]	1359	1			T20	318		T21	73		T42	350
valid_sources[0x0e]	1348	1			T20	333		T21	139		T42	304
valid_sources[0x0f]	1503	1			T20	389		T186	2		T144	2
valid_sources[0x10]	1454	1			T2	1		T20	320		T187	2
valid_sources[0x11]	1358	1			T1	2		T20	349		T188	2
valid_sources[0x12]	1441	1			T20	320		T189	1		T24	1
valid_sources[0x13]	1360	1			T20	309		T21	37		T42	338
valid_sources[0x14]	1327	1			T20	332		T21	70		T42	329
valid_sources[0x15]	1450	1			T20	364		T187	1		T21	55
valid_sources[0x16]	1390	1			T20	364		T21	94		T42	320
valid_sources[0x17]	1381	1			T20	341		T21	51		T42	330
valid_sources[0x18]	1442	1			T20	366		T190	1		T181	5
valid_sources[0x19]	1414	1			T20	326		T141	1		T159	1
valid_sources[0x1a]	1222	1			T20	307		T190	1		T21	22
valid_sources[0x1b]	1305	1			T20	330		T154	1		T21	107
valid_sources[0x1c]	1410	1			T20	384		T137	2		T21	59
valid_sources[0x1d]	1366	1			T4	7		T20	319		T12	1
valid_sources[0x1e]	1393	1			T6	1		T20	332		T21	67
valid_sources[0x1f]	1317	1			T20	349		T190	1		T21	115
valid_sources[0x20]	1421	1			T6	1		T20	327		T191	2
valid_sources[0x21]	1342	1			T20	321		T145	1		T180	1
valid_sources[0x22]	1433	1			T20	333		T11	4		T21	97
valid_sources[0x23]	1437	1			T19	3		T20	328		T12	2
valid_sources[0x24]	1303	1			T20	336		T189	1		T21	101
valid_sources[0x25]	1476	1			T20	318		T192	1		T21	181
valid_sources[0x26]	1346	1			T20	330		T190	1		T180	1
valid_sources[0x27]	1519	1			T6	1		T20	339		T21	107
valid_sources[0x28]	1492	1			T20	367		T71	7		T21	42
valid_sources[0x29]	1500	1			T6	3		T20	369		T21	77
valid_sources[0x2a]	1404	1			T20	312		T27	8		T136	2
valid_sources[0x2b]	1239	1			T20	306		T193	1		T187	1
valid_sources[0x2c]	1374	1			T13	1		T20	366		T21	75
valid_sources[0x2d]	1363	1			T20	334		T144	1		T21	110
valid_sources[0x2e]	1316	1			T20	326		T189	1		T21	70
valid_sources[0x2f]	1428	1			T19	1		T20	375		T188	1
valid_sources[0x30]	1390	1			T3	1		T20	336		T141	1
valid_sources[0x31]	1356	1			T20	352		T145	1		T21	115
valid_sources[0x32]	1350	1			T20	298		T137	1		T21	32
valid_sources[0x33]	1367	1			T20	319		T21	187		T194	1
valid_sources[0x34]	1417	1			T20	343		T152	1		T190	1
valid_sources[0x35]	1384	1			T20	322		T21	158		T135	2
valid_sources[0x36]	1555	1			T20	345		T21	57		T16	2
valid_sources[0x37]	1517	1			T20	329		T191	2		T21	194
valid_sources[0x38]	1289	1			T20	314		T21	51		T42	307
valid_sources[0x39]	1417	1			T20	367		T21	68		T42	331
valid_sources[0x3a]	1440	1			T20	301		T195	3		T196	1
valid_sources[0x3b]	1323	1			T20	357		T21	83		T42	303
valid_sources[0x3c]	1342	1			T20	315		T21	61		T42	323
valid_sources[0x3d]	1258	1			T20	348		T144	1		T21	69
valid_sources[0x3e]	1449	1			T20	349		T21	63		T47	1
valid_sources[0x3f]	1321	1			T20	341		T21	61		T42	306
valid_sources[0x40]	1490	1			T20	310		T61	2		T21	109
valid_sources[0x41]	1419	1			T20	318		T25	1		T21	34
valid_sources[0x42]	1428	1			T20	356		T31	2		T21	114
valid_sources[0x43]	1187	1			T20	315		T187	1		T21	37
valid_sources[0x44]	1341	1			T20	347		T189	1		T21	161
valid_sources[0x45]	1386	1			T20	382		T21	122		T197	1
valid_sources[0x46]	1260	1			T20	387		T48	6		T21	33
valid_sources[0x47]	1304	1			T20	361		T65	1		T21	46
valid_sources[0x48]	1377	1			T20	344		T136	4		T21	105
valid_sources[0x49]	1431	1			T20	338		T189	1		T11	2
valid_sources[0x4a]	1367	1			T20	353		T189	1		T21	69
valid_sources[0x4b]	1331	1			T20	325		T198	10		T21	56
valid_sources[0x4c]	1381	1			T20	333		T31	1		T21	112
valid_sources[0x4d]	1411	1			T20	316		T21	64		T42	325
valid_sources[0x4e]	1361	1			T20	360		T21	86		T42	292
valid_sources[0x4f]	1436	1			T20	338		T21	53		T199	1
valid_sources[0x50]	1437	1			T20	372		T21	161		T199	3
valid_sources[0x51]	1395	1			T20	368		T21	115		T185	1
valid_sources[0x52]	1354	1			T20	293		T200	1		T21	168
valid_sources[0x53]	1484	1			T20	324		T145	1		T144	1
valid_sources[0x54]	1354	1			T20	341		T201	1		T21	67
valid_sources[0x55]	1464	1			T20	349		T21	108		T202	2
valid_sources[0x56]	1355	1			T20	317		T72	13		T189	1
valid_sources[0x57]	1392	1			T20	322		T70	1		T40	2
valid_sources[0x58]	1307	1			T20	310		T21	38		T155	3
valid_sources[0x59]	1386	1			T20	327		T190	1		T154	1
valid_sources[0x5a]	1383	1			T20	313		T203	1		T21	61
valid_sources[0x5b]	1309	1			T20	345		T21	70		T204	2
valid_sources[0x5c]	1258	1			T20	353		T154	2		T21	88
valid_sources[0x5d]	1443	1			T20	312		T141	1		T21	180
valid_sources[0x5e]	1308	1			T20	331		T21	48		T42	354
valid_sources[0x5f]	1376	1			T20	326		T24	2		T21	116
valid_sources[0x60]	1427	1			T20	360		T205	1		T21	62
valid_sources[0x61]	1349	1			T20	335		T206	1		T180	1
valid_sources[0x62]	1310	1			T3	2		T33	1		T20	325
valid_sources[0x63]	1429	1			T20	344		T207	1		T25	3
valid_sources[0x64]	1349	1			T20	354		T186	1		T21	131
valid_sources[0x65]	1361	1			T20	323		T40	1		T208	8
valid_sources[0x66]	1634	1			T20	319		T21	68		T184	1
valid_sources[0x67]	1413	1			T20	360		T21	114		T42	332
valid_sources[0x68]	1337	1			T26	4		T20	335		T21	111
valid_sources[0x69]	1296	1			T20	317		T21	85		T42	356
valid_sources[0x6a]	1337	1			T20	371		T21	29		T173	1
valid_sources[0x6b]	1254	1			T20	314		T21	29		T209	4
valid_sources[0x6c]	1334	1			T57	1		T20	313		T49	1
valid_sources[0x6d]	1613	1			T20	324		T196	1		T21	86
valid_sources[0x6e]	1331	1			T20	354		T189	1		T177	1
valid_sources[0x6f]	1256	1			T20	318		T21	64		T185	1
valid_sources[0x70]	1404	1			T20	368		T40	1		T21	59
valid_sources[0x71]	1347	1			T20	365		T196	1		T21	78
valid_sources[0x72]	1377	1			T20	373		T191	1		T196	1
valid_sources[0x73]	1358	1			T20	320		T31	1		T21	77
valid_sources[0x74]	1332	1			T20	361		T210	1		T196	1
valid_sources[0x75]	1399	1			T20	364		T21	145		T42	314
valid_sources[0x76]	1394	1			T20	310		T21	113		T17	1
valid_sources[0x77]	1392	1			T20	357		T61	1		T136	2
valid_sources[0x78]	1346	1			T20	331		T211	9		T21	49
valid_sources[0x79]	1219	1			T20	291		T21	43		T45	1
valid_sources[0x7a]	1355	1			T20	340		T186	1		T21	44
valid_sources[0x7b]	1530	1			T20	346		T21	126		T42	299
valid_sources[0x7c]	1290	1			T20	321		T21	63		T42	330
valid_sources[0x7d]	1271	1			T20	332		T21	64		T42	316
valid_sources[0x7e]	1340	1			T20	338		T212	1		T21	53
valid_sources[0x7f]	1464	1			T20	354		T21	91		T42	328
valid_sources[0x80]	1337	1			T7	1		T20	328		T21	107

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

85433

1

T20

20839

T21

5131

T42

20013

values[0x0]

all_enables

biggest_size

124141

1

T1

2

T2

1

T3

4

values[0x1]

all_enables

biggest_size

123645

1

T3

3

T7

1

T4

3