SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[rv_dm_mem_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[rv_dm_regs_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 2202120 | 1 | T3 | 25 | T4 | 4 | T5 | 7 | ||||
auto[1] | 613831 | 1 | T37 | 80 | T20 | 158068 | T21 | 37168 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 2815753 | 1 | T3 | 25 | T4 | 4 | T5 | 7 | ||||
values[1] | 18 | 1 | T76 | 1 | T79 | 4 | T160 | 1 | ||||
values[2] | 1 | 1 | T161 | 1 | - | - | - | - | ||||
values[3] | 103 | 1 | T90 | 7 | T76 | 10 | T77 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 2815748 | 1 | T3 | 25 | T4 | 4 | T5 | 7 | ||||
values[1] | 18 | 1 | T77 | 2 | T79 | 2 | T162 | 1 | ||||
values[2] | 2 | 1 | T77 | 1 | T163 | 1 | - | - | ||||
values[3] | 112 | 1 | T90 | 8 | T76 | 9 | T77 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 2815641 | 1 | T3 | 25 | T4 | 4 | T5 | 7 | ||||
auto[TlIntgErrCmd] | 107 | 1 | T90 | 6 | T76 | 9 | T77 | 3 | ||||
auto[TlIntgErrData] | 112 | 1 | T90 | 9 | T76 | 3 | T77 | 5 | ||||
auto[TlIntgErrBoth] | 91 | 1 | T90 | 5 | T76 | 8 | T77 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[0] | 948274 | 0 | T1 | 6 | T2 | 1 | T3 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 948087 | 1 | T1 | 6 | T2 | 1 | T3 | 7 | ||||
values[1] | 19 | 1 | T90 | 2 | T76 | 2 | T77 | 1 | ||||
values[2] | 1 | 1 | T164 | 1 | - | - | - | - | ||||
values[3] | 85 | 1 | T90 | 2 | T76 | 4 | T79 | 9 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 948061 | 1 | T1 | 6 | T2 | 1 | T3 | 7 | ||||
values[1] | 25 | 1 | T90 | 2 | T79 | 2 | T165 | 1 | ||||
values[2] | 11 | 1 | T90 | 2 | T160 | 1 | T166 | 2 | ||||
values[3] | 100 | 1 | T90 | 9 | T76 | 6 | T77 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 947964 | 1 | T1 | 6 | T2 | 1 | T3 | 7 | ||||
auto[TlIntgErrCmd] | 97 | 1 | T90 | 3 | T76 | 13 | T77 | 5 | ||||
auto[TlIntgErrData] | 123 | 1 | T90 | 12 | T76 | 6 | T77 | 4 | ||||
auto[TlIntgErrBoth] | 90 | 1 | T90 | 5 | T76 | 1 | T77 | 1 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |