Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1977621

1

T3

18

T4

4

T5

3

full_word

838330

1

T3

7

T5

4

T6

3

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	2815641	1			T3	25		T4	4		T5	7
auto[TlIntgErrCmd]	107	1			T90	6		T76	9		T77	3
auto[TlIntgErrData]	112	1			T90	9		T76	3		T77	5
auto[TlIntgErrBoth]	91	1			T90	5		T76	8		T77	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

638353

1

T3

4

T5

3

T6

3

auto[1]

2177598

1

T3

21

T4

4

T5

4

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	272942	1			T3	1		T6	2		T39	1
auto[TlIntgErrNone]	partial	auto[1]	1704395	1			T3	17		T4	4		T5	3
auto[TlIntgErrNone]	full_word	auto[0]	365269	1			T3	3		T5	3		T6	1
auto[TlIntgErrNone]	full_word	auto[1]	473035	1			T3	4		T5	1		T6	2
auto[TlIntgErrCmd]	partial	auto[0]	44	1			T76	4		T77	3		T79	1
auto[TlIntgErrCmd]	partial	auto[1]	58	1			T90	5		T76	5		T79	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T90	1		T167	1		T168	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T160	1		T166	1		-	-
auto[TlIntgErrData]	partial	auto[0]	48	1			T90	2		T77	3		T79	4
auto[TlIntgErrData]	partial	auto[1]	50	1			T90	4		T76	2		T77	1
auto[TlIntgErrData]	full_word	auto[0]	9	1			T90	1		T76	1		T79	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T90	2		T77	1		T162	1
auto[TlIntgErrBoth]	partial	auto[0]	34	1			T90	3		T76	2		T79	2
auto[TlIntgErrBoth]	partial	auto[1]	50	1			T90	2		T76	6		T77	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T169	1		T161	3		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T169	1		T167	2		-	-