Module Definition
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Module : rv_dm_regs_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.rv_dm_regs_csr_assert 100.00 100.00



Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.16 100.00 85.71 97.60 100.00 87.50 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : rv_dm_regs_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 169765068 445885 0 0
late_debug_enable_rd_A 169765068 65146 0 0
late_debug_enable_regwen_rd_A 169765068 57403 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 169765068 445885 0 0
T9 0 48196 0 0
T10 199253 0 0 0
T20 596238 116557 0 0
T21 0 27601 0 0
T27 340440 0 0 0
T36 288984 0 0 0
T42 0 109171 0 0
T44 0 122641 0 0
T48 2709 0 0 0
T49 4290 0 0 0
T50 55453 0 0 0
T68 274003 0 0 0
T69 818623 0 0 0
T73 206185 0 0 0
T74 0 506 0 0
T75 0 17 0 0
T76 0 8 0 0
T77 0 2 0 0
T90 0 6 0 0

late_debug_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 169765068 65146 0 0
T9 274979 16293 0 0
T44 706294 41683 0 0
T54 66968 0 0 0
T58 431258 0 0 0
T67 139403 0 0 0
T75 0 24 0 0
T78 0 384 0 0
T84 0 6 0 0
T87 0 29 0 0
T91 0 29 0 0
T101 0 428 0 0
T111 0 441 0 0
T123 0 79 0 0
T124 650468 0 0 0
T125 42805 0 0 0
T126 5249 0 0 0
T127 14858 0 0 0
T128 2634 0 0 0

late_debug_enable_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 169765068 57403 0 0
T9 274979 14636 0 0
T44 706294 35945 0 0
T54 66968 0 0 0
T58 431258 0 0 0
T67 139403 0 0 0
T75 0 19 0 0
T78 0 214 0 0
T84 0 3 0 0
T86 0 967 0 0
T87 0 33 0 0
T91 0 13 0 0
T101 0 508 0 0
T111 0 466 0 0
T124 650468 0 0 0
T125 42805 0 0 0
T126 5249 0 0 0
T127 14858 0 0 0
T128 2634 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%