Line Coverage for Module :
prim_generic_clock_mux2
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Module :
prim_generic_clock_mux2
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Module :
prim_generic_clock_mux2
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
10067327 |
10065915 |
0 |
0 |
selKnown1 |
89549890 |
89548478 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10067327 |
10065915 |
0 |
0 |
T1 |
236 |
234 |
0 |
0 |
T2 |
11370 |
11368 |
0 |
0 |
T3 |
19025 |
19021 |
0 |
0 |
T4 |
15546 |
15542 |
0 |
0 |
T5 |
2868 |
2864 |
0 |
0 |
T6 |
17992 |
17988 |
0 |
0 |
T7 |
1176 |
1172 |
0 |
0 |
T13 |
23682 |
23678 |
0 |
0 |
T14 |
2 |
0 |
0 |
0 |
T19 |
0 |
5 |
0 |
0 |
T20 |
0 |
29 |
0 |
0 |
T23 |
0 |
10 |
0 |
0 |
T26 |
0 |
6 |
0 |
0 |
T27 |
0 |
14 |
0 |
0 |
T29 |
1650 |
1646 |
0 |
0 |
T33 |
284 |
280 |
0 |
0 |
T39 |
2 |
0 |
0 |
0 |
T50 |
0 |
40 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
89549890 |
89548478 |
0 |
0 |
T1 |
2133 |
2131 |
0 |
0 |
T2 |
99906 |
99904 |
0 |
0 |
T3 |
75419 |
75415 |
0 |
0 |
T4 |
39923 |
39919 |
0 |
0 |
T5 |
48093 |
48089 |
0 |
0 |
T6 |
303598 |
303594 |
0 |
0 |
T7 |
7765 |
7761 |
0 |
0 |
T13 |
192725 |
192721 |
0 |
0 |
T14 |
2 |
0 |
0 |
0 |
T19 |
0 |
4 |
0 |
0 |
T20 |
0 |
16 |
0 |
0 |
T23 |
0 |
8 |
0 |
0 |
T26 |
0 |
6 |
0 |
0 |
T27 |
0 |
14 |
0 |
0 |
T29 |
5026 |
5022 |
0 |
0 |
T33 |
3108 |
3104 |
0 |
0 |
T36 |
0 |
4 |
0 |
0 |
T39 |
2 |
0 |
0 |
0 |
T50 |
0 |
40 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
3369345 |
3369102 |
0 |
0 |
selKnown1 |
82852046 |
82851803 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3369345 |
3369102 |
0 |
0 |
T1 |
118 |
117 |
0 |
0 |
T2 |
5685 |
5684 |
0 |
0 |
T3 |
9505 |
9504 |
0 |
0 |
T4 |
7767 |
7766 |
0 |
0 |
T5 |
1433 |
1432 |
0 |
0 |
T6 |
8993 |
8992 |
0 |
0 |
T7 |
586 |
585 |
0 |
0 |
T13 |
11840 |
11839 |
0 |
0 |
T29 |
824 |
823 |
0 |
0 |
T33 |
141 |
140 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
82852046 |
82851803 |
0 |
0 |
T1 |
2015 |
2014 |
0 |
0 |
T2 |
94221 |
94220 |
0 |
0 |
T3 |
65904 |
65903 |
0 |
0 |
T4 |
32146 |
32145 |
0 |
0 |
T5 |
46658 |
46657 |
0 |
0 |
T6 |
294599 |
294598 |
0 |
0 |
T7 |
7177 |
7176 |
0 |
0 |
T13 |
180883 |
180882 |
0 |
0 |
T29 |
4200 |
4199 |
0 |
0 |
T33 |
2965 |
2964 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
699 |
456 |
0 |
0 |
T3 |
7 |
6 |
0 |
0 |
T4 |
5 |
4 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
3 |
2 |
0 |
0 |
T7 |
2 |
1 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
1 |
0 |
0 |
0 |
T19 |
0 |
2 |
0 |
0 |
T20 |
0 |
13 |
0 |
0 |
T23 |
0 |
5 |
0 |
0 |
T26 |
0 |
3 |
0 |
0 |
T27 |
0 |
7 |
0 |
0 |
T29 |
1 |
0 |
0 |
0 |
T33 |
1 |
0 |
0 |
0 |
T39 |
1 |
0 |
0 |
0 |
T50 |
0 |
20 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
657 |
414 |
0 |
0 |
T3 |
5 |
4 |
0 |
0 |
T4 |
5 |
4 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
3 |
2 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
1 |
0 |
0 |
0 |
T19 |
0 |
2 |
0 |
0 |
T20 |
0 |
8 |
0 |
0 |
T23 |
0 |
4 |
0 |
0 |
T26 |
0 |
3 |
0 |
0 |
T27 |
0 |
7 |
0 |
0 |
T29 |
1 |
0 |
0 |
0 |
T33 |
1 |
0 |
0 |
0 |
T36 |
0 |
2 |
0 |
0 |
T39 |
1 |
0 |
0 |
0 |
T50 |
0 |
20 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
6695472 |
6695009 |
0 |
0 |
selKnown1 |
6695472 |
6695009 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
6695472 |
6695009 |
0 |
0 |
T1 |
118 |
117 |
0 |
0 |
T2 |
5685 |
5684 |
0 |
0 |
T3 |
9505 |
9504 |
0 |
0 |
T4 |
7767 |
7766 |
0 |
0 |
T5 |
1433 |
1432 |
0 |
0 |
T6 |
8993 |
8992 |
0 |
0 |
T7 |
586 |
585 |
0 |
0 |
T13 |
11840 |
11839 |
0 |
0 |
T29 |
824 |
823 |
0 |
0 |
T33 |
141 |
140 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
6695472 |
6695009 |
0 |
0 |
T1 |
118 |
117 |
0 |
0 |
T2 |
5685 |
5684 |
0 |
0 |
T3 |
9505 |
9504 |
0 |
0 |
T4 |
7767 |
7766 |
0 |
0 |
T5 |
1433 |
1432 |
0 |
0 |
T6 |
8993 |
8992 |
0 |
0 |
T7 |
586 |
585 |
0 |
0 |
T13 |
11840 |
11839 |
0 |
0 |
T29 |
824 |
823 |
0 |
0 |
T33 |
141 |
140 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
1811 |
1348 |
0 |
0 |
selKnown1 |
1715 |
1252 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1811 |
1348 |
0 |
0 |
T3 |
8 |
7 |
0 |
0 |
T4 |
7 |
6 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
3 |
2 |
0 |
0 |
T7 |
2 |
1 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
1 |
0 |
0 |
0 |
T19 |
0 |
3 |
0 |
0 |
T20 |
0 |
16 |
0 |
0 |
T23 |
0 |
5 |
0 |
0 |
T26 |
0 |
3 |
0 |
0 |
T27 |
0 |
7 |
0 |
0 |
T29 |
1 |
0 |
0 |
0 |
T33 |
1 |
0 |
0 |
0 |
T39 |
1 |
0 |
0 |
0 |
T50 |
0 |
20 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1715 |
1252 |
0 |
0 |
T3 |
5 |
4 |
0 |
0 |
T4 |
5 |
4 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
3 |
2 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
1 |
0 |
0 |
0 |
T19 |
0 |
2 |
0 |
0 |
T20 |
0 |
8 |
0 |
0 |
T23 |
0 |
4 |
0 |
0 |
T26 |
0 |
3 |
0 |
0 |
T27 |
0 |
7 |
0 |
0 |
T29 |
1 |
0 |
0 |
0 |
T33 |
1 |
0 |
0 |
0 |
T36 |
0 |
2 |
0 |
0 |
T39 |
1 |
0 |
0 |
0 |
T50 |
0 |
20 |
0 |
0 |