SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_lc_sync_lc_hw_debug_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prim_lc_sync_lc_dft_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_en_sync_copies | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_pm_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
94.16 | 100.00 | 85.71 | 97.60 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
94.16 | 100.00 | 85.71 | 97.60 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
94.16 | 100.00 | 85.71 | 97.60 | 100.00 | 87.50 | dut |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
94.16 | 100.00 | 85.71 | 97.60 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
70.34 | 86.27 | 76.47 | 57.14 | 81.82 | 50.00 | u_tlul_lc_gate_sba |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
87.14 | 100.00 | 100.00 | 85.71 | 100.00 | 50.00 | u_tlul_lc_gate_rom |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1458 | 1458 | 0 | 0 |
OutputsKnown_A | 497112276 | 496821930 | 0 | 0 |
gen_flops.OutputDelay_A | 248556138 | 248405052 | 0 | 2187 |
gen_no_flops.OutputDelay_A | 248556138 | 248410965 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1458 | 1458 | 0 | 0 |
T1 | 6 | 6 | 0 | 0 |
T2 | 6 | 6 | 0 | 0 |
T3 | 6 | 6 | 0 | 0 |
T4 | 6 | 6 | 0 | 0 |
T5 | 6 | 6 | 0 | 0 |
T6 | 6 | 6 | 0 | 0 |
T7 | 6 | 6 | 0 | 0 |
T13 | 6 | 6 | 0 | 0 |
T29 | 6 | 6 | 0 | 0 |
T33 | 6 | 6 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 497112276 | 496821930 | 0 | 0 |
T1 | 12090 | 11622 | 0 | 0 |
T2 | 565326 | 564984 | 0 | 0 |
T3 | 395424 | 393228 | 0 | 0 |
T4 | 192876 | 190704 | 0 | 0 |
T5 | 279948 | 279516 | 0 | 0 |
T6 | 1767594 | 1766430 | 0 | 0 |
T7 | 43062 | 42762 | 0 | 0 |
T13 | 1085298 | 1084932 | 0 | 0 |
T29 | 25200 | 24822 | 0 | 0 |
T33 | 17790 | 17430 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 248556138 | 248405052 | 0 | 2187 |
T1 | 6045 | 5802 | 0 | 9 |
T2 | 282663 | 282483 | 0 | 9 |
T3 | 197712 | 196569 | 0 | 9 |
T4 | 96438 | 95307 | 0 | 9 |
T5 | 139974 | 139749 | 0 | 9 |
T6 | 883797 | 883188 | 0 | 9 |
T7 | 21531 | 21372 | 0 | 9 |
T13 | 542649 | 542457 | 0 | 9 |
T29 | 12600 | 12402 | 0 | 9 |
T33 | 8895 | 8706 | 0 | 9 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 248556138 | 248410965 | 0 | 0 |
T1 | 6045 | 5811 | 0 | 0 |
T2 | 282663 | 282492 | 0 | 0 |
T3 | 197712 | 196614 | 0 | 0 |
T4 | 96438 | 95352 | 0 | 0 |
T5 | 139974 | 139758 | 0 | 0 |
T6 | 883797 | 883215 | 0 | 0 |
T7 | 21531 | 21381 | 0 | 0 |
T13 | 542649 | 542466 | 0 | 0 |
T29 | 12600 | 12411 | 0 | 0 |
T33 | 8895 | 8715 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 243 | 243 | 0 | 0 |
OutputsKnown_A | 82852046 | 82803655 | 0 | 0 |
gen_flops.OutputDelay_A | 82852046 | 82801684 | 0 | 729 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 243 | 243 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 82852046 | 82803655 | 0 | 0 |
T1 | 2015 | 1937 | 0 | 0 |
T2 | 94221 | 94164 | 0 | 0 |
T3 | 65904 | 65538 | 0 | 0 |
T4 | 32146 | 31784 | 0 | 0 |
T5 | 46658 | 46586 | 0 | 0 |
T6 | 294599 | 294405 | 0 | 0 |
T7 | 7177 | 7127 | 0 | 0 |
T13 | 180883 | 180822 | 0 | 0 |
T29 | 4200 | 4137 | 0 | 0 |
T33 | 2965 | 2905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 82852046 | 82801684 | 0 | 729 |
T1 | 2015 | 1934 | 0 | 3 |
T2 | 94221 | 94161 | 0 | 3 |
T3 | 65904 | 65523 | 0 | 3 |
T4 | 32146 | 31769 | 0 | 3 |
T5 | 46658 | 46583 | 0 | 3 |
T6 | 294599 | 294396 | 0 | 3 |
T7 | 7177 | 7124 | 0 | 3 |
T13 | 180883 | 180819 | 0 | 3 |
T29 | 4200 | 4134 | 0 | 3 |
T33 | 2965 | 2902 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 243 | 243 | 0 | 0 |
OutputsKnown_A | 82852046 | 82803655 | 0 | 0 |
gen_flops.OutputDelay_A | 82852046 | 82801684 | 0 | 729 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 243 | 243 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 82852046 | 82803655 | 0 | 0 |
T1 | 2015 | 1937 | 0 | 0 |
T2 | 94221 | 94164 | 0 | 0 |
T3 | 65904 | 65538 | 0 | 0 |
T4 | 32146 | 31784 | 0 | 0 |
T5 | 46658 | 46586 | 0 | 0 |
T6 | 294599 | 294405 | 0 | 0 |
T7 | 7177 | 7127 | 0 | 0 |
T13 | 180883 | 180822 | 0 | 0 |
T29 | 4200 | 4137 | 0 | 0 |
T33 | 2965 | 2905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 82852046 | 82801684 | 0 | 729 |
T1 | 2015 | 1934 | 0 | 3 |
T2 | 94221 | 94161 | 0 | 3 |
T3 | 65904 | 65523 | 0 | 3 |
T4 | 32146 | 31769 | 0 | 3 |
T5 | 46658 | 46583 | 0 | 3 |
T6 | 294599 | 294396 | 0 | 3 |
T7 | 7177 | 7124 | 0 | 3 |
T13 | 180883 | 180819 | 0 | 3 |
T29 | 4200 | 4134 | 0 | 3 |
T33 | 2965 | 2902 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 243 | 243 | 0 | 0 |
OutputsKnown_A | 82852046 | 82803655 | 0 | 0 |
gen_no_flops.OutputDelay_A | 82852046 | 82803655 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 243 | 243 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 82852046 | 82803655 | 0 | 0 |
T1 | 2015 | 1937 | 0 | 0 |
T2 | 94221 | 94164 | 0 | 0 |
T3 | 65904 | 65538 | 0 | 0 |
T4 | 32146 | 31784 | 0 | 0 |
T5 | 46658 | 46586 | 0 | 0 |
T6 | 294599 | 294405 | 0 | 0 |
T7 | 7177 | 7127 | 0 | 0 |
T13 | 180883 | 180822 | 0 | 0 |
T29 | 4200 | 4137 | 0 | 0 |
T33 | 2965 | 2905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 82852046 | 82803655 | 0 | 0 |
T1 | 2015 | 1937 | 0 | 0 |
T2 | 94221 | 94164 | 0 | 0 |
T3 | 65904 | 65538 | 0 | 0 |
T4 | 32146 | 31784 | 0 | 0 |
T5 | 46658 | 46586 | 0 | 0 |
T6 | 294599 | 294405 | 0 | 0 |
T7 | 7177 | 7127 | 0 | 0 |
T13 | 180883 | 180822 | 0 | 0 |
T29 | 4200 | 4137 | 0 | 0 |
T33 | 2965 | 2905 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 243 | 243 | 0 | 0 |
OutputsKnown_A | 82852046 | 82803655 | 0 | 0 |
gen_flops.OutputDelay_A | 82852046 | 82801684 | 0 | 729 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 243 | 243 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 82852046 | 82803655 | 0 | 0 |
T1 | 2015 | 1937 | 0 | 0 |
T2 | 94221 | 94164 | 0 | 0 |
T3 | 65904 | 65538 | 0 | 0 |
T4 | 32146 | 31784 | 0 | 0 |
T5 | 46658 | 46586 | 0 | 0 |
T6 | 294599 | 294405 | 0 | 0 |
T7 | 7177 | 7127 | 0 | 0 |
T13 | 180883 | 180822 | 0 | 0 |
T29 | 4200 | 4137 | 0 | 0 |
T33 | 2965 | 2905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 82852046 | 82801684 | 0 | 729 |
T1 | 2015 | 1934 | 0 | 3 |
T2 | 94221 | 94161 | 0 | 3 |
T3 | 65904 | 65523 | 0 | 3 |
T4 | 32146 | 31769 | 0 | 3 |
T5 | 46658 | 46583 | 0 | 3 |
T6 | 294599 | 294396 | 0 | 3 |
T7 | 7177 | 7124 | 0 | 3 |
T13 | 180883 | 180819 | 0 | 3 |
T29 | 4200 | 4134 | 0 | 3 |
T33 | 2965 | 2902 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 243 | 243 | 0 | 0 |
OutputsKnown_A | 82852046 | 82803655 | 0 | 0 |
gen_no_flops.OutputDelay_A | 82852046 | 82803655 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 243 | 243 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 82852046 | 82803655 | 0 | 0 |
T1 | 2015 | 1937 | 0 | 0 |
T2 | 94221 | 94164 | 0 | 0 |
T3 | 65904 | 65538 | 0 | 0 |
T4 | 32146 | 31784 | 0 | 0 |
T5 | 46658 | 46586 | 0 | 0 |
T6 | 294599 | 294405 | 0 | 0 |
T7 | 7177 | 7127 | 0 | 0 |
T13 | 180883 | 180822 | 0 | 0 |
T29 | 4200 | 4137 | 0 | 0 |
T33 | 2965 | 2905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 82852046 | 82803655 | 0 | 0 |
T1 | 2015 | 1937 | 0 | 0 |
T2 | 94221 | 94164 | 0 | 0 |
T3 | 65904 | 65538 | 0 | 0 |
T4 | 32146 | 31784 | 0 | 0 |
T5 | 46658 | 46586 | 0 | 0 |
T6 | 294599 | 294405 | 0 | 0 |
T7 | 7177 | 7127 | 0 | 0 |
T13 | 180883 | 180822 | 0 | 0 |
T29 | 4200 | 4137 | 0 | 0 |
T33 | 2965 | 2905 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 243 | 243 | 0 | 0 |
OutputsKnown_A | 82852046 | 82803655 | 0 | 0 |
gen_no_flops.OutputDelay_A | 82852046 | 82803655 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 243 | 243 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 82852046 | 82803655 | 0 | 0 |
T1 | 2015 | 1937 | 0 | 0 |
T2 | 94221 | 94164 | 0 | 0 |
T3 | 65904 | 65538 | 0 | 0 |
T4 | 32146 | 31784 | 0 | 0 |
T5 | 46658 | 46586 | 0 | 0 |
T6 | 294599 | 294405 | 0 | 0 |
T7 | 7177 | 7127 | 0 | 0 |
T13 | 180883 | 180822 | 0 | 0 |
T29 | 4200 | 4137 | 0 | 0 |
T33 | 2965 | 2905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 82852046 | 82803655 | 0 | 0 |
T1 | 2015 | 1937 | 0 | 0 |
T2 | 94221 | 94164 | 0 | 0 |
T3 | 65904 | 65538 | 0 | 0 |
T4 | 32146 | 31784 | 0 | 0 |
T5 | 46658 | 46586 | 0 | 0 |
T6 | 294599 | 294405 | 0 | 0 |
T7 | 7177 | 7127 | 0 | 0 |
T13 | 180883 | 180822 | 0 | 0 |
T29 | 4200 | 4137 | 0 | 0 |
T33 | 2965 | 2905 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |