Line Coverage for Module :
prim_sync_reqack
| Line No. | Total | Covered | Percent |
TOTAL | | 27 | 27 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
ALWAYS | 75 | 10 | 10 | 100.00 |
ALWAYS | 117 | 3 | 3 | 100.00 |
ALWAYS | 126 | 11 | 11 | 100.00 |
ALWAYS | 169 | 3 | 3 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
75 |
1 |
1 |
76 |
1 |
1 |
77 |
1 |
1 |
79 |
1 |
1 |
83 |
1 |
1 |
84 |
1 |
1 |
|
|
|
MISSING_ELSE |
88 |
1 |
1 |
90 |
1 |
1 |
93 |
1 |
1 |
94 |
1 |
1 |
|
|
|
MISSING_ELSE |
117 |
1 |
1 |
118 |
1 |
1 |
120 |
1 |
1 |
126 |
1 |
1 |
127 |
1 |
1 |
128 |
1 |
1 |
130 |
1 |
1 |
132 |
1 |
1 |
134 |
1 |
1 |
137 |
1 |
1 |
138 |
1 |
1 |
|
|
|
MISSING_ELSE |
|
|
|
MISSING_ELSE |
143 |
1 |
1 |
145 |
1 |
1 |
146 |
1 |
1 |
|
|
|
MISSING_ELSE |
169 |
1 |
1 |
170 |
1 |
1 |
172 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Module :
prim_sync_reqack
| Total | Covered | Percent |
Conditions | 6 | 4 | 66.67 |
Logical | 6 | 4 | 66.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 83
EXPRESSION (((!gen_rz_hs_protocol.src_ack)) && src_req_i)
---------------1--------------- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 93
EXPRESSION (((!src_req_i)) || gen_rz_hs_protocol.src_ack)
-------1------ -------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
Branch Coverage for Module :
prim_sync_reqack
| Line No. | Total | Covered | Percent |
Branches |
|
13 |
13 |
100.00 |
CASE |
79 |
4 |
4 |
100.00 |
IF |
117 |
2 |
2 |
100.00 |
CASE |
130 |
5 |
5 |
100.00 |
IF |
169 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 79 case (gen_rz_hs_protocol.src_fsm_q)
-2-: 83 if (((!gen_rz_hs_protocol.src_ack) && src_req_i))
-3-: 93 if (((!src_req_i) || gen_rz_hs_protocol.src_ack))
Branches:
-1- | -2- | -3- | Status | Tests |
LoSt |
1 |
- |
Covered |
T1,T2,T3 |
LoSt |
0 |
- |
Covered |
T1,T2,T3 |
HiSt |
- |
1 |
Covered |
T1,T2,T3 |
HiSt |
- |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 117 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 130 case (gen_rz_hs_protocol.dst_fsm_q)
-2-: 132 if (gen_rz_hs_protocol.dst_req)
-3-: 137 if (dst_ack_i)
-4-: 145 if ((!gen_rz_hs_protocol.dst_req))
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
LoSt |
1 |
1 |
- |
Covered |
T1,T2,T3 |
LoSt |
1 |
0 |
- |
Covered |
T1,T2,T3 |
LoSt |
0 |
- |
- |
Covered |
T1,T2,T3 |
HiSt |
- |
- |
1 |
Covered |
T1,T2,T3 |
HiSt |
- |
- |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 169 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_sync_reqack
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
176460540 |
113540 |
0 |
0 |
T1 |
2133 |
2 |
0 |
0 |
T2 |
99906 |
102 |
0 |
0 |
T3 |
75409 |
168 |
0 |
0 |
T4 |
39913 |
124 |
0 |
0 |
T5 |
48091 |
24 |
0 |
0 |
T6 |
303592 |
140 |
0 |
0 |
T7 |
7763 |
6 |
0 |
0 |
T13 |
192723 |
216 |
0 |
0 |
T29 |
5024 |
14 |
0 |
0 |
T33 |
3106 |
2 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
176460540 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack
| Line No. | Total | Covered | Percent |
TOTAL | | 27 | 27 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
ALWAYS | 75 | 10 | 10 | 100.00 |
ALWAYS | 117 | 3 | 3 | 100.00 |
ALWAYS | 126 | 11 | 11 | 100.00 |
ALWAYS | 169 | 3 | 3 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
75 |
1 |
1 |
76 |
1 |
1 |
77 |
1 |
1 |
79 |
1 |
1 |
83 |
1 |
1 |
84 |
1 |
1 |
|
|
|
MISSING_ELSE |
88 |
1 |
1 |
90 |
1 |
1 |
93 |
1 |
1 |
94 |
1 |
1 |
|
|
|
MISSING_ELSE |
117 |
1 |
1 |
118 |
1 |
1 |
120 |
1 |
1 |
126 |
1 |
1 |
127 |
1 |
1 |
128 |
1 |
1 |
130 |
1 |
1 |
132 |
1 |
1 |
134 |
1 |
1 |
137 |
1 |
1 |
138 |
1 |
1 |
|
|
|
MISSING_ELSE |
|
|
|
MISSING_ELSE |
143 |
1 |
1 |
145 |
1 |
1 |
146 |
1 |
1 |
|
|
|
MISSING_ELSE |
169 |
1 |
1 |
170 |
1 |
1 |
172 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack
| Total | Covered | Percent |
Conditions | 6 | 4 | 66.67 |
Logical | 6 | 4 | 66.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 83
EXPRESSION (((!gen_rz_hs_protocol.src_ack)) && src_req_i)
---------------1--------------- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 93
EXPRESSION (((!src_req_i)) || gen_rz_hs_protocol.src_ack)
-------1------ -------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
Branch Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack
| Line No. | Total | Covered | Percent |
Branches |
|
13 |
13 |
100.00 |
CASE |
79 |
4 |
4 |
100.00 |
IF |
117 |
2 |
2 |
100.00 |
CASE |
130 |
5 |
5 |
100.00 |
IF |
169 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 79 case (gen_rz_hs_protocol.src_fsm_q)
-2-: 83 if (((!gen_rz_hs_protocol.src_ack) && src_req_i))
-3-: 93 if (((!src_req_i) || gen_rz_hs_protocol.src_ack))
Branches:
-1- | -2- | -3- | Status | Tests |
LoSt |
1 |
- |
Covered |
T1,T2,T3 |
LoSt |
0 |
- |
Covered |
T1,T2,T3 |
HiSt |
- |
1 |
Covered |
T1,T2,T3 |
HiSt |
- |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 117 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 130 case (gen_rz_hs_protocol.dst_fsm_q)
-2-: 132 if (gen_rz_hs_protocol.dst_req)
-3-: 137 if (dst_ack_i)
-4-: 145 if ((!gen_rz_hs_protocol.dst_req))
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
LoSt |
1 |
1 |
- |
Covered |
T1,T2,T3 |
LoSt |
1 |
0 |
- |
Covered |
T1,T2,T3 |
LoSt |
0 |
- |
- |
Covered |
T1,T2,T3 |
HiSt |
- |
- |
1 |
Covered |
T1,T2,T3 |
HiSt |
- |
- |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 169 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
169765068 |
56770 |
0 |
0 |
T1 |
2015 |
1 |
0 |
0 |
T2 |
94221 |
51 |
0 |
0 |
T3 |
65904 |
84 |
0 |
0 |
T4 |
32146 |
62 |
0 |
0 |
T5 |
46658 |
12 |
0 |
0 |
T6 |
294599 |
70 |
0 |
0 |
T7 |
7177 |
3 |
0 |
0 |
T13 |
180883 |
108 |
0 |
0 |
T29 |
4200 |
7 |
0 |
0 |
T33 |
2965 |
1 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
6695472 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack
| Line No. | Total | Covered | Percent |
TOTAL | | 27 | 27 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
ALWAYS | 75 | 10 | 10 | 100.00 |
ALWAYS | 117 | 3 | 3 | 100.00 |
ALWAYS | 126 | 11 | 11 | 100.00 |
ALWAYS | 169 | 3 | 3 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
75 |
1 |
1 |
76 |
1 |
1 |
77 |
1 |
1 |
79 |
1 |
1 |
83 |
1 |
1 |
84 |
1 |
1 |
|
|
|
MISSING_ELSE |
88 |
1 |
1 |
90 |
1 |
1 |
93 |
1 |
1 |
94 |
1 |
1 |
|
|
|
MISSING_ELSE |
117 |
1 |
1 |
118 |
1 |
1 |
120 |
1 |
1 |
126 |
1 |
1 |
127 |
1 |
1 |
128 |
1 |
1 |
130 |
1 |
1 |
132 |
1 |
1 |
134 |
1 |
1 |
137 |
1 |
1 |
138 |
1 |
1 |
|
|
|
==> MISSING_ELSE |
|
|
|
MISSING_ELSE |
143 |
1 |
1 |
145 |
1 |
1 |
146 |
1 |
1 |
|
|
|
MISSING_ELSE |
169 |
1 |
1 |
170 |
1 |
1 |
172 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack
| Total | Covered | Percent |
Conditions | 6 | 4 | 66.67 |
Logical | 6 | 4 | 66.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 83
EXPRESSION (((!gen_rz_hs_protocol.src_ack)) && src_req_i)
---------------1--------------- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 93
EXPRESSION (((!src_req_i)) || gen_rz_hs_protocol.src_ack)
-------1------ -------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
Branch Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
CASE |
79 |
4 |
4 |
100.00 |
IF |
117 |
2 |
2 |
100.00 |
CASE |
130 |
4 |
4 |
100.00 |
IF |
169 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 79 case (gen_rz_hs_protocol.src_fsm_q)
-2-: 83 if (((!gen_rz_hs_protocol.src_ack) && src_req_i))
-3-: 93 if (((!src_req_i) || gen_rz_hs_protocol.src_ack))
Branches:
-1- | -2- | -3- | Status | Tests |
LoSt |
1 |
- |
Covered |
T1,T2,T3 |
LoSt |
0 |
- |
Covered |
T1,T2,T3 |
HiSt |
- |
1 |
Covered |
T1,T2,T3 |
HiSt |
- |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 117 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 130 case (gen_rz_hs_protocol.dst_fsm_q)
-2-: 132 if (gen_rz_hs_protocol.dst_req)
-3-: 137 if (dst_ack_i)
-4-: 145 if ((!gen_rz_hs_protocol.dst_req))
Branches:
-1- | -2- | -3- | -4- | Status | Tests | Exclude Annotation |
LoSt |
1 |
1 |
- |
Covered |
T1,T2,T3 |
|
LoSt |
1 |
0 |
- |
Excluded |
|
VC_COV_UNR |
LoSt |
0 |
- |
- |
Covered |
T1,T2,T3 |
|
HiSt |
- |
- |
1 |
Covered |
T1,T2,T3 |
|
HiSt |
- |
- |
0 |
Covered |
T1,T2,T3 |
|
LineNo. Expression
-1-: 169 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
6695472 |
56770 |
0 |
0 |
T1 |
118 |
1 |
0 |
0 |
T2 |
5685 |
51 |
0 |
0 |
T3 |
9505 |
84 |
0 |
0 |
T4 |
7767 |
62 |
0 |
0 |
T5 |
1433 |
12 |
0 |
0 |
T6 |
8993 |
70 |
0 |
0 |
T7 |
586 |
3 |
0 |
0 |
T13 |
11840 |
108 |
0 |
0 |
T29 |
824 |
7 |
0 |
0 |
T33 |
141 |
1 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
169765068 |
0 |
0 |
0 |