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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
84.91 96.32 87.13 92.10 73.75 90.44 98.42 56.19


Total test records in report: 463
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T305 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.1451474914 Aug 11 05:35:09 PM PDT 24 Aug 11 05:36:49 PM PDT 24 120954425862 ps
T71 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.1929631820 Aug 11 05:35:26 PM PDT 24 Aug 11 05:35:30 PM PDT 24 286154484 ps
T52 /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.3958851069 Aug 11 05:35:18 PM PDT 24 Aug 11 05:35:39 PM PDT 24 24410805480 ps
T105 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.625449076 Aug 11 05:35:25 PM PDT 24 Aug 11 05:35:31 PM PDT 24 350581681 ps
T306 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.4220338704 Aug 11 05:35:08 PM PDT 24 Aug 11 05:35:11 PM PDT 24 246174738 ps
T53 /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.1350225284 Aug 11 05:35:14 PM PDT 24 Aug 11 05:36:54 PM PDT 24 33472571693 ps
T75 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.3013984030 Aug 11 05:35:28 PM PDT 24 Aug 11 05:35:36 PM PDT 24 644649548 ps
T55 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.908908945 Aug 11 05:35:31 PM PDT 24 Aug 11 05:35:32 PM PDT 24 539817242 ps
T56 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.1787648157 Aug 11 05:35:04 PM PDT 24 Aug 11 05:35:05 PM PDT 24 215353197 ps
T76 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.2309372314 Aug 11 05:35:06 PM PDT 24 Aug 11 05:35:08 PM PDT 24 100479898 ps
T307 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2956240760 Aug 11 05:35:30 PM PDT 24 Aug 11 05:35:31 PM PDT 24 169451813 ps
T308 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.869859311 Aug 11 05:35:03 PM PDT 24 Aug 11 05:37:00 PM PDT 24 70881232423 ps
T309 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1185036207 Aug 11 05:35:07 PM PDT 24 Aug 11 05:35:08 PM PDT 24 400254186 ps
T77 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.1637858027 Aug 11 05:35:14 PM PDT 24 Aug 11 05:35:16 PM PDT 24 175018349 ps
T310 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.3272875822 Aug 11 05:35:16 PM PDT 24 Aug 11 05:35:18 PM PDT 24 973884101 ps
T311 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.4034142936 Aug 11 05:35:25 PM PDT 24 Aug 11 05:35:28 PM PDT 24 5789033240 ps
T110 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.976536763 Aug 11 05:34:59 PM PDT 24 Aug 11 05:35:07 PM PDT 24 1045301293 ps
T78 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.86417171 Aug 11 05:35:06 PM PDT 24 Aug 11 05:36:04 PM PDT 24 6385434630 ps
T88 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.2768711159 Aug 11 05:35:08 PM PDT 24 Aug 11 05:36:28 PM PDT 24 8346948793 ps
T106 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.2886642314 Aug 11 05:35:36 PM PDT 24 Aug 11 05:35:38 PM PDT 24 387985781 ps
T159 /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.3654620219 Aug 11 05:35:05 PM PDT 24 Aug 11 05:36:32 PM PDT 24 52389395298 ps
T312 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.1439719408 Aug 11 05:35:30 PM PDT 24 Aug 11 05:35:36 PM PDT 24 2403078235 ps
T313 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.2552767441 Aug 11 05:35:05 PM PDT 24 Aug 11 05:35:06 PM PDT 24 135916111 ps
T314 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.2808762834 Aug 11 05:35:01 PM PDT 24 Aug 11 05:35:05 PM PDT 24 314175759 ps
T160 /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.2192234905 Aug 11 05:35:19 PM PDT 24 Aug 11 05:35:54 PM PDT 24 32581195822 ps
T107 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.761656956 Aug 11 05:35:27 PM PDT 24 Aug 11 05:35:56 PM PDT 24 5218447855 ps
T315 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.1426260293 Aug 11 05:34:57 PM PDT 24 Aug 11 05:34:59 PM PDT 24 328163624 ps
T316 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.2837696734 Aug 11 05:35:20 PM PDT 24 Aug 11 05:35:24 PM PDT 24 357742424 ps
T108 /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.302844461 Aug 11 05:35:07 PM PDT 24 Aug 11 05:35:09 PM PDT 24 120251746 ps
T317 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.702911668 Aug 11 05:35:26 PM PDT 24 Aug 11 05:35:27 PM PDT 24 205230788 ps
T109 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.4115214777 Aug 11 05:35:34 PM PDT 24 Aug 11 05:35:39 PM PDT 24 611814048 ps
T318 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.4106889170 Aug 11 05:35:21 PM PDT 24 Aug 11 05:35:32 PM PDT 24 6233861005 ps
T319 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.492051560 Aug 11 05:34:57 PM PDT 24 Aug 11 05:34:58 PM PDT 24 56641273 ps
T320 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.752584720 Aug 11 05:35:35 PM PDT 24 Aug 11 05:35:47 PM PDT 24 8015320559 ps
T321 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2705338702 Aug 11 05:35:29 PM PDT 24 Aug 11 05:35:30 PM PDT 24 230017830 ps
T322 /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.1405677917 Aug 11 05:35:36 PM PDT 24 Aug 11 05:35:38 PM PDT 24 118933447 ps
T79 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1156173188 Aug 11 05:35:18 PM PDT 24 Aug 11 05:35:20 PM PDT 24 47307261 ps
T80 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2393643872 Aug 11 05:35:01 PM PDT 24 Aug 11 05:35:05 PM PDT 24 260764160 ps
T81 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.2345567653 Aug 11 05:35:11 PM PDT 24 Aug 11 05:35:13 PM PDT 24 82892783 ps
T323 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.313978983 Aug 11 05:35:21 PM PDT 24 Aug 11 05:35:27 PM PDT 24 237962816 ps
T82 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.1130552125 Aug 11 05:35:40 PM PDT 24 Aug 11 05:35:42 PM PDT 24 644850998 ps
T83 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.928317560 Aug 11 05:34:59 PM PDT 24 Aug 11 05:35:06 PM PDT 24 531413856 ps
T324 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.2773695594 Aug 11 05:34:54 PM PDT 24 Aug 11 05:34:55 PM PDT 24 296202850 ps
T325 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.593952162 Aug 11 05:35:13 PM PDT 24 Aug 11 05:35:35 PM PDT 24 10156929544 ps
T326 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.3615629818 Aug 11 05:34:57 PM PDT 24 Aug 11 05:35:26 PM PDT 24 17947645564 ps
T327 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.1706998869 Aug 11 05:34:58 PM PDT 24 Aug 11 05:34:59 PM PDT 24 152462798 ps
T89 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.829267374 Aug 11 05:35:29 PM PDT 24 Aug 11 05:35:31 PM PDT 24 100994336 ps
T328 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.63320525 Aug 11 05:35:13 PM PDT 24 Aug 11 05:35:17 PM PDT 24 406539149 ps
T111 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1981672073 Aug 11 05:35:25 PM PDT 24 Aug 11 05:35:34 PM PDT 24 669584935 ps
T148 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.3029746001 Aug 11 05:35:39 PM PDT 24 Aug 11 05:35:57 PM PDT 24 1704493148 ps
T90 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.1336088860 Aug 11 05:35:19 PM PDT 24 Aug 11 05:35:21 PM PDT 24 221967576 ps
T91 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.4184849040 Aug 11 05:35:05 PM PDT 24 Aug 11 05:35:34 PM PDT 24 1442145730 ps
T329 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.3730134076 Aug 11 05:35:07 PM PDT 24 Aug 11 05:35:09 PM PDT 24 805021219 ps
T152 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.3389445079 Aug 11 05:35:21 PM PDT 24 Aug 11 05:35:38 PM PDT 24 2362319676 ps
T330 /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.4221686949 Aug 11 05:35:19 PM PDT 24 Aug 11 05:37:58 PM PDT 24 84965042861 ps
T331 /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.2924259923 Aug 11 05:35:06 PM PDT 24 Aug 11 05:37:27 PM PDT 24 43395459917 ps
T332 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.1880830824 Aug 11 05:35:40 PM PDT 24 Aug 11 05:35:45 PM PDT 24 1521871719 ps
T92 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.1898107454 Aug 11 05:35:12 PM PDT 24 Aug 11 05:36:25 PM PDT 24 6482501934 ps
T333 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.2855220888 Aug 11 05:35:35 PM PDT 24 Aug 11 05:35:38 PM PDT 24 194871237 ps
T149 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.2789813219 Aug 11 05:35:00 PM PDT 24 Aug 11 05:35:09 PM PDT 24 2018720557 ps
T334 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3218993614 Aug 11 05:34:57 PM PDT 24 Aug 11 05:34:58 PM PDT 24 605378411 ps
T93 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.2732149681 Aug 11 05:35:12 PM PDT 24 Aug 11 05:35:13 PM PDT 24 216090687 ps
T94 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3293149679 Aug 11 05:34:56 PM PDT 24 Aug 11 05:34:58 PM PDT 24 194807141 ps
T335 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.3201336775 Aug 11 05:34:57 PM PDT 24 Aug 11 05:34:58 PM PDT 24 163646430 ps
T336 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.416047575 Aug 11 05:35:31 PM PDT 24 Aug 11 05:35:44 PM PDT 24 10306577269 ps
T337 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.2933387113 Aug 11 05:35:33 PM PDT 24 Aug 11 05:36:05 PM PDT 24 28673419254 ps
T155 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3207400186 Aug 11 05:35:28 PM PDT 24 Aug 11 05:35:44 PM PDT 24 2936087241 ps
T95 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.1963564757 Aug 11 05:35:27 PM PDT 24 Aug 11 05:35:29 PM PDT 24 205690809 ps
T338 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.3466469611 Aug 11 05:35:25 PM PDT 24 Aug 11 05:35:26 PM PDT 24 63197468 ps
T339 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3314618328 Aug 11 05:34:55 PM PDT 24 Aug 11 05:34:59 PM PDT 24 369354294 ps
T340 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.2104045600 Aug 11 05:35:38 PM PDT 24 Aug 11 05:35:43 PM PDT 24 419735801 ps
T341 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2427182724 Aug 11 05:35:12 PM PDT 24 Aug 11 05:39:50 PM PDT 24 177835881115 ps
T96 /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.3556869247 Aug 11 05:35:25 PM PDT 24 Aug 11 05:35:28 PM PDT 24 334918552 ps
T97 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.2841381561 Aug 11 05:35:08 PM PDT 24 Aug 11 05:35:12 PM PDT 24 260314162 ps
T85 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.3191728041 Aug 11 05:35:05 PM PDT 24 Aug 11 05:35:15 PM PDT 24 15035947001 ps
T342 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.478568674 Aug 11 05:35:20 PM PDT 24 Aug 11 05:35:29 PM PDT 24 14205995355 ps
T343 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.2575285860 Aug 11 05:34:57 PM PDT 24 Aug 11 05:35:00 PM PDT 24 3025130147 ps
T344 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.414668342 Aug 11 05:35:08 PM PDT 24 Aug 11 05:35:10 PM PDT 24 258878985 ps
T156 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.1746158030 Aug 11 05:35:32 PM PDT 24 Aug 11 05:35:48 PM PDT 24 1820099208 ps
T345 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.1617665914 Aug 11 05:35:01 PM PDT 24 Aug 11 05:35:02 PM PDT 24 60279844 ps
T346 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.4002260265 Aug 11 05:35:26 PM PDT 24 Aug 11 05:35:27 PM PDT 24 209496214 ps
T98 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.2589121114 Aug 11 05:35:06 PM PDT 24 Aug 11 05:35:08 PM PDT 24 220947201 ps
T347 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.1629276547 Aug 11 05:35:35 PM PDT 24 Aug 11 05:35:36 PM PDT 24 178628423 ps
T348 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.421780522 Aug 11 05:35:11 PM PDT 24 Aug 11 05:35:27 PM PDT 24 21798877847 ps
T349 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3827405534 Aug 11 05:35:00 PM PDT 24 Aug 11 05:35:43 PM PDT 24 17135063472 ps
T350 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.2120198022 Aug 11 05:34:59 PM PDT 24 Aug 11 05:35:02 PM PDT 24 181970727 ps
T351 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.425837444 Aug 11 05:35:11 PM PDT 24 Aug 11 05:35:13 PM PDT 24 229035074 ps
T153 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.1433153115 Aug 11 05:35:05 PM PDT 24 Aug 11 05:35:28 PM PDT 24 2125061830 ps
T352 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2397556692 Aug 11 05:35:07 PM PDT 24 Aug 11 05:35:08 PM PDT 24 258682838 ps
T353 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.2645804754 Aug 11 05:35:06 PM PDT 24 Aug 11 05:35:08 PM PDT 24 427138046 ps
T354 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.4141510826 Aug 11 05:35:31 PM PDT 24 Aug 11 05:36:26 PM PDT 24 33250060240 ps
T355 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.4241732416 Aug 11 05:35:09 PM PDT 24 Aug 11 05:35:13 PM PDT 24 3973711719 ps
T356 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.2766247712 Aug 11 05:35:38 PM PDT 24 Aug 11 05:35:50 PM PDT 24 10754873195 ps
T357 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.152395259 Aug 11 05:35:06 PM PDT 24 Aug 11 05:35:07 PM PDT 24 158207990 ps
T99 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.347333771 Aug 11 05:34:59 PM PDT 24 Aug 11 05:36:13 PM PDT 24 3509588780 ps
T358 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.3544365994 Aug 11 05:35:24 PM PDT 24 Aug 11 05:35:25 PM PDT 24 322716703 ps
T359 /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.2301209153 Aug 11 05:35:33 PM PDT 24 Aug 11 05:35:36 PM PDT 24 419897453 ps
T360 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.3273224107 Aug 11 05:35:12 PM PDT 24 Aug 11 05:35:13 PM PDT 24 124129984 ps
T361 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.3029019610 Aug 11 05:35:33 PM PDT 24 Aug 11 05:35:35 PM PDT 24 317204607 ps
T362 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.4283636813 Aug 11 05:35:32 PM PDT 24 Aug 11 05:35:35 PM PDT 24 220643437 ps
T363 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.104197971 Aug 11 05:34:59 PM PDT 24 Aug 11 05:35:00 PM PDT 24 36322886 ps
T364 /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.3370537644 Aug 11 05:35:19 PM PDT 24 Aug 11 05:35:23 PM PDT 24 256058774 ps
T86 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.1067854029 Aug 11 05:35:06 PM PDT 24 Aug 11 05:35:19 PM PDT 24 12833098197 ps
T365 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.551626562 Aug 11 05:35:15 PM PDT 24 Aug 11 05:35:19 PM PDT 24 80274298 ps
T150 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.2418588256 Aug 11 05:35:32 PM PDT 24 Aug 11 05:35:42 PM PDT 24 1325928977 ps
T157 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2053559120 Aug 11 05:35:30 PM PDT 24 Aug 11 05:35:51 PM PDT 24 4956464467 ps
T366 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.3282797828 Aug 11 05:35:34 PM PDT 24 Aug 11 05:35:55 PM PDT 24 32956408453 ps
T367 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1296689322 Aug 11 05:34:56 PM PDT 24 Aug 11 05:39:43 PM PDT 24 104699027816 ps
T151 /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.2670605790 Aug 11 05:35:31 PM PDT 24 Aug 11 05:35:53 PM PDT 24 4818845469 ps
T368 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.324087221 Aug 11 05:35:00 PM PDT 24 Aug 11 05:35:02 PM PDT 24 538778591 ps
T369 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.3058340418 Aug 11 05:35:26 PM PDT 24 Aug 11 05:35:29 PM PDT 24 534032398 ps
T370 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2420163526 Aug 11 05:35:23 PM PDT 24 Aug 11 05:35:26 PM PDT 24 936063848 ps
T371 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.3775154060 Aug 11 05:35:25 PM PDT 24 Aug 11 05:35:28 PM PDT 24 313525927 ps
T372 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.3297598430 Aug 11 05:34:57 PM PDT 24 Aug 11 05:35:05 PM PDT 24 17985809957 ps
T373 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.1858559107 Aug 11 05:35:21 PM PDT 24 Aug 11 05:35:25 PM PDT 24 9444105181 ps
T374 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.1127915783 Aug 11 05:35:07 PM PDT 24 Aug 11 05:35:11 PM PDT 24 1471510907 ps
T375 /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.2428654667 Aug 11 05:35:07 PM PDT 24 Aug 11 05:35:10 PM PDT 24 269172838 ps
T376 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1723699916 Aug 11 05:34:54 PM PDT 24 Aug 11 05:35:01 PM PDT 24 6995752277 ps
T100 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.1261464556 Aug 11 05:35:30 PM PDT 24 Aug 11 05:35:34 PM PDT 24 259384160 ps
T377 /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.2440115779 Aug 11 05:35:04 PM PDT 24 Aug 11 05:35:06 PM PDT 24 135784539 ps
T378 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.153727251 Aug 11 05:35:10 PM PDT 24 Aug 11 05:35:16 PM PDT 24 261389852 ps
T379 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.4212306369 Aug 11 05:35:30 PM PDT 24 Aug 11 05:36:26 PM PDT 24 19215588961 ps
T380 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.2897559924 Aug 11 05:34:55 PM PDT 24 Aug 11 05:34:57 PM PDT 24 80931623 ps
T381 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.114027343 Aug 11 05:35:01 PM PDT 24 Aug 11 05:35:05 PM PDT 24 125291194 ps
T382 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.519808304 Aug 11 05:34:58 PM PDT 24 Aug 11 05:35:06 PM PDT 24 5353273990 ps
T383 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3346391529 Aug 11 05:34:58 PM PDT 24 Aug 11 05:34:59 PM PDT 24 603013823 ps
T101 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3011077300 Aug 11 05:35:30 PM PDT 24 Aug 11 05:35:36 PM PDT 24 459463612 ps
T384 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.2007912850 Aug 11 05:35:35 PM PDT 24 Aug 11 05:35:36 PM PDT 24 938551930 ps
T385 /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.2474223887 Aug 11 05:35:12 PM PDT 24 Aug 11 05:35:16 PM PDT 24 835990223 ps
T386 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.2214667179 Aug 11 05:35:02 PM PDT 24 Aug 11 05:35:03 PM PDT 24 82989989 ps
T102 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.567832710 Aug 11 05:35:12 PM PDT 24 Aug 11 05:35:17 PM PDT 24 1322715452 ps
T387 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.2255303445 Aug 11 05:35:19 PM PDT 24 Aug 11 05:35:20 PM PDT 24 403124288 ps
T388 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.2505108516 Aug 11 05:35:16 PM PDT 24 Aug 11 05:35:25 PM PDT 24 1090113685 ps
T389 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.1798810226 Aug 11 05:35:26 PM PDT 24 Aug 11 05:35:28 PM PDT 24 286025584 ps
T390 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.1013109339 Aug 11 05:35:00 PM PDT 24 Aug 11 05:35:03 PM PDT 24 236912953 ps
T391 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.1125983841 Aug 11 05:35:35 PM PDT 24 Aug 11 05:35:38 PM PDT 24 264085352 ps
T392 /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.4025834446 Aug 11 05:35:22 PM PDT 24 Aug 11 05:38:24 PM PDT 24 26230024821 ps
T154 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.4240805538 Aug 11 05:35:20 PM PDT 24 Aug 11 05:35:40 PM PDT 24 3662453496 ps
T393 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3880342300 Aug 11 05:35:21 PM PDT 24 Aug 11 05:35:32 PM PDT 24 11010407594 ps
T394 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2609114 Aug 11 05:35:06 PM PDT 24 Aug 11 05:35:27 PM PDT 24 12857676286 ps
T158 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.1487154232 Aug 11 05:34:52 PM PDT 24 Aug 11 05:35:09 PM PDT 24 1448524386 ps
T395 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.571208730 Aug 11 05:34:56 PM PDT 24 Aug 11 05:35:33 PM PDT 24 6679357613 ps
T396 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.1571963341 Aug 11 05:35:06 PM PDT 24 Aug 11 05:35:19 PM PDT 24 4523520898 ps
T397 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.3827997660 Aug 11 05:35:32 PM PDT 24 Aug 11 05:35:40 PM PDT 24 2916208090 ps
T398 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.3648996652 Aug 11 05:35:28 PM PDT 24 Aug 11 05:35:31 PM PDT 24 356119163 ps
T399 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.566088522 Aug 11 05:35:12 PM PDT 24 Aug 11 05:35:15 PM PDT 24 2992393512 ps
T400 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.2442060013 Aug 11 05:35:12 PM PDT 24 Aug 11 05:35:28 PM PDT 24 2896497523 ps
T401 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.475028122 Aug 11 05:35:25 PM PDT 24 Aug 11 05:35:28 PM PDT 24 153379858 ps
T402 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.22976188 Aug 11 05:35:11 PM PDT 24 Aug 11 05:35:28 PM PDT 24 5532326340 ps
T403 /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.1786439933 Aug 11 05:34:53 PM PDT 24 Aug 11 05:35:18 PM PDT 24 29364422115 ps
T103 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.662869672 Aug 11 05:35:06 PM PDT 24 Aug 11 05:35:14 PM PDT 24 595329975 ps
T404 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.4090010056 Aug 11 05:35:21 PM PDT 24 Aug 11 05:35:26 PM PDT 24 458683229 ps
T104 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.3781522364 Aug 11 05:35:19 PM PDT 24 Aug 11 05:35:24 PM PDT 24 335403836 ps
T405 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.2471197258 Aug 11 05:35:12 PM PDT 24 Aug 11 05:35:45 PM PDT 24 45684935019 ps
T406 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.2982838250 Aug 11 05:35:32 PM PDT 24 Aug 11 05:35:35 PM PDT 24 90377016 ps
T407 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.3779338130 Aug 11 05:35:33 PM PDT 24 Aug 11 05:35:40 PM PDT 24 505311322 ps
T408 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.4068051244 Aug 11 05:34:58 PM PDT 24 Aug 11 05:35:01 PM PDT 24 1378272553 ps
T409 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.3787458252 Aug 11 05:35:13 PM PDT 24 Aug 11 05:35:14 PM PDT 24 166676516 ps
T410 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.2796297389 Aug 11 05:35:29 PM PDT 24 Aug 11 05:35:34 PM PDT 24 732910771 ps
T411 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3961344736 Aug 11 05:35:28 PM PDT 24 Aug 11 05:35:39 PM PDT 24 2563647337 ps
T412 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.2273259837 Aug 11 05:35:13 PM PDT 24 Aug 11 05:35:25 PM PDT 24 1560740585 ps
T413 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.376249129 Aug 11 05:35:22 PM PDT 24 Aug 11 05:35:25 PM PDT 24 137607922 ps
T414 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1471578949 Aug 11 05:35:19 PM PDT 24 Aug 11 05:35:20 PM PDT 24 208891591 ps
T415 /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.1119974763 Aug 11 05:35:28 PM PDT 24 Aug 11 05:35:30 PM PDT 24 499967802 ps
T416 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.133973416 Aug 11 05:35:29 PM PDT 24 Aug 11 05:35:40 PM PDT 24 4072173185 ps
T417 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.3061640574 Aug 11 05:35:33 PM PDT 24 Aug 11 05:35:40 PM PDT 24 2899756596 ps
T418 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.376550473 Aug 11 05:35:12 PM PDT 24 Aug 11 05:35:13 PM PDT 24 47713983 ps
T419 /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.2357299774 Aug 11 05:34:59 PM PDT 24 Aug 11 05:35:23 PM PDT 24 24518560655 ps
T420 /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3245489384 Aug 11 05:35:34 PM PDT 24 Aug 11 05:35:37 PM PDT 24 167370116 ps
T421 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.851332291 Aug 11 05:35:25 PM PDT 24 Aug 11 05:35:33 PM PDT 24 900214557 ps
T422 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.2276918300 Aug 11 05:35:34 PM PDT 24 Aug 11 05:35:39 PM PDT 24 1951873864 ps
T423 /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1572371927 Aug 11 05:35:26 PM PDT 24 Aug 11 05:35:30 PM PDT 24 409726179 ps
T424 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.2909727584 Aug 11 05:35:03 PM PDT 24 Aug 11 05:36:25 PM PDT 24 19412455931 ps
T425 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.2028476333 Aug 11 05:34:56 PM PDT 24 Aug 11 05:36:08 PM PDT 24 27805432229 ps
T426 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.3243676207 Aug 11 05:35:32 PM PDT 24 Aug 11 05:35:33 PM PDT 24 187820371 ps
T427 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.4168440056 Aug 11 05:34:57 PM PDT 24 Aug 11 05:35:35 PM PDT 24 13436122481 ps
T428 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.874184212 Aug 11 05:35:07 PM PDT 24 Aug 11 05:35:08 PM PDT 24 99195990 ps
T429 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.3067544760 Aug 11 05:34:57 PM PDT 24 Aug 11 05:34:58 PM PDT 24 35307930 ps
T430 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.3710590661 Aug 11 05:35:19 PM PDT 24 Aug 11 05:35:24 PM PDT 24 4229396836 ps
T431 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.2012706722 Aug 11 05:35:28 PM PDT 24 Aug 11 05:35:37 PM PDT 24 1005373617 ps
T432 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.4100259620 Aug 11 05:34:54 PM PDT 24 Aug 11 05:34:56 PM PDT 24 878454874 ps
T433 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.3596473217 Aug 11 05:35:20 PM PDT 24 Aug 11 05:35:23 PM PDT 24 1190247889 ps
T434 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.4268713730 Aug 11 05:35:35 PM PDT 24 Aug 11 05:35:38 PM PDT 24 1851865823 ps
T435 /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.4215610676 Aug 11 05:35:38 PM PDT 24 Aug 11 05:35:41 PM PDT 24 332500921 ps
T436 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.335648629 Aug 11 05:34:59 PM PDT 24 Aug 11 05:35:30 PM PDT 24 3405095358 ps
T437 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.1437832220 Aug 11 05:35:32 PM PDT 24 Aug 11 05:35:34 PM PDT 24 159670837 ps
T438 /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.829229623 Aug 11 05:35:14 PM PDT 24 Aug 11 05:36:13 PM PDT 24 67592898832 ps
T439 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.1974127203 Aug 11 05:35:35 PM PDT 24 Aug 11 05:35:52 PM PDT 24 6689917221 ps
T440 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.3241340862 Aug 11 05:35:20 PM PDT 24 Aug 11 05:35:25 PM PDT 24 337098962 ps
T441 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.2936020611 Aug 11 05:35:00 PM PDT 24 Aug 11 05:35:02 PM PDT 24 1467039633 ps
T442 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.2660243038 Aug 11 05:35:20 PM PDT 24 Aug 11 05:35:30 PM PDT 24 12589326298 ps
T443 /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.810398592 Aug 11 05:34:53 PM PDT 24 Aug 11 05:34:57 PM PDT 24 280868907 ps
T444 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.3412244923 Aug 11 05:35:32 PM PDT 24 Aug 11 05:35:34 PM PDT 24 393625620 ps
T445 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.3430911448 Aug 11 05:35:11 PM PDT 24 Aug 11 05:35:15 PM PDT 24 218866473 ps
T446 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.2163006402 Aug 11 05:34:58 PM PDT 24 Aug 11 05:35:00 PM PDT 24 1811334692 ps
T447 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.1063321003 Aug 11 05:35:11 PM PDT 24 Aug 11 05:35:15 PM PDT 24 1091058858 ps
T448 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.718704403 Aug 11 05:34:56 PM PDT 24 Aug 11 05:34:58 PM PDT 24 857468710 ps
T449 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.1797571525 Aug 11 05:35:28 PM PDT 24 Aug 11 05:35:29 PM PDT 24 48209180 ps
T450 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.1116891911 Aug 11 05:35:25 PM PDT 24 Aug 11 05:35:28 PM PDT 24 284441083 ps
T451 /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.1993084463 Aug 11 05:35:32 PM PDT 24 Aug 11 05:35:39 PM PDT 24 184158406 ps
T452 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.2187777997 Aug 11 05:35:32 PM PDT 24 Aug 11 05:36:20 PM PDT 24 27907562376 ps
T453 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.2420907436 Aug 11 05:35:14 PM PDT 24 Aug 11 05:35:21 PM PDT 24 346695735 ps
T87 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2755501465 Aug 11 05:35:03 PM PDT 24 Aug 11 05:35:11 PM PDT 24 10169311274 ps
T454 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.2411895750 Aug 11 05:35:28 PM PDT 24 Aug 11 05:35:31 PM PDT 24 328204262 ps
T455 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2900840056 Aug 11 05:35:31 PM PDT 24 Aug 11 05:35:35 PM PDT 24 265489689 ps
T456 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.324831241 Aug 11 05:34:59 PM PDT 24 Aug 11 05:38:41 PM PDT 24 226086766345 ps
T457 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.204275332 Aug 11 05:35:36 PM PDT 24 Aug 11 05:35:37 PM PDT 24 238871088 ps
T458 /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.1711216910 Aug 11 05:35:20 PM PDT 24 Aug 11 05:35:23 PM PDT 24 197517329 ps
T459 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.2895660367 Aug 11 05:34:56 PM PDT 24 Aug 11 05:35:29 PM PDT 24 4785648479 ps
T460 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.4235271205 Aug 11 05:35:31 PM PDT 24 Aug 11 05:35:35 PM PDT 24 385689775 ps
T461 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.1563497679 Aug 11 05:35:01 PM PDT 24 Aug 11 05:36:17 PM PDT 24 7559047547 ps
T462 /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.3121174549 Aug 11 05:35:42 PM PDT 24 Aug 11 05:35:47 PM PDT 24 547136265 ps
T463 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.594461755 Aug 11 05:35:20 PM PDT 24 Aug 11 05:35:24 PM PDT 24 1009300551 ps

Test location /workspace/coverage/default/29.rv_dm_stress_all.2037106327
Short name T1
Test name
Test status
Simulation time 12909283266 ps
CPU time 19.33 seconds
Started Aug 11 05:36:33 PM PDT 24
Finished Aug 11 05:36:53 PM PDT 24
Peak memory 213800 kb
Host smart-80bfb8b2-1902-4b2d-bcaa-13aa33becff4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037106327 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.2037106327
Directory /workspace/29.rv_dm_stress_all/latest

Test location /workspace/coverage/default/5.rv_dm_stress_all_with_rand_reset.1204143115
Short name T9
Test name
Test status
Simulation time 13854410909 ps
CPU time 162.1 seconds
Started Aug 11 05:36:10 PM PDT 24
Finished Aug 11 05:38:52 PM PDT 24
Peak memory 222056 kb
Host smart-45b16040-2500-4ec3-90ec-a782db27b495
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204143115 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all_with_rand_reset.1204143115
Directory /workspace/5.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.2991059048
Short name T24
Test name
Test status
Simulation time 10774510348 ps
CPU time 30.38 seconds
Started Aug 11 05:36:32 PM PDT 24
Finished Aug 11 05:37:03 PM PDT 24
Peak memory 213848 kb
Host smart-ba7483ac-ccfd-442d-acce-38fafb8a0a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991059048 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.2991059048
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.2555190187
Short name T51
Test name
Test status
Simulation time 5266084482 ps
CPU time 14.12 seconds
Started Aug 11 05:35:46 PM PDT 24
Finished Aug 11 05:36:00 PM PDT 24
Peak memory 205536 kb
Host smart-06caf5cf-bc30-46f1-8c47-f4653925d194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555190187 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.2555190187
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.976536763
Short name T110
Test name
Test status
Simulation time 1045301293 ps
CPU time 8.41 seconds
Started Aug 11 05:34:59 PM PDT 24
Finished Aug 11 05:35:07 PM PDT 24
Peak memory 213816 kb
Host smart-2cee7b1e-ac9a-4733-aa5c-e63d1d9b3025
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976536763 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.976536763
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/3.rv_dm_stress_all_with_rand_reset.3338116131
Short name T18
Test name
Test status
Simulation time 887567694112 ps
CPU time 1964.9 seconds
Started Aug 11 05:36:11 PM PDT 24
Finished Aug 11 06:08:56 PM PDT 24
Peak memory 249092 kb
Host smart-6ecebee2-e35b-47f5-b072-d647141534af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338116131 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all_with_rand_reset.3338116131
Directory /workspace/3.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.1996558280
Short name T118
Test name
Test status
Simulation time 58325417906 ps
CPU time 115.08 seconds
Started Aug 11 05:36:17 PM PDT 24
Finished Aug 11 05:38:12 PM PDT 24
Peak memory 222112 kb
Host smart-1fc4dca9-d960-4e87-979b-610c3c61cd17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996558280 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.1996558280
Directory /workspace/11.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.82094407
Short name T42
Test name
Test status
Simulation time 615789397 ps
CPU time 1.86 seconds
Started Aug 11 05:36:08 PM PDT 24
Finished Aug 11 05:36:10 PM PDT 24
Peak memory 229524 kb
Host smart-fcac3d14-2e81-4ec7-bd47-5c3d9602686e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82094407 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.82094407
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.1637858027
Short name T77
Test name
Test status
Simulation time 175018349 ps
CPU time 2.24 seconds
Started Aug 11 05:35:14 PM PDT 24
Finished Aug 11 05:35:16 PM PDT 24
Peak memory 213596 kb
Host smart-1e19c162-a858-40a1-99ba-a38125bbbd04
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637858027 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.1637858027
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/default/40.rv_dm_stress_all.1189308866
Short name T23
Test name
Test status
Simulation time 1586803893 ps
CPU time 2.15 seconds
Started Aug 11 05:36:37 PM PDT 24
Finished Aug 11 05:36:39 PM PDT 24
Peak memory 205476 kb
Host smart-a0422f9f-b683-4b77-9963-8299a3fd5613
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189308866 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.1189308866
Directory /workspace/40.rv_dm_stress_all/latest

Test location /workspace/coverage/default/1.rv_dm_sba_debug_disabled.1885955334
Short name T114
Test name
Test status
Simulation time 821293525 ps
CPU time 3.08 seconds
Started Aug 11 05:36:03 PM PDT 24
Finished Aug 11 05:36:06 PM PDT 24
Peak memory 205328 kb
Host smart-d18f2c27-ad72-4732-959b-103747496797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885955334 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.1885955334
Directory /workspace/1.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_dmi_failed_op.2873162605
Short name T45
Test name
Test status
Simulation time 184355443 ps
CPU time 0.7 seconds
Started Aug 11 05:35:54 PM PDT 24
Finished Aug 11 05:35:55 PM PDT 24
Peak memory 205184 kb
Host smart-32fe6877-aa35-4acd-8298-261fa0d1a17d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873162605 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dmi_failed_op.2873162605
Directory /workspace/0.rv_dm_dmi_failed_op/latest

Test location /workspace/coverage/default/1.rv_dm_dmi_failed_op.196591126
Short name T50
Test name
Test status
Simulation time 475798180 ps
CPU time 1.27 seconds
Started Aug 11 05:36:04 PM PDT 24
Finished Aug 11 05:36:06 PM PDT 24
Peak memory 205228 kb
Host smart-460803f0-749f-4b59-9130-1667f8468066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196591126 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dmi_failed_op.196591126
Directory /workspace/1.rv_dm_dmi_failed_op/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.761656956
Short name T107
Test name
Test status
Simulation time 5218447855 ps
CPU time 29.34 seconds
Started Aug 11 05:35:27 PM PDT 24
Finished Aug 11 05:35:56 PM PDT 24
Peak memory 213860 kb
Host smart-58a6923a-2027-4bb3-834f-af43ef95b41e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761656956 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.761656956
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.2265231750
Short name T137
Test name
Test status
Simulation time 4791675687 ps
CPU time 12.95 seconds
Started Aug 11 05:36:32 PM PDT 24
Finished Aug 11 05:36:45 PM PDT 24
Peak memory 213596 kb
Host smart-3e7821ce-4338-4528-8b8d-1c21e71a5664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265231750 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.2265231750
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.860004586
Short name T17
Test name
Test status
Simulation time 475536344 ps
CPU time 1.69 seconds
Started Aug 11 05:35:57 PM PDT 24
Finished Aug 11 05:35:59 PM PDT 24
Peak memory 205284 kb
Host smart-c8aeeba1-c9fb-4548-a087-ffff14bcc196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860004586 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.860004586
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.4227505387
Short name T176
Test name
Test status
Simulation time 62000712 ps
CPU time 0.69 seconds
Started Aug 11 05:36:33 PM PDT 24
Finished Aug 11 05:36:34 PM PDT 24
Peak memory 205172 kb
Host smart-0289b6ab-e7aa-4867-86d7-b6f5bcaa2b35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227505387 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.4227505387
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.2752963814
Short name T32
Test name
Test status
Simulation time 148728929 ps
CPU time 1.11 seconds
Started Aug 11 05:35:54 PM PDT 24
Finished Aug 11 05:35:55 PM PDT 24
Peak memory 213400 kb
Host smart-05f4d42d-bdb3-4543-bcb7-7cd532673dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752963814 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.2752963814
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_stress_all_with_rand_reset.666839447
Short name T20
Test name
Test status
Simulation time 50910851928 ps
CPU time 736.42 seconds
Started Aug 11 05:36:00 PM PDT 24
Finished Aug 11 05:48:16 PM PDT 24
Peak memory 230964 kb
Host smart-34aa1aa0-804f-486d-92db-64c72fdf7742
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666839447 -assert nopostp
roc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all_with_rand_reset.666839447
Directory /workspace/1.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.1729523627
Short name T123
Test name
Test status
Simulation time 8818502137 ps
CPU time 24.84 seconds
Started Aug 11 05:36:17 PM PDT 24
Finished Aug 11 05:36:42 PM PDT 24
Peak memory 215344 kb
Host smart-df0ef065-5e19-407f-b544-10081e046600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729523627 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.1729523627
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.4240805538
Short name T154
Test name
Test status
Simulation time 3662453496 ps
CPU time 20.3 seconds
Started Aug 11 05:35:20 PM PDT 24
Finished Aug 11 05:35:40 PM PDT 24
Peak memory 213880 kb
Host smart-46ee58c9-0ee4-43ef-aa18-9b068c246511
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240805538 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.4240805538
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.1350225284
Short name T53
Test name
Test status
Simulation time 33472571693 ps
CPU time 99.87 seconds
Started Aug 11 05:35:14 PM PDT 24
Finished Aug 11 05:36:54 PM PDT 24
Peak memory 222112 kb
Host smart-884aea64-e3da-4be2-ac71-87b3b592f0be
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350225284 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.1350225284
Directory /workspace/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/0.rv_dm_hartsel_warl.2967488687
Short name T25
Test name
Test status
Simulation time 226198682 ps
CPU time 1.24 seconds
Started Aug 11 05:35:54 PM PDT 24
Finished Aug 11 05:35:56 PM PDT 24
Peak memory 204904 kb
Host smart-8c7f187f-d164-41fb-8598-3f6600b60892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967488687 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hartsel_warl_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hartsel_warl.2967488687
Directory /workspace/0.rv_dm_hartsel_warl/latest

Test location /workspace/coverage/default/6.rv_dm_stress_all_with_rand_reset.3332361071
Short name T67
Test name
Test status
Simulation time 21968590435 ps
CPU time 250.76 seconds
Started Aug 11 05:36:14 PM PDT 24
Finished Aug 11 05:40:25 PM PDT 24
Peak memory 221976 kb
Host smart-73a1fe73-1380-4a01-ad5e-3cbb6d44805c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332361071 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all_with_rand_reset.3332361071
Directory /workspace/6.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.rv_dm_stress_all.2729850537
Short name T6
Test name
Test status
Simulation time 4054444318 ps
CPU time 3.34 seconds
Started Aug 11 05:35:54 PM PDT 24
Finished Aug 11 05:35:57 PM PDT 24
Peak memory 213712 kb
Host smart-21580f0f-8d85-4177-aed1-dfa973faca9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729850537 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.2729850537
Directory /workspace/0.rv_dm_stress_all/latest

Test location /workspace/coverage/default/1.rv_dm_stress_all.2650924495
Short name T253
Test name
Test status
Simulation time 4366168095 ps
CPU time 7.32 seconds
Started Aug 11 05:36:03 PM PDT 24
Finished Aug 11 05:36:10 PM PDT 24
Peak memory 213732 kb
Host smart-bb12322c-a8ba-44af-acf9-6bbc4bfb0059
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650924495 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.2650924495
Directory /workspace/1.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.2773695594
Short name T324
Test name
Test status
Simulation time 296202850 ps
CPU time 1.48 seconds
Started Aug 11 05:34:54 PM PDT 24
Finished Aug 11 05:34:55 PM PDT 24
Peak memory 205272 kb
Host smart-4fb9eb18-0f5c-4d73-b3a6-63b635746b5a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773695594 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.2773695594
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/default/0.rv_dm_abstractcmd_status.1814622398
Short name T38
Test name
Test status
Simulation time 186021836 ps
CPU time 0.87 seconds
Started Aug 11 05:35:54 PM PDT 24
Finished Aug 11 05:35:55 PM PDT 24
Peak memory 205212 kb
Host smart-1d3168f0-cd59-458e-9212-18b2e05aedef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814622398 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.1814622398
Directory /workspace/0.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.3339269092
Short name T84
Test name
Test status
Simulation time 4174596488 ps
CPU time 12.68 seconds
Started Aug 11 05:34:54 PM PDT 24
Finished Aug 11 05:35:07 PM PDT 24
Peak memory 205604 kb
Host smart-45d08948-6fd6-4703-96a9-c283aade93a7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339269092 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_hw_reset.3339269092
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.928317560
Short name T83
Test name
Test status
Simulation time 531413856 ps
CPU time 7.7 seconds
Started Aug 11 05:34:59 PM PDT 24
Finished Aug 11 05:35:06 PM PDT 24
Peak memory 205612 kb
Host smart-492a61df-7430-4d94-8e11-a7d70a065841
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928317560 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_c
sr_outstanding.928317560
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.333900077
Short name T29
Test name
Test status
Simulation time 544588219 ps
CPU time 1.04 seconds
Started Aug 11 05:35:53 PM PDT 24
Finished Aug 11 05:35:54 PM PDT 24
Peak memory 205168 kb
Host smart-0cc67b6e-d7ed-4c62-aa88-383436f01dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333900077 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.333900077
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2053559120
Short name T157
Test name
Test status
Simulation time 4956464467 ps
CPU time 20.35 seconds
Started Aug 11 05:35:30 PM PDT 24
Finished Aug 11 05:35:51 PM PDT 24
Peak memory 213820 kb
Host smart-e496442d-b94d-443c-a119-caca88069178
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053559120 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.2
053559120
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/10.rv_dm_stress_all.1876317171
Short name T140
Test name
Test status
Simulation time 3453291448 ps
CPU time 9.65 seconds
Started Aug 11 05:36:17 PM PDT 24
Finished Aug 11 05:36:27 PM PDT 24
Peak memory 205584 kb
Host smart-c4c51456-84a2-4996-b4c3-7eb372bbcca3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876317171 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.1876317171
Directory /workspace/10.rv_dm_stress_all/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.1532450831
Short name T143
Test name
Test status
Simulation time 10197033578 ps
CPU time 8.96 seconds
Started Aug 11 05:36:24 PM PDT 24
Finished Aug 11 05:36:33 PM PDT 24
Peak memory 213868 kb
Host smart-2de5079e-0599-488f-a1d0-7cea21d205fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532450831 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.1532450831
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/20.rv_dm_stress_all.2988056237
Short name T135
Test name
Test status
Simulation time 5695469299 ps
CPU time 6.05 seconds
Started Aug 11 05:36:32 PM PDT 24
Finished Aug 11 05:36:38 PM PDT 24
Peak memory 213660 kb
Host smart-29053b12-2eb0-4dbe-9ef1-1517ca2c1d49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988056237 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.2988056237
Directory /workspace/20.rv_dm_stress_all/latest

Test location /workspace/coverage/default/42.rv_dm_stress_all.3361613603
Short name T115
Test name
Test status
Simulation time 4351948491 ps
CPU time 10.14 seconds
Started Aug 11 05:36:36 PM PDT 24
Finished Aug 11 05:36:46 PM PDT 24
Peak memory 213708 kb
Host smart-8592c555-dc4c-4647-9247-cd02361dfcea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361613603 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.3361613603
Directory /workspace/42.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.1963564757
Short name T95
Test name
Test status
Simulation time 205690809 ps
CPU time 2.36 seconds
Started Aug 11 05:35:27 PM PDT 24
Finished Aug 11 05:35:29 PM PDT 24
Peak memory 213736 kb
Host smart-2abb5b86-4ecc-417c-ad1d-9d96ce2f2c9e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963564757 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.1963564757
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.1091040231
Short name T179
Test name
Test status
Simulation time 5218005266 ps
CPU time 4.69 seconds
Started Aug 11 05:36:03 PM PDT 24
Finished Aug 11 05:36:08 PM PDT 24
Peak memory 213840 kb
Host smart-4ac89e79-0eda-4c27-8f91-95130ea5b347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091040231 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.1091040231
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.347333771
Short name T99
Test name
Test status
Simulation time 3509588780 ps
CPU time 74.36 seconds
Started Aug 11 05:34:59 PM PDT 24
Finished Aug 11 05:36:13 PM PDT 24
Peak memory 213948 kb
Host smart-d8554680-6f63-4c97-ae7b-7dfbfc939eb8
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347333771 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.rv_dm_csr_aliasing.347333771
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.571208730
Short name T395
Test name
Test status
Simulation time 6679357613 ps
CPU time 37.11 seconds
Started Aug 11 05:34:56 PM PDT 24
Finished Aug 11 05:35:33 PM PDT 24
Peak memory 205724 kb
Host smart-29d21794-6a85-4be6-b09d-c162ccaae332
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571208730 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.571208730
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3293149679
Short name T94
Test name
Test status
Simulation time 194807141 ps
CPU time 2.65 seconds
Started Aug 11 05:34:56 PM PDT 24
Finished Aug 11 05:34:58 PM PDT 24
Peak memory 213764 kb
Host smart-7a946dd2-f4ee-4fd2-bfbc-ea4cdf4222ad
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293149679 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.3293149679
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3314618328
Short name T339
Test name
Test status
Simulation time 369354294 ps
CPU time 3.85 seconds
Started Aug 11 05:34:55 PM PDT 24
Finished Aug 11 05:34:59 PM PDT 24
Peak memory 219104 kb
Host smart-dd330caa-1cd4-41a6-9be4-b87bc8247b5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314618328 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.3314618328
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.2897559924
Short name T380
Test name
Test status
Simulation time 80931623 ps
CPU time 2.26 seconds
Started Aug 11 05:34:55 PM PDT 24
Finished Aug 11 05:34:57 PM PDT 24
Peak memory 213704 kb
Host smart-7a09a2d0-ed17-4972-b1fa-35810a6898d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897559924 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.2897559924
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1296689322
Short name T367
Test name
Test status
Simulation time 104699027816 ps
CPU time 286.32 seconds
Started Aug 11 05:34:56 PM PDT 24
Finished Aug 11 05:39:43 PM PDT 24
Peak memory 205604 kb
Host smart-9c2356f6-ed23-494e-8995-9e1aba137e9e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296689322 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_aliasing.1296689322
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.2028476333
Short name T425
Test name
Test status
Simulation time 27805432229 ps
CPU time 71.85 seconds
Started Aug 11 05:34:56 PM PDT 24
Finished Aug 11 05:36:08 PM PDT 24
Peak memory 205552 kb
Host smart-3f829230-ca5e-46d3-b079-fbb28f788498
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028476333 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
rv_dm_jtag_dmi_csr_bit_bash.2028476333
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.4168440056
Short name T427
Test name
Test status
Simulation time 13436122481 ps
CPU time 37.39 seconds
Started Aug 11 05:34:57 PM PDT 24
Finished Aug 11 05:35:35 PM PDT 24
Peak memory 205476 kb
Host smart-c94e4f47-f4e8-40be-bdb9-b83c01d08ef8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168440056 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.4
168440056
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.4100259620
Short name T432
Test name
Test status
Simulation time 878454874 ps
CPU time 1.94 seconds
Started Aug 11 05:34:54 PM PDT 24
Finished Aug 11 05:34:56 PM PDT 24
Peak memory 205240 kb
Host smart-e8ca8a48-b79b-4914-9e66-57320ea0ed51
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100259620 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.4100259620
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1723699916
Short name T376
Test name
Test status
Simulation time 6995752277 ps
CPU time 6.92 seconds
Started Aug 11 05:34:54 PM PDT 24
Finished Aug 11 05:35:01 PM PDT 24
Peak memory 205600 kb
Host smart-7718e9a1-5618-4455-84f8-4a8f623a9dc3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723699916 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_bit_bash.1723699916
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.718704403
Short name T448
Test name
Test status
Simulation time 857468710 ps
CPU time 2.17 seconds
Started Aug 11 05:34:56 PM PDT 24
Finished Aug 11 05:34:58 PM PDT 24
Peak memory 205244 kb
Host smart-6beb59ff-2219-41f3-91d5-f195fd6bc365
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718704403 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.718704403
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.3067544760
Short name T429
Test name
Test status
Simulation time 35307930 ps
CPU time 0.77 seconds
Started Aug 11 05:34:57 PM PDT 24
Finished Aug 11 05:34:58 PM PDT 24
Peak memory 205340 kb
Host smart-212c7b4d-a631-4f44-a905-6fe4b1fc5cf0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067544760 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.3067544760
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.492051560
Short name T319
Test name
Test status
Simulation time 56641273 ps
CPU time 0.69 seconds
Started Aug 11 05:34:57 PM PDT 24
Finished Aug 11 05:34:58 PM PDT 24
Peak memory 205324 kb
Host smart-7d87aeae-7777-4491-bbdf-57a0bc7f25fb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492051560 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.492051560
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.810398592
Short name T443
Test name
Test status
Simulation time 280868907 ps
CPU time 4.27 seconds
Started Aug 11 05:34:53 PM PDT 24
Finished Aug 11 05:34:57 PM PDT 24
Peak memory 205548 kb
Host smart-0539436c-7c96-49a1-9ed8-7d92974d91b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810398592 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_c
sr_outstanding.810398592
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.1786439933
Short name T403
Test name
Test status
Simulation time 29364422115 ps
CPU time 25.49 seconds
Started Aug 11 05:34:53 PM PDT 24
Finished Aug 11 05:35:18 PM PDT 24
Peak memory 222020 kb
Host smart-d04d135c-a5c7-4530-8458-4e47b8db426f
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786439933 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.1786439933
Directory /workspace/0.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.2120198022
Short name T350
Test name
Test status
Simulation time 181970727 ps
CPU time 3.03 seconds
Started Aug 11 05:34:59 PM PDT 24
Finished Aug 11 05:35:02 PM PDT 24
Peak memory 213776 kb
Host smart-bd30fd04-b9b3-449a-916f-7f3c3b3bc077
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120198022 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.2120198022
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.1487154232
Short name T158
Test name
Test status
Simulation time 1448524386 ps
CPU time 16.74 seconds
Started Aug 11 05:34:52 PM PDT 24
Finished Aug 11 05:35:09 PM PDT 24
Peak memory 213800 kb
Host smart-a95823dd-4882-4b95-b1c9-c1d14e329085
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487154232 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.1487154232
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.2895660367
Short name T459
Test name
Test status
Simulation time 4785648479 ps
CPU time 32.83 seconds
Started Aug 11 05:34:56 PM PDT 24
Finished Aug 11 05:35:29 PM PDT 24
Peak memory 215012 kb
Host smart-d4cce378-2a85-44c4-9caa-63ee68f2da8c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895660367 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.2895660367
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.1563497679
Short name T461
Test name
Test status
Simulation time 7559047547 ps
CPU time 75.41 seconds
Started Aug 11 05:35:01 PM PDT 24
Finished Aug 11 05:36:17 PM PDT 24
Peak memory 205608 kb
Host smart-979614b3-dff5-4ba7-b0be-2202685c2e24
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563497679 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.1563497679
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2393643872
Short name T80
Test name
Test status
Simulation time 260764160 ps
CPU time 2.76 seconds
Started Aug 11 05:35:01 PM PDT 24
Finished Aug 11 05:35:05 PM PDT 24
Peak memory 213704 kb
Host smart-81e15d25-6114-4b3f-86b4-fe5a7b3e288c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393643872 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.2393643872
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.1013109339
Short name T390
Test name
Test status
Simulation time 236912953 ps
CPU time 2.64 seconds
Started Aug 11 05:35:00 PM PDT 24
Finished Aug 11 05:35:03 PM PDT 24
Peak memory 221984 kb
Host smart-2894a4df-7512-4ded-8d8a-039da0e9bb3b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013109339 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.1013109339
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.2440115779
Short name T377
Test name
Test status
Simulation time 135784539 ps
CPU time 2.58 seconds
Started Aug 11 05:35:04 PM PDT 24
Finished Aug 11 05:35:06 PM PDT 24
Peak memory 213608 kb
Host smart-bfb9b5fe-6ca7-4618-a169-2f01a80d167e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440115779 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.2440115779
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.324831241
Short name T456
Test name
Test status
Simulation time 226086766345 ps
CPU time 222.24 seconds
Started Aug 11 05:34:59 PM PDT 24
Finished Aug 11 05:38:41 PM PDT 24
Peak memory 211552 kb
Host smart-bd6c11ef-747d-447b-b4d8-6d63e3ee68e0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324831241 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr
_aliasing.324831241
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3827405534
Short name T349
Test name
Test status
Simulation time 17135063472 ps
CPU time 43.15 seconds
Started Aug 11 05:35:00 PM PDT 24
Finished Aug 11 05:35:43 PM PDT 24
Peak memory 205544 kb
Host smart-efdba87c-0ff5-493e-b7d7-fbceba34752e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827405534 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
rv_dm_jtag_dmi_csr_bit_bash.3827405534
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.4068051244
Short name T408
Test name
Test status
Simulation time 1378272553 ps
CPU time 2.77 seconds
Started Aug 11 05:34:58 PM PDT 24
Finished Aug 11 05:35:01 PM PDT 24
Peak memory 205536 kb
Host smart-3ca7577b-dfe2-4def-bea5-36e46f458042
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068051244 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.4068051244
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.2163006402
Short name T446
Test name
Test status
Simulation time 1811334692 ps
CPU time 1.96 seconds
Started Aug 11 05:34:58 PM PDT 24
Finished Aug 11 05:35:00 PM PDT 24
Peak memory 205472 kb
Host smart-bb1bf151-7eab-4f82-b2f9-f93077746ccb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163006402 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.2
163006402
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.2936020611
Short name T441
Test name
Test status
Simulation time 1467039633 ps
CPU time 1.72 seconds
Started Aug 11 05:35:00 PM PDT 24
Finished Aug 11 05:35:02 PM PDT 24
Peak memory 205240 kb
Host smart-d80128f4-4c50-49e9-b23d-6c9790e43f46
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936020611 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_aliasing.2936020611
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.3615629818
Short name T326
Test name
Test status
Simulation time 17947645564 ps
CPU time 29.48 seconds
Started Aug 11 05:34:57 PM PDT 24
Finished Aug 11 05:35:26 PM PDT 24
Peak memory 205612 kb
Host smart-fc87ebde-235f-4f83-8bbe-ee5c2b3ae8aa
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615629818 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_bit_bash.3615629818
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.3201336775
Short name T335
Test name
Test status
Simulation time 163646430 ps
CPU time 1.08 seconds
Started Aug 11 05:34:57 PM PDT 24
Finished Aug 11 05:34:58 PM PDT 24
Peak memory 205224 kb
Host smart-13a78d63-4ef1-4228-a676-d0dba2812613
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201336775 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.3201336775
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3346391529
Short name T383
Test name
Test status
Simulation time 603013823 ps
CPU time 0.87 seconds
Started Aug 11 05:34:58 PM PDT 24
Finished Aug 11 05:34:59 PM PDT 24
Peak memory 204256 kb
Host smart-b6724fe3-a066-435f-8eb3-db234c5b91c6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346391529 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.3
346391529
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.2214667179
Short name T386
Test name
Test status
Simulation time 82989989 ps
CPU time 0.72 seconds
Started Aug 11 05:35:02 PM PDT 24
Finished Aug 11 05:35:03 PM PDT 24
Peak memory 205224 kb
Host smart-a1fe9634-7825-4aa5-a507-3a17640eac15
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214667179 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.2214667179
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.104197971
Short name T363
Test name
Test status
Simulation time 36322886 ps
CPU time 0.7 seconds
Started Aug 11 05:34:59 PM PDT 24
Finished Aug 11 05:35:00 PM PDT 24
Peak memory 205228 kb
Host smart-3d752c91-189a-4a8c-866b-ff8609708cbb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104197971 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.104197971
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.2357299774
Short name T419
Test name
Test status
Simulation time 24518560655 ps
CPU time 23.6 seconds
Started Aug 11 05:34:59 PM PDT 24
Finished Aug 11 05:35:23 PM PDT 24
Peak memory 222140 kb
Host smart-25ca0d26-4da1-475e-913f-b6a117562852
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357299774 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.2357299774
Directory /workspace/1.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.114027343
Short name T381
Test name
Test status
Simulation time 125291194 ps
CPU time 3.08 seconds
Started Aug 11 05:35:01 PM PDT 24
Finished Aug 11 05:35:05 PM PDT 24
Peak memory 213816 kb
Host smart-8e260700-ae46-4135-9da2-58c9ee461318
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114027343 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.114027343
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3245489384
Short name T420
Test name
Test status
Simulation time 167370116 ps
CPU time 2.86 seconds
Started Aug 11 05:35:34 PM PDT 24
Finished Aug 11 05:35:37 PM PDT 24
Peak memory 213836 kb
Host smart-e4c4f365-6240-45c5-9a88-25c9ae187a55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245489384 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.3245489384
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.829267374
Short name T89
Test name
Test status
Simulation time 100994336 ps
CPU time 2.09 seconds
Started Aug 11 05:35:29 PM PDT 24
Finished Aug 11 05:35:31 PM PDT 24
Peak memory 213732 kb
Host smart-a221cfe3-c31b-4825-aa2a-7f3c1629b5a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829267374 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.829267374
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.1858559107
Short name T373
Test name
Test status
Simulation time 9444105181 ps
CPU time 4.58 seconds
Started Aug 11 05:35:21 PM PDT 24
Finished Aug 11 05:35:25 PM PDT 24
Peak memory 205620 kb
Host smart-af6a58b5-8486-48a4-870c-d43c2fc91e06
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858559107 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.rv_dm_jtag_dmi_csr_bit_bash.1858559107
Directory /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.4106889170
Short name T318
Test name
Test status
Simulation time 6233861005 ps
CPU time 10.83 seconds
Started Aug 11 05:35:21 PM PDT 24
Finished Aug 11 05:35:32 PM PDT 24
Peak memory 205556 kb
Host smart-9a8683f3-85b8-4fee-9399-4d43fe6d7be0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106889170 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.
4106889170
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1471578949
Short name T414
Test name
Test status
Simulation time 208891591 ps
CPU time 0.79 seconds
Started Aug 11 05:35:19 PM PDT 24
Finished Aug 11 05:35:20 PM PDT 24
Peak memory 205220 kb
Host smart-ebac7d9b-6ffa-4727-99db-9007cfb5066e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471578949 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
1471578949
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.851332291
Short name T421
Test name
Test status
Simulation time 900214557 ps
CPU time 7.77 seconds
Started Aug 11 05:35:25 PM PDT 24
Finished Aug 11 05:35:33 PM PDT 24
Peak memory 205552 kb
Host smart-ae868f38-8526-4869-8e65-cb1a95a05486
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851332291 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same_
csr_outstanding.851332291
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3154537332
Short name T68
Test name
Test status
Simulation time 84044986 ps
CPU time 3.3 seconds
Started Aug 11 05:35:21 PM PDT 24
Finished Aug 11 05:35:25 PM PDT 24
Peak memory 213904 kb
Host smart-3c546277-7a89-418d-b345-6d3539877e97
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154537332 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.3154537332
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1981672073
Short name T111
Test name
Test status
Simulation time 669584935 ps
CPU time 8.85 seconds
Started Aug 11 05:35:25 PM PDT 24
Finished Aug 11 05:35:34 PM PDT 24
Peak memory 213728 kb
Host smart-d74d344f-bd24-48a0-8159-530c00510078
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981672073 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.1
981672073
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.2411895750
Short name T454
Test name
Test status
Simulation time 328204262 ps
CPU time 2.76 seconds
Started Aug 11 05:35:28 PM PDT 24
Finished Aug 11 05:35:31 PM PDT 24
Peak memory 215224 kb
Host smart-9a7b47c1-dde9-44d8-b067-957848c36167
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411895750 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.2411895750
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.3466469611
Short name T338
Test name
Test status
Simulation time 63197468 ps
CPU time 0.68 seconds
Started Aug 11 05:35:25 PM PDT 24
Finished Aug 11 05:35:26 PM PDT 24
Peak memory 205288 kb
Host smart-8ebb9894-2c81-4707-ba02-256e8bcfcb0d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466469611 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.rv_dm_jtag_dmi_csr_bit_bash.3466469611
Directory /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.2276918300
Short name T422
Test name
Test status
Simulation time 1951873864 ps
CPU time 4.15 seconds
Started Aug 11 05:35:34 PM PDT 24
Finished Aug 11 05:35:39 PM PDT 24
Peak memory 205428 kb
Host smart-6fc95a86-9715-4230-96a9-b59dbce05a0a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276918300 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
2276918300
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.1629276547
Short name T347
Test name
Test status
Simulation time 178628423 ps
CPU time 0.92 seconds
Started Aug 11 05:35:35 PM PDT 24
Finished Aug 11 05:35:36 PM PDT 24
Peak memory 205264 kb
Host smart-380e4295-d034-44b5-8538-8944512bc7a3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629276547 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.
1629276547
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.3013984030
Short name T75
Test name
Test status
Simulation time 644649548 ps
CPU time 8.48 seconds
Started Aug 11 05:35:28 PM PDT 24
Finished Aug 11 05:35:36 PM PDT 24
Peak memory 205576 kb
Host smart-d7e9a8d3-0bbd-4268-a1f0-b3b603212fe2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013984030 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same
_csr_outstanding.3013984030
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.3648996652
Short name T398
Test name
Test status
Simulation time 356119163 ps
CPU time 2.22 seconds
Started Aug 11 05:35:28 PM PDT 24
Finished Aug 11 05:35:31 PM PDT 24
Peak memory 213908 kb
Host smart-0c0be5a5-ffcf-4b0a-add1-e152f3b5b27d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648996652 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.3648996652
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.2012706722
Short name T431
Test name
Test status
Simulation time 1005373617 ps
CPU time 9.07 seconds
Started Aug 11 05:35:28 PM PDT 24
Finished Aug 11 05:35:37 PM PDT 24
Peak memory 214104 kb
Host smart-813acdb7-a128-44c5-bb43-1c04686a4ef0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012706722 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.2
012706722
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.1405677917
Short name T322
Test name
Test status
Simulation time 118933447 ps
CPU time 2.47 seconds
Started Aug 11 05:35:36 PM PDT 24
Finished Aug 11 05:35:38 PM PDT 24
Peak memory 218748 kb
Host smart-08829ce2-01e4-4b77-9860-a126d6711052
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405677917 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.1405677917
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.2301209153
Short name T359
Test name
Test status
Simulation time 419897453 ps
CPU time 2.29 seconds
Started Aug 11 05:35:33 PM PDT 24
Finished Aug 11 05:35:36 PM PDT 24
Peak memory 213736 kb
Host smart-55aab45d-df15-4320-bd98-72455b3ed0ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301209153 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.2301209153
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.1797571525
Short name T449
Test name
Test status
Simulation time 48209180 ps
CPU time 0.76 seconds
Started Aug 11 05:35:28 PM PDT 24
Finished Aug 11 05:35:29 PM PDT 24
Peak memory 205284 kb
Host smart-b417d681-bb2c-401b-a1d6-6857ee6df823
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797571525 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.rv_dm_jtag_dmi_csr_bit_bash.1797571525
Directory /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.416047575
Short name T336
Test name
Test status
Simulation time 10306577269 ps
CPU time 12.97 seconds
Started Aug 11 05:35:31 PM PDT 24
Finished Aug 11 05:35:44 PM PDT 24
Peak memory 205560 kb
Host smart-6a12689a-60e9-4fdf-8a6e-939d8ffd09dd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416047575 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.416047575
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.4002260265
Short name T346
Test name
Test status
Simulation time 209496214 ps
CPU time 0.93 seconds
Started Aug 11 05:35:26 PM PDT 24
Finished Aug 11 05:35:27 PM PDT 24
Peak memory 205220 kb
Host smart-fd0649b4-8935-4a40-bfd5-b6940b7d1d64
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002260265 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
4002260265
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1572371927
Short name T423
Test name
Test status
Simulation time 409726179 ps
CPU time 3.92 seconds
Started Aug 11 05:35:26 PM PDT 24
Finished Aug 11 05:35:30 PM PDT 24
Peak memory 205600 kb
Host smart-a00e114d-039d-46fa-a03a-e5e328a12a70
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572371927 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.1572371927
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.2796297389
Short name T410
Test name
Test status
Simulation time 732910771 ps
CPU time 4.32 seconds
Started Aug 11 05:35:29 PM PDT 24
Finished Aug 11 05:35:34 PM PDT 24
Peak memory 213860 kb
Host smart-90520cc0-cc40-4484-9370-68b214369991
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796297389 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.2796297389
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3207400186
Short name T155
Test name
Test status
Simulation time 2936087241 ps
CPU time 16.21 seconds
Started Aug 11 05:35:28 PM PDT 24
Finished Aug 11 05:35:44 PM PDT 24
Peak memory 213864 kb
Host smart-661121a9-9581-42c4-a172-8b4387e8589e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207400186 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.3
207400186
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.1929631820
Short name T71
Test name
Test status
Simulation time 286154484 ps
CPU time 3.72 seconds
Started Aug 11 05:35:26 PM PDT 24
Finished Aug 11 05:35:30 PM PDT 24
Peak memory 219208 kb
Host smart-f933ad9b-cbf2-415a-8ebe-b86dd0d82760
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929631820 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.1929631820
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.1119974763
Short name T415
Test name
Test status
Simulation time 499967802 ps
CPU time 2.42 seconds
Started Aug 11 05:35:28 PM PDT 24
Finished Aug 11 05:35:30 PM PDT 24
Peak memory 213700 kb
Host smart-4f6d143f-e4c7-4bc3-a953-366350ab2fdd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119974763 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.1119974763
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.3282797828
Short name T366
Test name
Test status
Simulation time 32956408453 ps
CPU time 20.11 seconds
Started Aug 11 05:35:34 PM PDT 24
Finished Aug 11 05:35:55 PM PDT 24
Peak memory 205500 kb
Host smart-6aeeebab-4684-4091-9b70-00f61b386b5b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282797828 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.rv_dm_jtag_dmi_csr_bit_bash.3282797828
Directory /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.2007912850
Short name T384
Test name
Test status
Simulation time 938551930 ps
CPU time 1.36 seconds
Started Aug 11 05:35:35 PM PDT 24
Finished Aug 11 05:35:36 PM PDT 24
Peak memory 205388 kb
Host smart-8e685260-fed7-454e-8655-20a1a2ea70df
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007912850 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
2007912850
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.3058340418
Short name T369
Test name
Test status
Simulation time 534032398 ps
CPU time 2.25 seconds
Started Aug 11 05:35:26 PM PDT 24
Finished Aug 11 05:35:29 PM PDT 24
Peak memory 205212 kb
Host smart-f3f309cf-fe53-4397-b1ec-311cb95c44eb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058340418 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
3058340418
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.3556869247
Short name T96
Test name
Test status
Simulation time 334918552 ps
CPU time 3.68 seconds
Started Aug 11 05:35:25 PM PDT 24
Finished Aug 11 05:35:28 PM PDT 24
Peak memory 205444 kb
Host smart-0019efac-da8e-4c33-a153-55d2c9e6863c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556869247 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.3556869247
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.3775154060
Short name T371
Test name
Test status
Simulation time 313525927 ps
CPU time 2.98 seconds
Started Aug 11 05:35:25 PM PDT 24
Finished Aug 11 05:35:28 PM PDT 24
Peak memory 213784 kb
Host smart-25076a2d-8a94-42e6-9c05-88e0992f87fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775154060 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.3775154060
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.339995677
Short name T69
Test name
Test status
Simulation time 659331683 ps
CPU time 4 seconds
Started Aug 11 05:35:29 PM PDT 24
Finished Aug 11 05:35:33 PM PDT 24
Peak memory 219828 kb
Host smart-ff8df924-a4f6-4b3b-8101-ab5429366598
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339995677 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.339995677
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.1798810226
Short name T389
Test name
Test status
Simulation time 286025584 ps
CPU time 1.69 seconds
Started Aug 11 05:35:26 PM PDT 24
Finished Aug 11 05:35:28 PM PDT 24
Peak memory 213692 kb
Host smart-86d0ef5a-3d26-4d26-8507-0e521d28a316
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798810226 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.1798810226
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.4212306369
Short name T379
Test name
Test status
Simulation time 19215588961 ps
CPU time 55.39 seconds
Started Aug 11 05:35:30 PM PDT 24
Finished Aug 11 05:36:26 PM PDT 24
Peak memory 205536 kb
Host smart-4b9242bf-731c-4d6d-bde8-a1952e299648
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212306369 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.rv_dm_jtag_dmi_csr_bit_bash.4212306369
Directory /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.1974127203
Short name T439
Test name
Test status
Simulation time 6689917221 ps
CPU time 17.04 seconds
Started Aug 11 05:35:35 PM PDT 24
Finished Aug 11 05:35:52 PM PDT 24
Peak memory 205620 kb
Host smart-a20ab8fc-3131-40fb-aba5-856ec8403675
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974127203 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
1974127203
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2705338702
Short name T321
Test name
Test status
Simulation time 230017830 ps
CPU time 0.78 seconds
Started Aug 11 05:35:29 PM PDT 24
Finished Aug 11 05:35:30 PM PDT 24
Peak memory 205248 kb
Host smart-6e5af848-f390-408c-98eb-053d88a44cfd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705338702 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
2705338702
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3011077300
Short name T101
Test name
Test status
Simulation time 459463612 ps
CPU time 6.04 seconds
Started Aug 11 05:35:30 PM PDT 24
Finished Aug 11 05:35:36 PM PDT 24
Peak memory 205636 kb
Host smart-bed7a01f-10a6-459b-8524-b0e8cc2fbb75
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011077300 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.3011077300
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.625449076
Short name T105
Test name
Test status
Simulation time 350581681 ps
CPU time 6.3 seconds
Started Aug 11 05:35:25 PM PDT 24
Finished Aug 11 05:35:31 PM PDT 24
Peak memory 213864 kb
Host smart-7816d46e-3be2-419b-bec9-1cc2bb506233
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625449076 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.625449076
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3961344736
Short name T411
Test name
Test status
Simulation time 2563647337 ps
CPU time 10.72 seconds
Started Aug 11 05:35:28 PM PDT 24
Finished Aug 11 05:35:39 PM PDT 24
Peak memory 213884 kb
Host smart-db9e9ba9-c885-47a3-9f8f-5a414e6a37a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961344736 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.3
961344736
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.2083315979
Short name T70
Test name
Test status
Simulation time 427435209 ps
CPU time 4.19 seconds
Started Aug 11 05:35:36 PM PDT 24
Finished Aug 11 05:35:40 PM PDT 24
Peak memory 219372 kb
Host smart-1300fb5d-d874-4dc2-ba1a-1cd6f816f20d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083315979 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.2083315979
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.3029019610
Short name T361
Test name
Test status
Simulation time 317204607 ps
CPU time 1.42 seconds
Started Aug 11 05:35:33 PM PDT 24
Finished Aug 11 05:35:35 PM PDT 24
Peak memory 213708 kb
Host smart-9031908a-d91f-4e86-ac1b-b4c267261f3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029019610 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.3029019610
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.4141510826
Short name T354
Test name
Test status
Simulation time 33250060240 ps
CPU time 54.18 seconds
Started Aug 11 05:35:31 PM PDT 24
Finished Aug 11 05:36:26 PM PDT 24
Peak memory 205524 kb
Host smart-9737f849-66b3-4cce-a411-b14da079dde1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141510826 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.rv_dm_jtag_dmi_csr_bit_bash.4141510826
Directory /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.133973416
Short name T416
Test name
Test status
Simulation time 4072173185 ps
CPU time 11.44 seconds
Started Aug 11 05:35:29 PM PDT 24
Finished Aug 11 05:35:40 PM PDT 24
Peak memory 205568 kb
Host smart-36a8450b-3387-422a-886a-07cd89f4e325
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133973416 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.133973416
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.702911668
Short name T317
Test name
Test status
Simulation time 205230788 ps
CPU time 0.94 seconds
Started Aug 11 05:35:26 PM PDT 24
Finished Aug 11 05:35:27 PM PDT 24
Peak memory 205224 kb
Host smart-d21930cb-2af5-4f10-861e-4a901d8cb661
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702911668 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.702911668
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.1993084463
Short name T451
Test name
Test status
Simulation time 184158406 ps
CPU time 6.44 seconds
Started Aug 11 05:35:32 PM PDT 24
Finished Aug 11 05:35:39 PM PDT 24
Peak memory 205580 kb
Host smart-eb0d9860-c1ae-493f-ae7c-a126078c891c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993084463 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.1993084463
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.4115214777
Short name T109
Test name
Test status
Simulation time 611814048 ps
CPU time 5.3 seconds
Started Aug 11 05:35:34 PM PDT 24
Finished Aug 11 05:35:39 PM PDT 24
Peak memory 213872 kb
Host smart-110765e3-ebc0-480d-a409-e007129068ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115214777 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.4115214777
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.1125983841
Short name T391
Test name
Test status
Simulation time 264085352 ps
CPU time 2.64 seconds
Started Aug 11 05:35:35 PM PDT 24
Finished Aug 11 05:35:38 PM PDT 24
Peak memory 213912 kb
Host smart-e4f81c83-b1dd-460f-98f3-aed0241b024c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125983841 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.1125983841
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.1437832220
Short name T437
Test name
Test status
Simulation time 159670837 ps
CPU time 2.22 seconds
Started Aug 11 05:35:32 PM PDT 24
Finished Aug 11 05:35:34 PM PDT 24
Peak memory 213568 kb
Host smart-038c0772-7839-402f-9cb1-48bc4bd93855
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437832220 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.1437832220
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.2933387113
Short name T337
Test name
Test status
Simulation time 28673419254 ps
CPU time 31.81 seconds
Started Aug 11 05:35:33 PM PDT 24
Finished Aug 11 05:36:05 PM PDT 24
Peak memory 205548 kb
Host smart-11b2c507-8ca4-4af0-bac1-01304fc0d51c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933387113 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.rv_dm_jtag_dmi_csr_bit_bash.2933387113
Directory /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.4268713730
Short name T434
Test name
Test status
Simulation time 1851865823 ps
CPU time 3.12 seconds
Started Aug 11 05:35:35 PM PDT 24
Finished Aug 11 05:35:38 PM PDT 24
Peak memory 205404 kb
Host smart-9cb220a9-30d8-437d-8239-24c7cf55cd11
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268713730 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
4268713730
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.204275332
Short name T457
Test name
Test status
Simulation time 238871088 ps
CPU time 0.83 seconds
Started Aug 11 05:35:36 PM PDT 24
Finished Aug 11 05:35:37 PM PDT 24
Peak memory 205188 kb
Host smart-1ed2bb94-9982-4564-b003-ce8437d424ce
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204275332 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.204275332
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.4235271205
Short name T460
Test name
Test status
Simulation time 385689775 ps
CPU time 4.42 seconds
Started Aug 11 05:35:31 PM PDT 24
Finished Aug 11 05:35:35 PM PDT 24
Peak memory 205540 kb
Host smart-70167389-92e1-49ef-89c6-0ebdc48dd979
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235271205 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same
_csr_outstanding.4235271205
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.1439719408
Short name T312
Test name
Test status
Simulation time 2403078235 ps
CPU time 6.48 seconds
Started Aug 11 05:35:30 PM PDT 24
Finished Aug 11 05:35:36 PM PDT 24
Peak memory 216724 kb
Host smart-baa0d33d-bf6e-48ce-8619-7d7e450e9d40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439719408 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.1439719408
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.2418588256
Short name T150
Test name
Test status
Simulation time 1325928977 ps
CPU time 10.41 seconds
Started Aug 11 05:35:32 PM PDT 24
Finished Aug 11 05:35:42 PM PDT 24
Peak memory 213856 kb
Host smart-50f3d848-a1a5-47b1-bc69-dc759329d73a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418588256 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.2
418588256
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.2855220888
Short name T333
Test name
Test status
Simulation time 194871237 ps
CPU time 2.34 seconds
Started Aug 11 05:35:35 PM PDT 24
Finished Aug 11 05:35:38 PM PDT 24
Peak memory 213912 kb
Host smart-dc4d26f9-164d-46c4-a2a7-27ad82274559
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855220888 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.2855220888
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.3412244923
Short name T444
Test name
Test status
Simulation time 393625620 ps
CPU time 1.66 seconds
Started Aug 11 05:35:32 PM PDT 24
Finished Aug 11 05:35:34 PM PDT 24
Peak memory 213708 kb
Host smart-a5fc3a60-c726-4e83-8604-b38ae1c71bf9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412244923 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.3412244923
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.3827997660
Short name T397
Test name
Test status
Simulation time 2916208090 ps
CPU time 8.37 seconds
Started Aug 11 05:35:32 PM PDT 24
Finished Aug 11 05:35:40 PM PDT 24
Peak memory 205588 kb
Host smart-870c41ad-ee63-4f8b-917f-0b089dc25514
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827997660 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.rv_dm_jtag_dmi_csr_bit_bash.3827997660
Directory /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.3061640574
Short name T417
Test name
Test status
Simulation time 2899756596 ps
CPU time 6.07 seconds
Started Aug 11 05:35:33 PM PDT 24
Finished Aug 11 05:35:40 PM PDT 24
Peak memory 205572 kb
Host smart-849ea3eb-14fe-411b-a7f6-efd8ae547f78
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061640574 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.
3061640574
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.908908945
Short name T55
Test name
Test status
Simulation time 539817242 ps
CPU time 0.83 seconds
Started Aug 11 05:35:31 PM PDT 24
Finished Aug 11 05:35:32 PM PDT 24
Peak memory 205200 kb
Host smart-2053d195-bf93-4583-aa36-637f0fe02b83
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908908945 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.908908945
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.3779338130
Short name T407
Test name
Test status
Simulation time 505311322 ps
CPU time 6.85 seconds
Started Aug 11 05:35:33 PM PDT 24
Finished Aug 11 05:35:40 PM PDT 24
Peak memory 205584 kb
Host smart-45a6c78a-2226-4e72-b893-df1d9e70decb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779338130 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.3779338130
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.2982838250
Short name T406
Test name
Test status
Simulation time 90377016 ps
CPU time 2.28 seconds
Started Aug 11 05:35:32 PM PDT 24
Finished Aug 11 05:35:35 PM PDT 24
Peak memory 213864 kb
Host smart-dfd82ad8-2443-4c74-9eb7-4ccbbd871f0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982838250 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.2982838250
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.2670605790
Short name T151
Test name
Test status
Simulation time 4818845469 ps
CPU time 21.66 seconds
Started Aug 11 05:35:31 PM PDT 24
Finished Aug 11 05:35:53 PM PDT 24
Peak memory 214168 kb
Host smart-6051c6f9-bb36-4805-86ae-d86fd4d56b7f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670605790 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.2
670605790
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2900840056
Short name T455
Test name
Test status
Simulation time 265489689 ps
CPU time 3.98 seconds
Started Aug 11 05:35:31 PM PDT 24
Finished Aug 11 05:35:35 PM PDT 24
Peak memory 219176 kb
Host smart-a399bd6a-3d52-4459-b543-29d2cccdcb89
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900840056 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.2900840056
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.4283636813
Short name T362
Test name
Test status
Simulation time 220643437 ps
CPU time 2.45 seconds
Started Aug 11 05:35:32 PM PDT 24
Finished Aug 11 05:35:35 PM PDT 24
Peak memory 213804 kb
Host smart-6c05d808-19bc-4ea1-af54-47bb90539ea7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283636813 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.4283636813
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.2187777997
Short name T452
Test name
Test status
Simulation time 27907562376 ps
CPU time 47.85 seconds
Started Aug 11 05:35:32 PM PDT 24
Finished Aug 11 05:36:20 PM PDT 24
Peak memory 205540 kb
Host smart-52a28568-61d1-4618-9c10-00c8c9fc930d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187777997 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.rv_dm_jtag_dmi_csr_bit_bash.2187777997
Directory /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.752584720
Short name T320
Test name
Test status
Simulation time 8015320559 ps
CPU time 12.33 seconds
Started Aug 11 05:35:35 PM PDT 24
Finished Aug 11 05:35:47 PM PDT 24
Peak memory 205580 kb
Host smart-2428ad4b-873a-4c75-9c39-5c2b169cec37
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752584720 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.752584720
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2956240760
Short name T307
Test name
Test status
Simulation time 169451813 ps
CPU time 0.78 seconds
Started Aug 11 05:35:30 PM PDT 24
Finished Aug 11 05:35:31 PM PDT 24
Peak memory 205232 kb
Host smart-ec16ba2f-402e-4cd1-b375-65477b793a41
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956240760 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
2956240760
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.1261464556
Short name T100
Test name
Test status
Simulation time 259384160 ps
CPU time 3.39 seconds
Started Aug 11 05:35:30 PM PDT 24
Finished Aug 11 05:35:34 PM PDT 24
Peak memory 205536 kb
Host smart-dcae24da-675b-4922-9d62-cdd33d533163
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261464556 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.1261464556
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.2886642314
Short name T106
Test name
Test status
Simulation time 387985781 ps
CPU time 2.65 seconds
Started Aug 11 05:35:36 PM PDT 24
Finished Aug 11 05:35:38 PM PDT 24
Peak memory 213824 kb
Host smart-02eedee5-3ece-4878-ae56-04ff2b42d02d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886642314 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.2886642314
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.1746158030
Short name T156
Test name
Test status
Simulation time 1820099208 ps
CPU time 15.69 seconds
Started Aug 11 05:35:32 PM PDT 24
Finished Aug 11 05:35:48 PM PDT 24
Peak memory 213804 kb
Host smart-11005d2b-fd05-4e1a-b529-ad5a22825224
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746158030 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.1
746158030
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.2104045600
Short name T340
Test name
Test status
Simulation time 419735801 ps
CPU time 4.32 seconds
Started Aug 11 05:35:38 PM PDT 24
Finished Aug 11 05:35:43 PM PDT 24
Peak memory 221956 kb
Host smart-b8064400-7501-451d-adfc-65dacbe31884
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104045600 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.2104045600
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.1130552125
Short name T82
Test name
Test status
Simulation time 644850998 ps
CPU time 2.35 seconds
Started Aug 11 05:35:40 PM PDT 24
Finished Aug 11 05:35:42 PM PDT 24
Peak memory 213732 kb
Host smart-e30922cb-a68e-4929-bc22-9d53605acadd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130552125 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.1130552125
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.2766247712
Short name T356
Test name
Test status
Simulation time 10754873195 ps
CPU time 11 seconds
Started Aug 11 05:35:38 PM PDT 24
Finished Aug 11 05:35:50 PM PDT 24
Peak memory 205496 kb
Host smart-7dee7f36-7d1e-4c72-9dcf-2023cdf926ce
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766247712 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.rv_dm_jtag_dmi_csr_bit_bash.2766247712
Directory /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.1880830824
Short name T332
Test name
Test status
Simulation time 1521871719 ps
CPU time 4.82 seconds
Started Aug 11 05:35:40 PM PDT 24
Finished Aug 11 05:35:45 PM PDT 24
Peak memory 205420 kb
Host smart-af367c2d-af11-4d72-910d-d2c226243fe7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880830824 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.
1880830824
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.3243676207
Short name T426
Test name
Test status
Simulation time 187820371 ps
CPU time 0.76 seconds
Started Aug 11 05:35:32 PM PDT 24
Finished Aug 11 05:35:33 PM PDT 24
Peak memory 205224 kb
Host smart-c9eb0aa8-f8c5-4b6d-92d3-ed3a02ce8ee8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243676207 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
3243676207
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.3121174549
Short name T462
Test name
Test status
Simulation time 547136265 ps
CPU time 4.5 seconds
Started Aug 11 05:35:42 PM PDT 24
Finished Aug 11 05:35:47 PM PDT 24
Peak memory 205604 kb
Host smart-d99221a2-8295-4350-a5d8-c0637bd9dbbf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121174549 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.3121174549
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.4215610676
Short name T435
Test name
Test status
Simulation time 332500921 ps
CPU time 3.23 seconds
Started Aug 11 05:35:38 PM PDT 24
Finished Aug 11 05:35:41 PM PDT 24
Peak memory 213896 kb
Host smart-50965c65-d0f7-4ed1-b7ae-cb86935fafc0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215610676 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.4215610676
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.3029746001
Short name T148
Test name
Test status
Simulation time 1704493148 ps
CPU time 17.61 seconds
Started Aug 11 05:35:39 PM PDT 24
Finished Aug 11 05:35:57 PM PDT 24
Peak memory 213776 kb
Host smart-bb0d0204-b441-4710-a9c3-3ba2abdceced
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029746001 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.3
029746001
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.335648629
Short name T436
Test name
Test status
Simulation time 3405095358 ps
CPU time 30.82 seconds
Started Aug 11 05:34:59 PM PDT 24
Finished Aug 11 05:35:30 PM PDT 24
Peak memory 205716 kb
Host smart-3e293a30-1e02-4013-9bb2-eed99f74c459
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335648629 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.rv_dm_csr_aliasing.335648629
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.4184849040
Short name T91
Test name
Test status
Simulation time 1442145730 ps
CPU time 28.5 seconds
Started Aug 11 05:35:05 PM PDT 24
Finished Aug 11 05:35:34 PM PDT 24
Peak memory 213652 kb
Host smart-394184d0-cddf-4866-b351-60dc10e47711
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184849040 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.4184849040
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.2645804754
Short name T353
Test name
Test status
Simulation time 427138046 ps
CPU time 1.81 seconds
Started Aug 11 05:35:06 PM PDT 24
Finished Aug 11 05:35:08 PM PDT 24
Peak memory 213744 kb
Host smart-da9e2dd9-8d99-4538-bfd6-4579fcf0abd2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645804754 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.2645804754
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.302844461
Short name T108
Test name
Test status
Simulation time 120251746 ps
CPU time 2.26 seconds
Started Aug 11 05:35:07 PM PDT 24
Finished Aug 11 05:35:09 PM PDT 24
Peak memory 215748 kb
Host smart-ae85164b-9d5e-4c91-84cb-c0f6d755a6cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302844461 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.302844461
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.414668342
Short name T344
Test name
Test status
Simulation time 258878985 ps
CPU time 2.56 seconds
Started Aug 11 05:35:08 PM PDT 24
Finished Aug 11 05:35:10 PM PDT 24
Peak memory 213680 kb
Host smart-ec15559d-149e-4caa-beb0-773c66ec38d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414668342 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.414668342
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.3297598430
Short name T372
Test name
Test status
Simulation time 17985809957 ps
CPU time 8.05 seconds
Started Aug 11 05:34:57 PM PDT 24
Finished Aug 11 05:35:05 PM PDT 24
Peak memory 205460 kb
Host smart-ba06da61-ea78-4210-b0d1-7b87f3403ed0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297598430 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_aliasing.3297598430
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.869859311
Short name T308
Test name
Test status
Simulation time 70881232423 ps
CPU time 117.1 seconds
Started Aug 11 05:35:03 PM PDT 24
Finished Aug 11 05:37:00 PM PDT 24
Peak memory 205472 kb
Host smart-5c7eca5d-3281-465d-9ce4-0004078dbfd5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869859311 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.r
v_dm_jtag_dmi_csr_bit_bash.869859311
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2755501465
Short name T87
Test name
Test status
Simulation time 10169311274 ps
CPU time 7.98 seconds
Started Aug 11 05:35:03 PM PDT 24
Finished Aug 11 05:35:11 PM PDT 24
Peak memory 205532 kb
Host smart-2f3816b7-33b1-47d3-a058-59df9cdadd54
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755501465 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.2755501465
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.519808304
Short name T382
Test name
Test status
Simulation time 5353273990 ps
CPU time 8.4 seconds
Started Aug 11 05:34:58 PM PDT 24
Finished Aug 11 05:35:06 PM PDT 24
Peak memory 205544 kb
Host smart-0665c6d1-e8fb-4ac6-ac99-0416cdcfb16a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519808304 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.519808304
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.324087221
Short name T368
Test name
Test status
Simulation time 538778591 ps
CPU time 1.97 seconds
Started Aug 11 05:35:00 PM PDT 24
Finished Aug 11 05:35:02 PM PDT 24
Peak memory 205268 kb
Host smart-48449782-2376-4d3d-97bd-01cf4e5c6256
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324087221 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr
_aliasing.324087221
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.2575285860
Short name T343
Test name
Test status
Simulation time 3025130147 ps
CPU time 3.1 seconds
Started Aug 11 05:34:57 PM PDT 24
Finished Aug 11 05:35:00 PM PDT 24
Peak memory 205556 kb
Host smart-1e206fa5-299f-4871-be94-84b065e7c997
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575285860 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_bit_bash.2575285860
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3218993614
Short name T334
Test name
Test status
Simulation time 605378411 ps
CPU time 1.06 seconds
Started Aug 11 05:34:57 PM PDT 24
Finished Aug 11 05:34:58 PM PDT 24
Peak memory 205328 kb
Host smart-a51dd6a5-1229-4acf-b7c0-dcf668504bce
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218993614 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.3218993614
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.1426260293
Short name T315
Test name
Test status
Simulation time 328163624 ps
CPU time 1.51 seconds
Started Aug 11 05:34:57 PM PDT 24
Finished Aug 11 05:34:59 PM PDT 24
Peak memory 205188 kb
Host smart-51de0145-1235-4bec-9ec4-4e0a77524929
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426260293 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.1
426260293
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.1706998869
Short name T327
Test name
Test status
Simulation time 152462798 ps
CPU time 0.82 seconds
Started Aug 11 05:34:58 PM PDT 24
Finished Aug 11 05:34:59 PM PDT 24
Peak memory 205284 kb
Host smart-bb116592-c28b-4a07-80ec-e96aaaaa4912
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706998869 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.1706998869
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.1617665914
Short name T345
Test name
Test status
Simulation time 60279844 ps
CPU time 0.8 seconds
Started Aug 11 05:35:01 PM PDT 24
Finished Aug 11 05:35:02 PM PDT 24
Peak memory 205184 kb
Host smart-4fcb5c19-1747-477b-bdec-16bc1e713f41
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617665914 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.1617665914
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.2841381561
Short name T97
Test name
Test status
Simulation time 260314162 ps
CPU time 3.93 seconds
Started Aug 11 05:35:08 PM PDT 24
Finished Aug 11 05:35:12 PM PDT 24
Peak memory 205492 kb
Host smart-87bc7c86-15a9-4111-a62f-60d07f24cb1a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841381561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.2841381561
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.2924259923
Short name T331
Test name
Test status
Simulation time 43395459917 ps
CPU time 140.7 seconds
Started Aug 11 05:35:06 PM PDT 24
Finished Aug 11 05:37:27 PM PDT 24
Peak memory 222044 kb
Host smart-284a3da6-8c31-49d2-8f61-6a21b99d22a7
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924259923 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.2924259923
Directory /workspace/2.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.2808762834
Short name T314
Test name
Test status
Simulation time 314175759 ps
CPU time 4.44 seconds
Started Aug 11 05:35:01 PM PDT 24
Finished Aug 11 05:35:05 PM PDT 24
Peak memory 213880 kb
Host smart-33c3672f-44f3-4f93-8a18-94e9c46067d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808762834 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.2808762834
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.2789813219
Short name T149
Test name
Test status
Simulation time 2018720557 ps
CPU time 8.85 seconds
Started Aug 11 05:35:00 PM PDT 24
Finished Aug 11 05:35:09 PM PDT 24
Peak memory 213848 kb
Host smart-ccdad96d-6370-42d0-868b-58423b3af839
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789813219 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.2789813219
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.2768711159
Short name T88
Test name
Test status
Simulation time 8346948793 ps
CPU time 79.87 seconds
Started Aug 11 05:35:08 PM PDT 24
Finished Aug 11 05:36:28 PM PDT 24
Peak memory 213884 kb
Host smart-0af16feb-db3d-41f7-940b-7bf0b5f5c846
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768711159 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.2768711159
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.86417171
Short name T78
Test name
Test status
Simulation time 6385434630 ps
CPU time 57.35 seconds
Started Aug 11 05:35:06 PM PDT 24
Finished Aug 11 05:36:04 PM PDT 24
Peak memory 205620 kb
Host smart-d81e17ea-3622-435d-8860-0ae6485d6cd6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86417171 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.86417171
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.2309372314
Short name T76
Test name
Test status
Simulation time 100479898 ps
CPU time 1.71 seconds
Started Aug 11 05:35:06 PM PDT 24
Finished Aug 11 05:35:08 PM PDT 24
Peak memory 213788 kb
Host smart-eec6c4af-e46a-435c-8f5a-66ce9c58fe19
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309372314 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.2309372314
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.2428654667
Short name T375
Test name
Test status
Simulation time 269172838 ps
CPU time 2.4 seconds
Started Aug 11 05:35:07 PM PDT 24
Finished Aug 11 05:35:10 PM PDT 24
Peak memory 218668 kb
Host smart-5edb1989-92ac-40c0-8ed4-3eaa5ac5285b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428654667 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.2428654667
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.2589121114
Short name T98
Test name
Test status
Simulation time 220947201 ps
CPU time 2.4 seconds
Started Aug 11 05:35:06 PM PDT 24
Finished Aug 11 05:35:08 PM PDT 24
Peak memory 213656 kb
Host smart-c7021022-69c0-42f3-ae65-9d35d4dbda4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589121114 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.2589121114
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.1451474914
Short name T305
Test name
Test status
Simulation time 120954425862 ps
CPU time 99.97 seconds
Started Aug 11 05:35:09 PM PDT 24
Finished Aug 11 05:36:49 PM PDT 24
Peak memory 205568 kb
Host smart-64194107-2a61-47c1-8a83-39fb6bd2972e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451474914 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.1451474914
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.152395259
Short name T357
Test name
Test status
Simulation time 158207990 ps
CPU time 0.77 seconds
Started Aug 11 05:35:06 PM PDT 24
Finished Aug 11 05:35:07 PM PDT 24
Peak memory 205212 kb
Host smart-40844e9c-9398-474b-9e69-86fdcdbcc464
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152395259 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.r
v_dm_jtag_dmi_csr_bit_bash.152395259
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.1067854029
Short name T86
Test name
Test status
Simulation time 12833098197 ps
CPU time 12.52 seconds
Started Aug 11 05:35:06 PM PDT 24
Finished Aug 11 05:35:19 PM PDT 24
Peak memory 205668 kb
Host smart-837a4dc0-c7d3-41f8-aac1-2ae98aca6f49
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067854029 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_hw_reset.1067854029
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.4241732416
Short name T355
Test name
Test status
Simulation time 3973711719 ps
CPU time 3.85 seconds
Started Aug 11 05:35:09 PM PDT 24
Finished Aug 11 05:35:13 PM PDT 24
Peak memory 205620 kb
Host smart-1a54a185-b449-4918-be6e-fded9145f200
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241732416 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.4
241732416
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.1127915783
Short name T374
Test name
Test status
Simulation time 1471510907 ps
CPU time 4.11 seconds
Started Aug 11 05:35:07 PM PDT 24
Finished Aug 11 05:35:11 PM PDT 24
Peak memory 205260 kb
Host smart-9193712c-1528-4a7c-991d-69b6369ced3a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127915783 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.1127915783
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2609114
Short name T394
Test name
Test status
Simulation time 12857676286 ps
CPU time 20.87 seconds
Started Aug 11 05:35:06 PM PDT 24
Finished Aug 11 05:35:27 PM PDT 24
Peak memory 205500 kb
Host smart-4c4d4587-4270-4981-9398-20881f3598f8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609114 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_b
it_bash.2609114
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1185036207
Short name T309
Test name
Test status
Simulation time 400254186 ps
CPU time 1.03 seconds
Started Aug 11 05:35:07 PM PDT 24
Finished Aug 11 05:35:08 PM PDT 24
Peak memory 205292 kb
Host smart-a9a22c38-cef7-409e-9557-b76d47cde94e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185036207 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_hw_reset.1185036207
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.1787648157
Short name T56
Test name
Test status
Simulation time 215353197 ps
CPU time 0.85 seconds
Started Aug 11 05:35:04 PM PDT 24
Finished Aug 11 05:35:05 PM PDT 24
Peak memory 205212 kb
Host smart-ffe4b179-9c96-4cf4-8126-3e330ad14343
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787648157 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.1
787648157
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.874184212
Short name T428
Test name
Test status
Simulation time 99195990 ps
CPU time 0.71 seconds
Started Aug 11 05:35:07 PM PDT 24
Finished Aug 11 05:35:08 PM PDT 24
Peak memory 205332 kb
Host smart-022e5783-fdfd-4566-a04b-0cb3d7cb7387
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874184212 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_part
ial_access.874184212
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.2552767441
Short name T313
Test name
Test status
Simulation time 135916111 ps
CPU time 0.71 seconds
Started Aug 11 05:35:05 PM PDT 24
Finished Aug 11 05:35:06 PM PDT 24
Peak memory 205236 kb
Host smart-d8c98bbb-6ab9-42e5-9a8d-f9e67c3a5b95
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552767441 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.2552767441
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.662869672
Short name T103
Test name
Test status
Simulation time 595329975 ps
CPU time 7.63 seconds
Started Aug 11 05:35:06 PM PDT 24
Finished Aug 11 05:35:14 PM PDT 24
Peak memory 205588 kb
Host smart-1b624fc5-3a1f-4fd2-b783-482da3f1fde1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662869672 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_c
sr_outstanding.662869672
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.3654620219
Short name T159
Test name
Test status
Simulation time 52389395298 ps
CPU time 87.43 seconds
Started Aug 11 05:35:05 PM PDT 24
Finished Aug 11 05:36:32 PM PDT 24
Peak memory 222080 kb
Host smart-1cfef541-d897-4f9f-a265-65704caaf5a6
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654620219 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.3654620219
Directory /workspace/3.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.4220338704
Short name T306
Test name
Test status
Simulation time 246174738 ps
CPU time 2.54 seconds
Started Aug 11 05:35:08 PM PDT 24
Finished Aug 11 05:35:11 PM PDT 24
Peak memory 213860 kb
Host smart-c9bde2b5-854e-474f-948c-b9f66d3f9429
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220338704 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.4220338704
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.1433153115
Short name T153
Test name
Test status
Simulation time 2125061830 ps
CPU time 22.47 seconds
Started Aug 11 05:35:05 PM PDT 24
Finished Aug 11 05:35:28 PM PDT 24
Peak memory 213760 kb
Host smart-0684672a-600b-4fb1-9052-6f9c78feae69
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433153115 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.1433153115
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.2909727584
Short name T424
Test name
Test status
Simulation time 19412455931 ps
CPU time 81.91 seconds
Started Aug 11 05:35:03 PM PDT 24
Finished Aug 11 05:36:25 PM PDT 24
Peak memory 213860 kb
Host smart-df4c723c-8878-4984-934b-cb444c91f068
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909727584 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.2909727584
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.1898107454
Short name T92
Test name
Test status
Simulation time 6482501934 ps
CPU time 73.19 seconds
Started Aug 11 05:35:12 PM PDT 24
Finished Aug 11 05:36:25 PM PDT 24
Peak memory 213888 kb
Host smart-a3803a0e-887b-43b6-ac46-9804efe95ef3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898107454 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.1898107454
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.425837444
Short name T351
Test name
Test status
Simulation time 229035074 ps
CPU time 2.14 seconds
Started Aug 11 05:35:11 PM PDT 24
Finished Aug 11 05:35:13 PM PDT 24
Peak memory 213808 kb
Host smart-1f13a3e1-63ec-48b2-85e7-dfec1668995d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425837444 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.425837444
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.63320525
Short name T328
Test name
Test status
Simulation time 406539149 ps
CPU time 3.88 seconds
Started Aug 11 05:35:13 PM PDT 24
Finished Aug 11 05:35:17 PM PDT 24
Peak memory 219420 kb
Host smart-d3d6c358-55c2-48da-bbba-f1107e0a00dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63320525 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.63320525
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.2732149681
Short name T93
Test name
Test status
Simulation time 216090687 ps
CPU time 1.52 seconds
Started Aug 11 05:35:12 PM PDT 24
Finished Aug 11 05:35:13 PM PDT 24
Peak memory 213704 kb
Host smart-b2637eb8-80fa-4661-9882-f2e6a48233c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732149681 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.2732149681
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2427182724
Short name T341
Test name
Test status
Simulation time 177835881115 ps
CPU time 277.79 seconds
Started Aug 11 05:35:12 PM PDT 24
Finished Aug 11 05:39:50 PM PDT 24
Peak memory 208624 kb
Host smart-3b33fdbc-4c2a-4e52-9350-e9d40bad64d7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427182724 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_aliasing.2427182724
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.22976188
Short name T402
Test name
Test status
Simulation time 5532326340 ps
CPU time 17.4 seconds
Started Aug 11 05:35:11 PM PDT 24
Finished Aug 11 05:35:28 PM PDT 24
Peak memory 205464 kb
Host smart-183658e4-28ad-4f96-a995-fbabaa320e93
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22976188 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv
_dm_jtag_dmi_csr_bit_bash.22976188
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.3191728041
Short name T85
Test name
Test status
Simulation time 15035947001 ps
CPU time 9.59 seconds
Started Aug 11 05:35:05 PM PDT 24
Finished Aug 11 05:35:15 PM PDT 24
Peak memory 205572 kb
Host smart-e92ee3f5-40f1-4d4e-957d-13ef61d3269f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191728041 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.3191728041
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.566088522
Short name T399
Test name
Test status
Simulation time 2992393512 ps
CPU time 2.91 seconds
Started Aug 11 05:35:12 PM PDT 24
Finished Aug 11 05:35:15 PM PDT 24
Peak memory 205600 kb
Host smart-5d4819b3-d632-49a5-b39e-e63245526cc6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566088522 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.566088522
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.3730134076
Short name T329
Test name
Test status
Simulation time 805021219 ps
CPU time 1.44 seconds
Started Aug 11 05:35:07 PM PDT 24
Finished Aug 11 05:35:09 PM PDT 24
Peak memory 205240 kb
Host smart-e315cffe-b3a9-4b98-bd48-d3283910941d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730134076 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_aliasing.3730134076
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.1571963341
Short name T396
Test name
Test status
Simulation time 4523520898 ps
CPU time 12.9 seconds
Started Aug 11 05:35:06 PM PDT 24
Finished Aug 11 05:35:19 PM PDT 24
Peak memory 205532 kb
Host smart-1586a1dd-3b49-4d50-b1e5-0ef78ffd44d1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571963341 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.1571963341
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2397556692
Short name T352
Test name
Test status
Simulation time 258682838 ps
CPU time 0.91 seconds
Started Aug 11 05:35:07 PM PDT 24
Finished Aug 11 05:35:08 PM PDT 24
Peak memory 205288 kb
Host smart-3dc855e3-3467-4365-a9c9-120745dc6ffb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397556692 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.2397556692
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2217308036
Short name T54
Test name
Test status
Simulation time 184741752 ps
CPU time 0.74 seconds
Started Aug 11 05:35:07 PM PDT 24
Finished Aug 11 05:35:08 PM PDT 24
Peak memory 205324 kb
Host smart-5bba6675-62e8-43b2-8208-5499f6198d4d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217308036 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.2
217308036
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.3273224107
Short name T360
Test name
Test status
Simulation time 124129984 ps
CPU time 0.77 seconds
Started Aug 11 05:35:12 PM PDT 24
Finished Aug 11 05:35:13 PM PDT 24
Peak memory 205392 kb
Host smart-1efe4e0d-2d4b-4846-aa04-6e4ba39ae601
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273224107 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.3273224107
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.376550473
Short name T418
Test name
Test status
Simulation time 47713983 ps
CPU time 0.68 seconds
Started Aug 11 05:35:12 PM PDT 24
Finished Aug 11 05:35:13 PM PDT 24
Peak memory 205204 kb
Host smart-ebdc7564-d336-472e-bc69-3a41105fa141
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376550473 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.376550473
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.567832710
Short name T102
Test name
Test status
Simulation time 1322715452 ps
CPU time 4.72 seconds
Started Aug 11 05:35:12 PM PDT 24
Finished Aug 11 05:35:17 PM PDT 24
Peak memory 205608 kb
Host smart-6c0c78e1-c45e-4328-93ff-0b6a0c8bd53e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567832710 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_c
sr_outstanding.567832710
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.3430911448
Short name T445
Test name
Test status
Simulation time 218866473 ps
CPU time 3.89 seconds
Started Aug 11 05:35:11 PM PDT 24
Finished Aug 11 05:35:15 PM PDT 24
Peak memory 213776 kb
Host smart-faf1b08c-a026-473c-9df7-d3abf6964650
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430911448 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.3430911448
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.2273259837
Short name T412
Test name
Test status
Simulation time 1560740585 ps
CPU time 11.54 seconds
Started Aug 11 05:35:13 PM PDT 24
Finished Aug 11 05:35:25 PM PDT 24
Peak memory 213768 kb
Host smart-cea7b8c3-0818-4f99-8580-b474f3c3fd4d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273259837 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.2273259837
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.2474223887
Short name T385
Test name
Test status
Simulation time 835990223 ps
CPU time 4.05 seconds
Started Aug 11 05:35:12 PM PDT 24
Finished Aug 11 05:35:16 PM PDT 24
Peak memory 217400 kb
Host smart-12cde652-f37a-4192-b5e1-39ddf3407228
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474223887 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.2474223887
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.2471197258
Short name T405
Test name
Test status
Simulation time 45684935019 ps
CPU time 33.28 seconds
Started Aug 11 05:35:12 PM PDT 24
Finished Aug 11 05:35:45 PM PDT 24
Peak memory 205528 kb
Host smart-c2693114-c990-48f3-8b5a-79d777547ad3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471197258 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
rv_dm_jtag_dmi_csr_bit_bash.2471197258
Directory /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.593952162
Short name T325
Test name
Test status
Simulation time 10156929544 ps
CPU time 21.85 seconds
Started Aug 11 05:35:13 PM PDT 24
Finished Aug 11 05:35:35 PM PDT 24
Peak memory 205544 kb
Host smart-88bb256c-1136-463c-b831-b36a608288ca
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593952162 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.593952162
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.3787458252
Short name T409
Test name
Test status
Simulation time 166676516 ps
CPU time 1.12 seconds
Started Aug 11 05:35:13 PM PDT 24
Finished Aug 11 05:35:14 PM PDT 24
Peak memory 205256 kb
Host smart-ca543d46-9fb2-4352-8911-ae859a7d04cf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787458252 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.3
787458252
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.2420907436
Short name T453
Test name
Test status
Simulation time 346695735 ps
CPU time 6.83 seconds
Started Aug 11 05:35:14 PM PDT 24
Finished Aug 11 05:35:21 PM PDT 24
Peak memory 205552 kb
Host smart-80889666-5a9e-4eb5-a78a-32ebacbfe005
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420907436 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.2420907436
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.829229623
Short name T438
Test name
Test status
Simulation time 67592898832 ps
CPU time 59.07 seconds
Started Aug 11 05:35:14 PM PDT 24
Finished Aug 11 05:36:13 PM PDT 24
Peak memory 222784 kb
Host smart-11e67837-f63d-46ab-bb52-b441fc97566b
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829229623 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.829229623
Directory /workspace/5.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.153727251
Short name T378
Test name
Test status
Simulation time 261389852 ps
CPU time 5.04 seconds
Started Aug 11 05:35:10 PM PDT 24
Finished Aug 11 05:35:16 PM PDT 24
Peak memory 213876 kb
Host smart-4e68a259-f1ae-47c6-b79a-7ee24ceaa6a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153727251 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.153727251
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.2442060013
Short name T400
Test name
Test status
Simulation time 2896497523 ps
CPU time 16.26 seconds
Started Aug 11 05:35:12 PM PDT 24
Finished Aug 11 05:35:28 PM PDT 24
Peak memory 213940 kb
Host smart-6b71a227-1a5b-4a7c-a6e0-ebc91eb3bf21
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442060013 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.2442060013
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.4090010056
Short name T404
Test name
Test status
Simulation time 458683229 ps
CPU time 4.76 seconds
Started Aug 11 05:35:21 PM PDT 24
Finished Aug 11 05:35:26 PM PDT 24
Peak memory 220064 kb
Host smart-f4bdd648-7923-43dc-970a-fc789d1c6d22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090010056 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.4090010056
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.2345567653
Short name T81
Test name
Test status
Simulation time 82892783 ps
CPU time 1.64 seconds
Started Aug 11 05:35:11 PM PDT 24
Finished Aug 11 05:35:13 PM PDT 24
Peak memory 213756 kb
Host smart-8203b37f-a604-45fa-a450-9695ce72f91f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345567653 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.2345567653
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.421780522
Short name T348
Test name
Test status
Simulation time 21798877847 ps
CPU time 15.12 seconds
Started Aug 11 05:35:11 PM PDT 24
Finished Aug 11 05:35:27 PM PDT 24
Peak memory 205600 kb
Host smart-e5ddbd8f-56a3-44e4-baee-277458621089
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421780522 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.r
v_dm_jtag_dmi_csr_bit_bash.421780522
Directory /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.1063321003
Short name T447
Test name
Test status
Simulation time 1091058858 ps
CPU time 4.17 seconds
Started Aug 11 05:35:11 PM PDT 24
Finished Aug 11 05:35:15 PM PDT 24
Peak memory 205412 kb
Host smart-682142cc-b478-449e-8ec7-9949f034253c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063321003 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.1
063321003
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.3272875822
Short name T310
Test name
Test status
Simulation time 973884101 ps
CPU time 1.95 seconds
Started Aug 11 05:35:16 PM PDT 24
Finished Aug 11 05:35:18 PM PDT 24
Peak memory 205244 kb
Host smart-afa288bb-27a7-4869-be45-89a39b40b23e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272875822 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.3
272875822
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.3241340862
Short name T440
Test name
Test status
Simulation time 337098962 ps
CPU time 4.68 seconds
Started Aug 11 05:35:20 PM PDT 24
Finished Aug 11 05:35:25 PM PDT 24
Peak memory 205620 kb
Host smart-c5dbfa45-8216-40aa-ab9f-6d8ac52afaad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241340862 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.3241340862
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.3958851069
Short name T52
Test name
Test status
Simulation time 24410805480 ps
CPU time 21.11 seconds
Started Aug 11 05:35:18 PM PDT 24
Finished Aug 11 05:35:39 PM PDT 24
Peak memory 221888 kb
Host smart-966e8d6e-2513-4db6-9644-cd3911111b60
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958851069 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.3958851069
Directory /workspace/6.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.551626562
Short name T365
Test name
Test status
Simulation time 80274298 ps
CPU time 3.61 seconds
Started Aug 11 05:35:15 PM PDT 24
Finished Aug 11 05:35:19 PM PDT 24
Peak memory 213856 kb
Host smart-ee4c5e42-c236-4e56-abec-4cbb888088fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551626562 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.551626562
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.2505108516
Short name T388
Test name
Test status
Simulation time 1090113685 ps
CPU time 8.68 seconds
Started Aug 11 05:35:16 PM PDT 24
Finished Aug 11 05:35:25 PM PDT 24
Peak memory 213760 kb
Host smart-c220e670-4de3-4014-9b4f-6d69e04497af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505108516 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.2505108516
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.1711216910
Short name T458
Test name
Test status
Simulation time 197517329 ps
CPU time 2.79 seconds
Started Aug 11 05:35:20 PM PDT 24
Finished Aug 11 05:35:23 PM PDT 24
Peak memory 213920 kb
Host smart-66dabe87-8f63-4578-965e-8c55cc83ec20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711216910 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.1711216910
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.376249129
Short name T413
Test name
Test status
Simulation time 137607922 ps
CPU time 2.35 seconds
Started Aug 11 05:35:22 PM PDT 24
Finished Aug 11 05:35:25 PM PDT 24
Peak memory 213828 kb
Host smart-95cee0e0-e518-49c8-9a33-46360f15bc0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376249129 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.376249129
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.2280368103
Short name T304
Test name
Test status
Simulation time 27114790675 ps
CPU time 49.87 seconds
Started Aug 11 05:35:19 PM PDT 24
Finished Aug 11 05:36:09 PM PDT 24
Peak memory 205544 kb
Host smart-703ae52e-8881-4f54-acff-2fe794dd9ada
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280368103 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
rv_dm_jtag_dmi_csr_bit_bash.2280368103
Directory /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.2660243038
Short name T442
Test name
Test status
Simulation time 12589326298 ps
CPU time 9.44 seconds
Started Aug 11 05:35:20 PM PDT 24
Finished Aug 11 05:35:30 PM PDT 24
Peak memory 205584 kb
Host smart-57c393be-f395-48d7-8ca5-3924e836ea90
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660243038 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.2
660243038
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.3544365994
Short name T358
Test name
Test status
Simulation time 322716703 ps
CPU time 0.81 seconds
Started Aug 11 05:35:24 PM PDT 24
Finished Aug 11 05:35:25 PM PDT 24
Peak memory 205184 kb
Host smart-14e477ea-8404-43e5-bb2c-0c452d4958e7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544365994 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.3
544365994
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.3781522364
Short name T104
Test name
Test status
Simulation time 335403836 ps
CPU time 4.49 seconds
Started Aug 11 05:35:19 PM PDT 24
Finished Aug 11 05:35:24 PM PDT 24
Peak memory 205592 kb
Host smart-3624be7c-28c3-4eab-9d1a-e6e00809ea10
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781522364 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.3781522364
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.4025834446
Short name T392
Test name
Test status
Simulation time 26230024821 ps
CPU time 181.48 seconds
Started Aug 11 05:35:22 PM PDT 24
Finished Aug 11 05:38:24 PM PDT 24
Peak memory 221728 kb
Host smart-f3d0c9f1-9d68-469c-ada1-6579c97540d0
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025834446 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.4025834446
Directory /workspace/7.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.3370537644
Short name T364
Test name
Test status
Simulation time 256058774 ps
CPU time 2.93 seconds
Started Aug 11 05:35:19 PM PDT 24
Finished Aug 11 05:35:23 PM PDT 24
Peak memory 213720 kb
Host smart-9a0e6517-8e63-4394-b40f-4d9717235f0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370537644 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.3370537644
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.2837696734
Short name T316
Test name
Test status
Simulation time 357742424 ps
CPU time 4.22 seconds
Started Aug 11 05:35:20 PM PDT 24
Finished Aug 11 05:35:24 PM PDT 24
Peak memory 219400 kb
Host smart-ae557cab-bd66-476b-bb86-466f94e5899f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837696734 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.2837696734
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.1336088860
Short name T90
Test name
Test status
Simulation time 221967576 ps
CPU time 2.32 seconds
Started Aug 11 05:35:19 PM PDT 24
Finished Aug 11 05:35:21 PM PDT 24
Peak memory 213716 kb
Host smart-1e8ebfd9-7e67-4999-ba80-145f29ff299b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336088860 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.1336088860
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.478568674
Short name T342
Test name
Test status
Simulation time 14205995355 ps
CPU time 8.85 seconds
Started Aug 11 05:35:20 PM PDT 24
Finished Aug 11 05:35:29 PM PDT 24
Peak memory 205572 kb
Host smart-b71d02e8-35bf-424d-b601-9e46db7f88dc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478568674 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.r
v_dm_jtag_dmi_csr_bit_bash.478568674
Directory /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.3596473217
Short name T433
Test name
Test status
Simulation time 1190247889 ps
CPU time 2.57 seconds
Started Aug 11 05:35:20 PM PDT 24
Finished Aug 11 05:35:23 PM PDT 24
Peak memory 205436 kb
Host smart-643c9248-305b-4df7-a5fc-1a556fbb16ab
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596473217 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.3
596473217
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2420163526
Short name T370
Test name
Test status
Simulation time 936063848 ps
CPU time 2.82 seconds
Started Aug 11 05:35:23 PM PDT 24
Finished Aug 11 05:35:26 PM PDT 24
Peak memory 205188 kb
Host smart-32385b67-6431-4ebb-9c1a-aa33f6cdcc6d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420163526 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.2
420163526
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.594461755
Short name T463
Test name
Test status
Simulation time 1009300551 ps
CPU time 3.6 seconds
Started Aug 11 05:35:20 PM PDT 24
Finished Aug 11 05:35:24 PM PDT 24
Peak memory 205556 kb
Host smart-2c94673b-e730-4249-9d3a-40999fa2547c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594461755 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_c
sr_outstanding.594461755
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.4221686949
Short name T330
Test name
Test status
Simulation time 84965042861 ps
CPU time 159.34 seconds
Started Aug 11 05:35:19 PM PDT 24
Finished Aug 11 05:37:58 PM PDT 24
Peak memory 222120 kb
Host smart-1e926463-f143-4d08-a802-23500f4275e0
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221686949 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.4221686949
Directory /workspace/8.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.313978983
Short name T323
Test name
Test status
Simulation time 237962816 ps
CPU time 5.26 seconds
Started Aug 11 05:35:21 PM PDT 24
Finished Aug 11 05:35:27 PM PDT 24
Peak memory 213804 kb
Host smart-141b8a08-7d8c-4049-ac76-770894c54157
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313978983 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.313978983
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3880342300
Short name T393
Test name
Test status
Simulation time 11010407594 ps
CPU time 10.31 seconds
Started Aug 11 05:35:21 PM PDT 24
Finished Aug 11 05:35:32 PM PDT 24
Peak memory 213896 kb
Host smart-dbbe42dc-19fb-488b-b85e-2319eb15d502
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880342300 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.3880342300
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.1116891911
Short name T450
Test name
Test status
Simulation time 284441083 ps
CPU time 3.8 seconds
Started Aug 11 05:35:25 PM PDT 24
Finished Aug 11 05:35:28 PM PDT 24
Peak memory 221724 kb
Host smart-aed6e183-f16d-427a-a254-82630a46b7ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116891911 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.1116891911
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1156173188
Short name T79
Test name
Test status
Simulation time 47307261 ps
CPU time 1.54 seconds
Started Aug 11 05:35:18 PM PDT 24
Finished Aug 11 05:35:20 PM PDT 24
Peak memory 213956 kb
Host smart-cf442856-9485-4040-85a9-52e4af0b817b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156173188 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.1156173188
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.3710590661
Short name T430
Test name
Test status
Simulation time 4229396836 ps
CPU time 4.22 seconds
Started Aug 11 05:35:19 PM PDT 24
Finished Aug 11 05:35:24 PM PDT 24
Peak memory 205540 kb
Host smart-83b3301f-44dc-4078-a3ed-eea130544f2c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710590661 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
rv_dm_jtag_dmi_csr_bit_bash.3710590661
Directory /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.4034142936
Short name T311
Test name
Test status
Simulation time 5789033240 ps
CPU time 3.13 seconds
Started Aug 11 05:35:25 PM PDT 24
Finished Aug 11 05:35:28 PM PDT 24
Peak memory 205528 kb
Host smart-a4f5f5f4-2c1a-4ef4-8494-54c4d5075939
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034142936 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.4
034142936
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.2255303445
Short name T387
Test name
Test status
Simulation time 403124288 ps
CPU time 0.81 seconds
Started Aug 11 05:35:19 PM PDT 24
Finished Aug 11 05:35:20 PM PDT 24
Peak memory 205232 kb
Host smart-978ee073-72de-4dd3-b5b5-a4c6b0d8209c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255303445 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.2
255303445
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.458884340
Short name T74
Test name
Test status
Simulation time 614752108 ps
CPU time 4.29 seconds
Started Aug 11 05:35:18 PM PDT 24
Finished Aug 11 05:35:22 PM PDT 24
Peak memory 205604 kb
Host smart-2acc0b2e-c3eb-4360-bb88-817face2003d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458884340 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_c
sr_outstanding.458884340
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.2192234905
Short name T160
Test name
Test status
Simulation time 32581195822 ps
CPU time 34.1 seconds
Started Aug 11 05:35:19 PM PDT 24
Finished Aug 11 05:35:54 PM PDT 24
Peak memory 222104 kb
Host smart-7f990eb9-3da7-48a5-9909-802f9eabee7a
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192234905 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.2192234905
Directory /workspace/9.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.475028122
Short name T401
Test name
Test status
Simulation time 153379858 ps
CPU time 3.12 seconds
Started Aug 11 05:35:25 PM PDT 24
Finished Aug 11 05:35:28 PM PDT 24
Peak memory 213800 kb
Host smart-a638e36f-0e67-497b-9e5c-4c343bd8be99
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475028122 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.475028122
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.3389445079
Short name T152
Test name
Test status
Simulation time 2362319676 ps
CPU time 16.24 seconds
Started Aug 11 05:35:21 PM PDT 24
Finished Aug 11 05:35:38 PM PDT 24
Peak memory 213912 kb
Host smart-aeb0aa7f-489a-4c79-aebb-d4a2030a4e7c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389445079 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.3389445079
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.721650327
Short name T197
Test name
Test status
Simulation time 147117301 ps
CPU time 0.82 seconds
Started Aug 11 05:35:54 PM PDT 24
Finished Aug 11 05:35:55 PM PDT 24
Peak memory 205208 kb
Host smart-a1b88aa3-c571-4d9f-b45e-a2107c4490c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721650327 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.721650327
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.3936540530
Short name T125
Test name
Test status
Simulation time 65346264979 ps
CPU time 145.74 seconds
Started Aug 11 05:35:57 PM PDT 24
Finished Aug 11 05:38:23 PM PDT 24
Peak memory 213872 kb
Host smart-484d9822-7497-40f6-a3a7-cf6a7186a0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936540530 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.3936540530
Directory /workspace/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.2493379840
Short name T282
Test name
Test status
Simulation time 3001191629 ps
CPU time 9.04 seconds
Started Aug 11 05:35:54 PM PDT 24
Finished Aug 11 05:36:03 PM PDT 24
Peak memory 214912 kb
Host smart-094cc815-8056-4c88-b5ce-fde6a9e27b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493379840 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.2493379840
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.77272349
Short name T232
Test name
Test status
Simulation time 1326994343 ps
CPU time 4.21 seconds
Started Aug 11 05:35:53 PM PDT 24
Finished Aug 11 05:35:57 PM PDT 24
Peak memory 205212 kb
Host smart-0a74cc64-ae63-408a-8b3f-c4dbf3c933fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77272349 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.77272349
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.2769907583
Short name T286
Test name
Test status
Simulation time 373977886 ps
CPU time 1.63 seconds
Started Aug 11 05:35:55 PM PDT 24
Finished Aug 11 05:35:56 PM PDT 24
Peak memory 205212 kb
Host smart-8e2871ae-6913-4ce5-b0a1-79649bdc0b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769907583 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.2769907583
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.1630129088
Short name T258
Test name
Test status
Simulation time 135435676 ps
CPU time 0.74 seconds
Started Aug 11 05:35:55 PM PDT 24
Finished Aug 11 05:35:56 PM PDT 24
Peak memory 205208 kb
Host smart-973d5639-51b0-4c88-89a3-c56704d775fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630129088 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.1630129088
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_debug_disabled.1935811222
Short name T112
Test name
Test status
Simulation time 76137723 ps
CPU time 0.88 seconds
Started Aug 11 05:35:54 PM PDT 24
Finished Aug 11 05:35:55 PM PDT 24
Peak memory 215548 kb
Host smart-01da7abe-3c24-4e84-8454-5728d2f2d005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935811222 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.1935811222
Directory /workspace/0.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.312913604
Short name T175
Test name
Test status
Simulation time 2995741866 ps
CPU time 5.39 seconds
Started Aug 11 05:35:54 PM PDT 24
Finished Aug 11 05:35:59 PM PDT 24
Peak memory 213824 kb
Host smart-b4b9c56c-1388-4274-b9c1-a52bd8a43f54
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=312913604 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_tl
_access.312913604
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.3753974971
Short name T277
Test name
Test status
Simulation time 616266401 ps
CPU time 0.94 seconds
Started Aug 11 05:35:53 PM PDT 24
Finished Aug 11 05:35:54 PM PDT 24
Peak memory 205116 kb
Host smart-ac2ad454-2890-4535-a501-8cda627eb10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753974971 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.3753974971
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.1177776762
Short name T269
Test name
Test status
Simulation time 323396893 ps
CPU time 0.96 seconds
Started Aug 11 05:35:52 PM PDT 24
Finished Aug 11 05:35:53 PM PDT 24
Peak memory 205080 kb
Host smart-03fac880-8da4-4510-aceb-2c6a043393ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177776762 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.1177776762
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.1121556000
Short name T73
Test name
Test status
Simulation time 699567228 ps
CPU time 2.5 seconds
Started Aug 11 05:35:54 PM PDT 24
Finished Aug 11 05:35:57 PM PDT 24
Peak memory 205192 kb
Host smart-bd39d4da-dd1a-4847-be12-81c5332df806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121556000 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.1121556000
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.1112748112
Short name T298
Test name
Test status
Simulation time 435428814 ps
CPU time 1.47 seconds
Started Aug 11 05:35:55 PM PDT 24
Finished Aug 11 05:35:56 PM PDT 24
Peak memory 205108 kb
Host smart-5ae40234-4525-4908-a506-b5fbe59378cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112748112 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.1112748112
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.3402029678
Short name T252
Test name
Test status
Simulation time 208305355 ps
CPU time 0.88 seconds
Started Aug 11 05:35:57 PM PDT 24
Finished Aug 11 05:35:58 PM PDT 24
Peak memory 205236 kb
Host smart-1319dcf9-20a8-4610-aee8-1c3b79402c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402029678 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.3402029678
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.3437416972
Short name T247
Test name
Test status
Simulation time 670253072 ps
CPU time 1.29 seconds
Started Aug 11 05:35:54 PM PDT 24
Finished Aug 11 05:35:56 PM PDT 24
Peak memory 204892 kb
Host smart-ed800912-9345-426f-a58c-9756e0e0710b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437416972 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.3437416972
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.1471710554
Short name T208
Test name
Test status
Simulation time 204047355 ps
CPU time 0.95 seconds
Started Aug 11 05:35:56 PM PDT 24
Finished Aug 11 05:35:57 PM PDT 24
Peak memory 205172 kb
Host smart-7ccaadec-aebb-400f-9c29-b0a8aa7cef08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471710554 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.1471710554
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.436991304
Short name T202
Test name
Test status
Simulation time 703455229 ps
CPU time 2.46 seconds
Started Aug 11 05:35:56 PM PDT 24
Finished Aug 11 05:35:58 PM PDT 24
Peak memory 205300 kb
Host smart-ed98c5d1-32ab-44ec-8f60-8ba1a8bdc7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436991304 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.436991304
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.2115822249
Short name T61
Test name
Test status
Simulation time 266747060 ps
CPU time 1.11 seconds
Started Aug 11 05:35:53 PM PDT 24
Finished Aug 11 05:35:54 PM PDT 24
Peak memory 213452 kb
Host smart-5e61d98f-2c6e-4187-a803-f3a14708e95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115822249 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.2115822249
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.1244597627
Short name T289
Test name
Test status
Simulation time 565836040 ps
CPU time 1.39 seconds
Started Aug 11 05:35:53 PM PDT 24
Finished Aug 11 05:35:55 PM PDT 24
Peak memory 205208 kb
Host smart-7e281350-eaca-41cd-b329-75a549332f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244597627 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.1244597627
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/0.rv_dm_sba_debug_disabled.4139147163
Short name T113
Test name
Test status
Simulation time 1009226003 ps
CPU time 2.48 seconds
Started Aug 11 05:35:55 PM PDT 24
Finished Aug 11 05:35:58 PM PDT 24
Peak memory 205324 kb
Host smart-f5dd0320-9bb2-4df8-8060-50344da60ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139147163 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.4139147163
Directory /workspace/0.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.812576553
Short name T227
Test name
Test status
Simulation time 17427411138 ps
CPU time 11.16 seconds
Started Aug 11 05:35:46 PM PDT 24
Finished Aug 11 05:35:57 PM PDT 24
Peak memory 221944 kb
Host smart-230afb59-a553-440f-b068-239e2fd5d017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812576553 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.812576553
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.3773470129
Short name T44
Test name
Test status
Simulation time 924716866 ps
CPU time 2.27 seconds
Started Aug 11 05:35:56 PM PDT 24
Finished Aug 11 05:35:58 PM PDT 24
Peak memory 229448 kb
Host smart-7da57d2b-82a4-431d-8004-5ba44ae91396
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773470129 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.3773470129
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.35885586
Short name T291
Test name
Test status
Simulation time 1269082833 ps
CPU time 2.44 seconds
Started Aug 11 05:35:48 PM PDT 24
Finished Aug 11 05:35:51 PM PDT 24
Peak memory 205364 kb
Host smart-d0ba3239-fd81-4bda-8b1b-6c451a0b79f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35885586 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.35885586
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/1.rv_dm_abstractcmd_status.544845632
Short name T37
Test name
Test status
Simulation time 155408555 ps
CPU time 0.86 seconds
Started Aug 11 05:36:02 PM PDT 24
Finished Aug 11 05:36:03 PM PDT 24
Peak memory 205164 kb
Host smart-c61b5247-94dc-4a6d-9bde-6e32d8f42b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544845632 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.544845632
Directory /workspace/1.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.1095115553
Short name T241
Test name
Test status
Simulation time 82892438 ps
CPU time 0.81 seconds
Started Aug 11 05:36:04 PM PDT 24
Finished Aug 11 05:36:05 PM PDT 24
Peak memory 205212 kb
Host smart-26d77405-56a8-4d46-ad1f-31dd43cad00a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095115553 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.1095115553
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.1446905827
Short name T169
Test name
Test status
Simulation time 8516469375 ps
CPU time 11.35 seconds
Started Aug 11 05:36:02 PM PDT 24
Finished Aug 11 05:36:13 PM PDT 24
Peak memory 213800 kb
Host smart-a14564b4-554e-4bf5-9e69-76b7eb827fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446905827 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.1446905827
Directory /workspace/1.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.696514104
Short name T259
Test name
Test status
Simulation time 2074977635 ps
CPU time 1.9 seconds
Started Aug 11 05:36:04 PM PDT 24
Finished Aug 11 05:36:06 PM PDT 24
Peak memory 213824 kb
Host smart-79c5a342-d9e1-40d1-922d-8ac2546eb3b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696514104 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.696514104
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.1636986883
Short name T16
Test name
Test status
Simulation time 1283741843 ps
CPU time 2.54 seconds
Started Aug 11 05:36:03 PM PDT 24
Finished Aug 11 05:36:06 PM PDT 24
Peak memory 205288 kb
Host smart-ac015cf7-4f0b-4ae2-8c92-2ad25b911e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636986883 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.1636986883
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.24389335
Short name T3
Test name
Test status
Simulation time 116706140 ps
CPU time 1.05 seconds
Started Aug 11 05:36:05 PM PDT 24
Finished Aug 11 05:36:06 PM PDT 24
Peak memory 205184 kb
Host smart-5aeb6c9a-28a1-43d8-a5ef-a22e4b7a0f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24389335 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.24389335
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.986427364
Short name T30
Test name
Test status
Simulation time 273117278 ps
CPU time 0.83 seconds
Started Aug 11 05:36:02 PM PDT 24
Finished Aug 11 05:36:03 PM PDT 24
Peak memory 205176 kb
Host smart-1f6f1d57-1201-4bf7-aec9-3da8db7bc362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986427364 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.986427364
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.3546844865
Short name T186
Test name
Test status
Simulation time 207302058 ps
CPU time 0.83 seconds
Started Aug 11 05:36:02 PM PDT 24
Finished Aug 11 05:36:03 PM PDT 24
Peak memory 205476 kb
Host smart-d1960949-dcde-4e69-981e-72ce9e79dc9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546844865 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.3546844865
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.480882808
Short name T60
Test name
Test status
Simulation time 283272115 ps
CPU time 0.8 seconds
Started Aug 11 05:36:01 PM PDT 24
Finished Aug 11 05:36:02 PM PDT 24
Peak memory 205220 kb
Host smart-606cf394-dde2-4711-97f3-91b71dee14e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480882808 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.480882808
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_debug_disabled.1560306566
Short name T211
Test name
Test status
Simulation time 138145368 ps
CPU time 1.16 seconds
Started Aug 11 05:36:01 PM PDT 24
Finished Aug 11 05:36:02 PM PDT 24
Peak memory 215488 kb
Host smart-296f2d11-acd1-4d3c-8010-98bd437464dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560306566 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.1560306566
Directory /workspace/1.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.2159174443
Short name T264
Test name
Test status
Simulation time 2183821937 ps
CPU time 6.64 seconds
Started Aug 11 05:36:01 PM PDT 24
Finished Aug 11 05:36:08 PM PDT 24
Peak memory 213988 kb
Host smart-76d94561-7bfb-488e-a6b5-b605c2650c91
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2159174443 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t
l_access.2159174443
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.3412883265
Short name T35
Test name
Test status
Simulation time 941119038 ps
CPU time 1.32 seconds
Started Aug 11 05:36:02 PM PDT 24
Finished Aug 11 05:36:04 PM PDT 24
Peak memory 205196 kb
Host smart-9e3c48dd-fdde-40d8-9fce-70d20b122299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412883265 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.3412883265
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.2477993474
Short name T218
Test name
Test status
Simulation time 391375838 ps
CPU time 1.69 seconds
Started Aug 11 05:36:01 PM PDT 24
Finished Aug 11 05:36:03 PM PDT 24
Peak memory 205204 kb
Host smart-4f78b458-439f-4d76-96ae-22a491ab816f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477993474 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.2477993474
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.1928191670
Short name T117
Test name
Test status
Simulation time 285669420 ps
CPU time 0.7 seconds
Started Aug 11 05:36:02 PM PDT 24
Finished Aug 11 05:36:03 PM PDT 24
Peak memory 205160 kb
Host smart-ca6afd4a-bac0-4d7d-86bc-515f9f693edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928191670 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.1928191670
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.727550082
Short name T285
Test name
Test status
Simulation time 367586230 ps
CPU time 1.54 seconds
Started Aug 11 05:36:01 PM PDT 24
Finished Aug 11 05:36:03 PM PDT 24
Peak memory 205024 kb
Host smart-55c24e10-e2b7-4b86-b19b-a2dd22164405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727550082 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.727550082
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.1073923107
Short name T228
Test name
Test status
Simulation time 723874131 ps
CPU time 1.73 seconds
Started Aug 11 05:35:59 PM PDT 24
Finished Aug 11 05:36:01 PM PDT 24
Peak memory 205256 kb
Host smart-52a9ed0f-235a-4c6c-9318-be130acc21fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073923107 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.1073923107
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.2448669519
Short name T280
Test name
Test status
Simulation time 331954266 ps
CPU time 1.51 seconds
Started Aug 11 05:36:05 PM PDT 24
Finished Aug 11 05:36:06 PM PDT 24
Peak memory 205180 kb
Host smart-13a819c1-a671-4ca7-b9a2-dfaef207a35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448669519 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.2448669519
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.1466521171
Short name T236
Test name
Test status
Simulation time 116958515 ps
CPU time 0.76 seconds
Started Aug 11 05:36:05 PM PDT 24
Finished Aug 11 05:36:06 PM PDT 24
Peak memory 205212 kb
Host smart-9ed8e516-a399-4f82-af53-f264f858830c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466521171 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.1466521171
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.1638720274
Short name T162
Test name
Test status
Simulation time 514909851 ps
CPU time 1.49 seconds
Started Aug 11 05:36:05 PM PDT 24
Finished Aug 11 05:36:06 PM PDT 24
Peak memory 205300 kb
Host smart-432ae257-0684-4bb6-b226-f1e3bc43ac3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638720274 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.1638720274
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.168867193
Short name T220
Test name
Test status
Simulation time 370278126 ps
CPU time 0.99 seconds
Started Aug 11 05:36:04 PM PDT 24
Finished Aug 11 05:36:05 PM PDT 24
Peak memory 213424 kb
Host smart-0ec845dd-77a5-438d-9962-9d155fa3731f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168867193 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.168867193
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.3831007720
Short name T28
Test name
Test status
Simulation time 1297543321 ps
CPU time 2.76 seconds
Started Aug 11 05:36:05 PM PDT 24
Finished Aug 11 05:36:08 PM PDT 24
Peak memory 205184 kb
Host smart-1b2071f5-471e-4b6d-b5a3-2e82dec2f9fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831007720 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.3831007720
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.2490226927
Short name T31
Test name
Test status
Simulation time 52358607 ps
CPU time 0.88 seconds
Started Aug 11 05:36:03 PM PDT 24
Finished Aug 11 05:36:04 PM PDT 24
Peak memory 213388 kb
Host smart-d3a4babc-7805-46db-ab8a-db9be6a950e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490226927 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.2490226927
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.2414036454
Short name T58
Test name
Test status
Simulation time 1345155540 ps
CPU time 1.57 seconds
Started Aug 11 05:36:04 PM PDT 24
Finished Aug 11 05:36:06 PM PDT 24
Peak memory 229556 kb
Host smart-6c571732-d9c2-4221-b9c9-b7c450879e08
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414036454 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.2414036454
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.2465111862
Short name T221
Test name
Test status
Simulation time 508903462 ps
CPU time 2.06 seconds
Started Aug 11 05:35:55 PM PDT 24
Finished Aug 11 05:35:57 PM PDT 24
Peak memory 205216 kb
Host smart-191f0ff3-6183-4b94-a9ea-5a6ff70edff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465111862 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.2465111862
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.153063234
Short name T174
Test name
Test status
Simulation time 122659576 ps
CPU time 1.02 seconds
Started Aug 11 05:36:16 PM PDT 24
Finished Aug 11 05:36:18 PM PDT 24
Peak memory 205216 kb
Host smart-a7e3ce9c-ee9e-4bc0-8d50-683fc82a2f61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153063234 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.153063234
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.1369508598
Short name T187
Test name
Test status
Simulation time 12025718907 ps
CPU time 34.16 seconds
Started Aug 11 05:36:17 PM PDT 24
Finished Aug 11 05:36:51 PM PDT 24
Peak memory 213924 kb
Host smart-d27e974d-8d9e-4aaf-b518-ddd008e6be8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369508598 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.1369508598
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.812296161
Short name T223
Test name
Test status
Simulation time 13386760965 ps
CPU time 37.69 seconds
Started Aug 11 05:36:21 PM PDT 24
Finished Aug 11 05:36:59 PM PDT 24
Peak memory 213892 kb
Host smart-dc9a7346-787f-4293-a124-d5642fde6ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812296161 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.812296161
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.2708352170
Short name T274
Test name
Test status
Simulation time 3159562227 ps
CPU time 9.37 seconds
Started Aug 11 05:36:16 PM PDT 24
Finished Aug 11 05:36:25 PM PDT 24
Peak memory 213808 kb
Host smart-2d205293-0aff-44b5-89b9-8f722e087658
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2708352170 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_
tl_access.2708352170
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.3434716335
Short name T204
Test name
Test status
Simulation time 4463993548 ps
CPU time 13.01 seconds
Started Aug 11 05:36:17 PM PDT 24
Finished Aug 11 05:36:30 PM PDT 24
Peak memory 213840 kb
Host smart-27fa174f-aa47-4d04-8f3d-f7659745d016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434716335 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.3434716335
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.2170320211
Short name T268
Test name
Test status
Simulation time 42830646 ps
CPU time 0.77 seconds
Started Aug 11 05:36:21 PM PDT 24
Finished Aug 11 05:36:22 PM PDT 24
Peak memory 205244 kb
Host smart-629c52c9-08f3-414b-9629-b56449d50816
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170320211 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.2170320211
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.2508440702
Short name T233
Test name
Test status
Simulation time 2745539128 ps
CPU time 8.39 seconds
Started Aug 11 05:36:17 PM PDT 24
Finished Aug 11 05:36:26 PM PDT 24
Peak memory 205752 kb
Host smart-6b39bcfb-fed0-49df-a526-0315a7a0c7e8
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2508440702 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_
tl_access.2508440702
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.2951397525
Short name T250
Test name
Test status
Simulation time 2167261239 ps
CPU time 2.88 seconds
Started Aug 11 05:36:17 PM PDT 24
Finished Aug 11 05:36:20 PM PDT 24
Peak memory 205676 kb
Host smart-40fb151c-8482-445e-b97e-8ab0401ee658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951397525 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.2951397525
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_stress_all.1651013814
Short name T11
Test name
Test status
Simulation time 2266855465 ps
CPU time 3.97 seconds
Started Aug 11 05:36:18 PM PDT 24
Finished Aug 11 05:36:22 PM PDT 24
Peak memory 213656 kb
Host smart-ba27f2b1-68b2-481a-bafa-5e5957416903
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651013814 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.1651013814
Directory /workspace/11.rv_dm_stress_all/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.2174277511
Short name T240
Test name
Test status
Simulation time 85822339 ps
CPU time 0.82 seconds
Started Aug 11 05:36:20 PM PDT 24
Finished Aug 11 05:36:22 PM PDT 24
Peak memory 205280 kb
Host smart-23cd5258-e983-43f1-8d0d-48b1e968ac70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174277511 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.2174277511
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.3404517465
Short name T199
Test name
Test status
Simulation time 4317477667 ps
CPU time 10.18 seconds
Started Aug 11 05:36:27 PM PDT 24
Finished Aug 11 05:36:37 PM PDT 24
Peak memory 213848 kb
Host smart-3f7a4bbf-3eb5-466c-88db-b1dd1dffbfa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404517465 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.3404517465
Directory /workspace/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.1944313563
Short name T239
Test name
Test status
Simulation time 1126572237 ps
CPU time 1.69 seconds
Started Aug 11 05:36:18 PM PDT 24
Finished Aug 11 05:36:20 PM PDT 24
Peak memory 205564 kb
Host smart-88cb3866-fb1a-4bf5-b242-f2f5ae6d16d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944313563 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.1944313563
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.3421986152
Short name T48
Test name
Test status
Simulation time 5822734768 ps
CPU time 16.45 seconds
Started Aug 11 05:36:21 PM PDT 24
Finished Aug 11 05:36:38 PM PDT 24
Peak memory 213996 kb
Host smart-78cf50a3-db55-4581-9149-68c0353940a3
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3421986152 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_
tl_access.3421986152
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.3275309620
Short name T66
Test name
Test status
Simulation time 3203657382 ps
CPU time 5.29 seconds
Started Aug 11 05:36:24 PM PDT 24
Finished Aug 11 05:36:30 PM PDT 24
Peak memory 205588 kb
Host smart-af3f5c6b-a57d-4cb4-99a6-2d7572d6536c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275309620 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.3275309620
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_stress_all.49794149
Short name T132
Test name
Test status
Simulation time 3590963742 ps
CPU time 3.59 seconds
Started Aug 11 05:36:17 PM PDT 24
Finished Aug 11 05:36:21 PM PDT 24
Peak memory 213792 kb
Host smart-e741fe00-afef-4f32-9256-2b3b726198c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49794149 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.49794149
Directory /workspace/12.rv_dm_stress_all/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.1321966867
Short name T292
Test name
Test status
Simulation time 44721526 ps
CPU time 0.8 seconds
Started Aug 11 05:36:18 PM PDT 24
Finished Aug 11 05:36:19 PM PDT 24
Peak memory 205276 kb
Host smart-9d43ae04-a364-4d86-a873-940207180e04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321966867 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.1321966867
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.1819537473
Short name T13
Test name
Test status
Simulation time 1923559729 ps
CPU time 3.42 seconds
Started Aug 11 05:36:24 PM PDT 24
Finished Aug 11 05:36:28 PM PDT 24
Peak memory 214648 kb
Host smart-0c62b780-ba2f-475f-b745-97afe59f68d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819537473 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.1819537473
Directory /workspace/13.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.704023503
Short name T242
Test name
Test status
Simulation time 8063768824 ps
CPU time 20.45 seconds
Started Aug 11 05:36:16 PM PDT 24
Finished Aug 11 05:36:36 PM PDT 24
Peak memory 205992 kb
Host smart-b799762d-92b2-46bf-8de6-d1826da3f1de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704023503 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.704023503
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.725579046
Short name T234
Test name
Test status
Simulation time 3239990993 ps
CPU time 4.38 seconds
Started Aug 11 05:36:17 PM PDT 24
Finished Aug 11 05:36:22 PM PDT 24
Peak memory 213856 kb
Host smart-e4c95c9e-8efa-41f8-8fea-e0954b6c9e4c
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=725579046 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_t
l_access.725579046
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.1819323990
Short name T129
Test name
Test status
Simulation time 7778918605 ps
CPU time 5.12 seconds
Started Aug 11 05:36:16 PM PDT 24
Finished Aug 11 05:36:21 PM PDT 24
Peak memory 215064 kb
Host smart-884b8e48-b523-43b0-a2a0-351a654ed1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819323990 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.1819323990
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_stress_all.768622605
Short name T122
Test name
Test status
Simulation time 7496345608 ps
CPU time 20.32 seconds
Started Aug 11 05:36:14 PM PDT 24
Finished Aug 11 05:36:35 PM PDT 24
Peak memory 205492 kb
Host smart-f3a4f473-4669-4525-bf8b-b4bf82b1effe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768622605 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.768622605
Directory /workspace/13.rv_dm_stress_all/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.1470537396
Short name T198
Test name
Test status
Simulation time 297381216 ps
CPU time 0.74 seconds
Started Aug 11 05:36:21 PM PDT 24
Finished Aug 11 05:36:22 PM PDT 24
Peak memory 205196 kb
Host smart-41a50da9-0698-4f9f-b4b4-55a5ce505ad3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470537396 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.1470537396
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.68187182
Short name T62
Test name
Test status
Simulation time 15466690612 ps
CPU time 41.47 seconds
Started Aug 11 05:36:22 PM PDT 24
Finished Aug 11 05:37:03 PM PDT 24
Peak memory 213976 kb
Host smart-c0b37c76-34ee-40bd-af78-ac20fd8a7649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68187182 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.68187182
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.4134260830
Short name T139
Test name
Test status
Simulation time 5256288550 ps
CPU time 9.4 seconds
Started Aug 11 05:36:20 PM PDT 24
Finished Aug 11 05:36:30 PM PDT 24
Peak memory 213980 kb
Host smart-60f7d19b-8826-4e15-be3d-45ed1234076f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4134260830 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_
tl_access.4134260830
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.528555381
Short name T184
Test name
Test status
Simulation time 6871258596 ps
CPU time 6.45 seconds
Started Aug 11 05:36:17 PM PDT 24
Finished Aug 11 05:36:24 PM PDT 24
Peak memory 205712 kb
Host smart-e65c35fe-507f-49ab-a996-44d5066cb1f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528555381 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.528555381
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_stress_all.2023728588
Short name T134
Test name
Test status
Simulation time 3436929464 ps
CPU time 6.33 seconds
Started Aug 11 05:36:23 PM PDT 24
Finished Aug 11 05:36:29 PM PDT 24
Peak memory 205492 kb
Host smart-094b3e8b-f40b-486b-a1a2-7333b7475945
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023728588 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.2023728588
Directory /workspace/14.rv_dm_stress_all/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.1574510374
Short name T172
Test name
Test status
Simulation time 154394516 ps
CPU time 0.8 seconds
Started Aug 11 05:36:21 PM PDT 24
Finished Aug 11 05:36:22 PM PDT 24
Peak memory 205228 kb
Host smart-d2952169-5652-4daa-a558-96843ef0de5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574510374 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.1574510374
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.1889935442
Short name T273
Test name
Test status
Simulation time 33575147454 ps
CPU time 93.52 seconds
Started Aug 11 05:36:24 PM PDT 24
Finished Aug 11 05:37:57 PM PDT 24
Peak memory 213888 kb
Host smart-f2c1d868-be50-4e3a-a0dd-23f3d3bb1e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889935442 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.1889935442
Directory /workspace/15.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.3478072207
Short name T201
Test name
Test status
Simulation time 3220530387 ps
CPU time 4.92 seconds
Started Aug 11 05:36:26 PM PDT 24
Finished Aug 11 05:36:31 PM PDT 24
Peak memory 213796 kb
Host smart-e1f38197-8e4f-47b9-8fc4-5ab0fe7d0bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478072207 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.3478072207
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.2243907561
Short name T295
Test name
Test status
Simulation time 974908249 ps
CPU time 1.1 seconds
Started Aug 11 05:36:23 PM PDT 24
Finished Aug 11 05:36:24 PM PDT 24
Peak memory 205596 kb
Host smart-cfa9577c-0eb6-4a81-88fb-b89df45796e7
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2243907561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_
tl_access.2243907561
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.1778856169
Short name T190
Test name
Test status
Simulation time 2333086170 ps
CPU time 2.71 seconds
Started Aug 11 05:36:32 PM PDT 24
Finished Aug 11 05:36:35 PM PDT 24
Peak memory 205708 kb
Host smart-453c7508-baca-4751-88cc-e62bf753f06f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778856169 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.1778856169
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_stress_all.3326109439
Short name T15
Test name
Test status
Simulation time 3409755863 ps
CPU time 5.69 seconds
Started Aug 11 05:36:23 PM PDT 24
Finished Aug 11 05:36:29 PM PDT 24
Peak memory 213660 kb
Host smart-4ebb969a-b678-4f54-88fd-5d885e468f59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326109439 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.3326109439
Directory /workspace/15.rv_dm_stress_all/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.182694634
Short name T193
Test name
Test status
Simulation time 83494992 ps
CPU time 0.85 seconds
Started Aug 11 05:36:32 PM PDT 24
Finished Aug 11 05:36:33 PM PDT 24
Peak memory 204840 kb
Host smart-001c1f47-1b2e-43a0-9e4f-61d29d743a29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182694634 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.182694634
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.3584417349
Short name T49
Test name
Test status
Simulation time 10415635455 ps
CPU time 12.68 seconds
Started Aug 11 05:36:22 PM PDT 24
Finished Aug 11 05:36:35 PM PDT 24
Peak memory 213888 kb
Host smart-863b49f2-6b15-4ced-a62d-3891efc2bb06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584417349 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.3584417349
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.487459473
Short name T189
Test name
Test status
Simulation time 4148325171 ps
CPU time 12.97 seconds
Started Aug 11 05:36:22 PM PDT 24
Finished Aug 11 05:36:35 PM PDT 24
Peak memory 213912 kb
Host smart-afb37622-a916-428f-a616-9938538497ea
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=487459473 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_t
l_access.487459473
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.888411235
Short name T210
Test name
Test status
Simulation time 1898515961 ps
CPU time 5.8 seconds
Started Aug 11 05:36:32 PM PDT 24
Finished Aug 11 05:36:38 PM PDT 24
Peak memory 205456 kb
Host smart-4e2360ff-ade0-4dbb-b41b-b5593f8d2cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888411235 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.888411235
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_stress_all.2598239521
Short name T46
Test name
Test status
Simulation time 8163278124 ps
CPU time 23.68 seconds
Started Aug 11 05:36:23 PM PDT 24
Finished Aug 11 05:36:47 PM PDT 24
Peak memory 213760 kb
Host smart-7dd922b6-2a53-49b8-b386-05e6eeb9378a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598239521 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.2598239521
Directory /workspace/16.rv_dm_stress_all/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.4084671610
Short name T222
Test name
Test status
Simulation time 48561603 ps
CPU time 0.81 seconds
Started Aug 11 05:36:31 PM PDT 24
Finished Aug 11 05:36:32 PM PDT 24
Peak memory 205208 kb
Host smart-03a66c53-61e2-4899-abd8-63b997bf0fb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084671610 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.4084671610
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.2609692173
Short name T116
Test name
Test status
Simulation time 26332208750 ps
CPU time 64.06 seconds
Started Aug 11 05:36:31 PM PDT 24
Finished Aug 11 05:37:35 PM PDT 24
Peak memory 213776 kb
Host smart-0214240a-ee69-4584-b37d-004d363e8a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609692173 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.2609692173
Directory /workspace/17.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.2524606156
Short name T262
Test name
Test status
Simulation time 3039605504 ps
CPU time 3.99 seconds
Started Aug 11 05:36:25 PM PDT 24
Finished Aug 11 05:36:29 PM PDT 24
Peak memory 213896 kb
Host smart-fda2c174-d43e-4f7a-b9b3-fc2f304c9a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524606156 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.2524606156
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.439528029
Short name T178
Test name
Test status
Simulation time 1182464050 ps
CPU time 4.37 seconds
Started Aug 11 05:36:32 PM PDT 24
Finished Aug 11 05:36:37 PM PDT 24
Peak memory 213732 kb
Host smart-779f805b-f41f-4d59-8a8f-32de12e6a9f9
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=439528029 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_t
l_access.439528029
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.3712948717
Short name T215
Test name
Test status
Simulation time 2574410279 ps
CPU time 7.93 seconds
Started Aug 11 05:36:22 PM PDT 24
Finished Aug 11 05:36:30 PM PDT 24
Peak memory 205652 kb
Host smart-8ff3a70f-093c-4cf4-af49-64aa2f733937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712948717 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.3712948717
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_stress_all.950075294
Short name T128
Test name
Test status
Simulation time 2002577468 ps
CPU time 2.49 seconds
Started Aug 11 05:36:32 PM PDT 24
Finished Aug 11 05:36:35 PM PDT 24
Peak memory 205428 kb
Host smart-c8277a87-c945-4d5e-988b-cfb09fea17aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950075294 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.950075294
Directory /workspace/17.rv_dm_stress_all/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.3899032799
Short name T249
Test name
Test status
Simulation time 56107509 ps
CPU time 0.78 seconds
Started Aug 11 05:36:31 PM PDT 24
Finished Aug 11 05:36:32 PM PDT 24
Peak memory 205236 kb
Host smart-71c2dafa-118e-4365-b3f3-fe75d86e11d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899032799 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.3899032799
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.944455155
Short name T226
Test name
Test status
Simulation time 5286428652 ps
CPU time 8.87 seconds
Started Aug 11 05:36:31 PM PDT 24
Finished Aug 11 05:36:40 PM PDT 24
Peak memory 215208 kb
Host smart-fbd073ab-e3ec-4b8d-83f6-679678a54b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944455155 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.944455155
Directory /workspace/18.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.816686074
Short name T120
Test name
Test status
Simulation time 3851245063 ps
CPU time 10.64 seconds
Started Aug 11 05:36:29 PM PDT 24
Finished Aug 11 05:36:40 PM PDT 24
Peak memory 213924 kb
Host smart-bf6edf83-78be-42be-98fd-c06e4bbc37da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816686074 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.816686074
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.3572642235
Short name T131
Test name
Test status
Simulation time 17725098862 ps
CPU time 21.96 seconds
Started Aug 11 05:36:30 PM PDT 24
Finished Aug 11 05:36:53 PM PDT 24
Peak memory 213824 kb
Host smart-8161964c-199e-428b-9ad5-39fa6c5121dc
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3572642235 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_
tl_access.3572642235
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.1262221313
Short name T126
Test name
Test status
Simulation time 1161410287 ps
CPU time 2.7 seconds
Started Aug 11 05:36:37 PM PDT 24
Finished Aug 11 05:36:40 PM PDT 24
Peak memory 213812 kb
Host smart-222be2cf-13b0-42bb-987b-35aea61e236a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262221313 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.1262221313
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_stress_all.2431384468
Short name T283
Test name
Test status
Simulation time 2281470416 ps
CPU time 3.58 seconds
Started Aug 11 05:36:32 PM PDT 24
Finished Aug 11 05:36:36 PM PDT 24
Peak memory 205640 kb
Host smart-702c1752-64d4-4893-bbcd-40238a12bd66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431384468 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.2431384468
Directory /workspace/18.rv_dm_stress_all/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.283729226
Short name T231
Test name
Test status
Simulation time 153078107 ps
CPU time 0.9 seconds
Started Aug 11 05:36:31 PM PDT 24
Finished Aug 11 05:36:32 PM PDT 24
Peak memory 205260 kb
Host smart-aea8e0ee-2ee4-4363-baa5-68db76db6edc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283729226 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.283729226
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.808810218
Short name T297
Test name
Test status
Simulation time 1660632878 ps
CPU time 5.11 seconds
Started Aug 11 05:36:29 PM PDT 24
Finished Aug 11 05:36:34 PM PDT 24
Peak memory 213792 kb
Host smart-58ae4c3e-850b-403e-8ed1-668e6c4189ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808810218 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.808810218
Directory /workspace/19.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.125435965
Short name T177
Test name
Test status
Simulation time 4667452343 ps
CPU time 6.35 seconds
Started Aug 11 05:36:31 PM PDT 24
Finished Aug 11 05:36:37 PM PDT 24
Peak memory 221984 kb
Host smart-bee0ef4d-a486-4bb2-999c-6634afabfc68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125435965 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.125435965
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.2642021101
Short name T251
Test name
Test status
Simulation time 6947609725 ps
CPU time 19.62 seconds
Started Aug 11 05:36:30 PM PDT 24
Finished Aug 11 05:36:50 PM PDT 24
Peak memory 213912 kb
Host smart-49766aa5-ce33-4bfd-9b21-86eff7356314
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2642021101 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_
tl_access.2642021101
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.3103308825
Short name T64
Test name
Test status
Simulation time 2598467840 ps
CPU time 7.75 seconds
Started Aug 11 05:36:30 PM PDT 24
Finished Aug 11 05:36:38 PM PDT 24
Peak memory 205664 kb
Host smart-e412a4df-8284-43a5-ab3d-e90595e4ece1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103308825 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.3103308825
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_stress_all.3380888456
Short name T22
Test name
Test status
Simulation time 12640923185 ps
CPU time 11.07 seconds
Started Aug 11 05:36:33 PM PDT 24
Finished Aug 11 05:36:44 PM PDT 24
Peak memory 214764 kb
Host smart-2030a12a-404f-410a-ba26-85d7871fbaa7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380888456 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.3380888456
Directory /workspace/19.rv_dm_stress_all/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.3676261065
Short name T272
Test name
Test status
Simulation time 32133206 ps
CPU time 0.75 seconds
Started Aug 11 05:36:08 PM PDT 24
Finished Aug 11 05:36:09 PM PDT 24
Peak memory 205216 kb
Host smart-ef13f04b-4e39-4b1a-b34c-f8222bb1f77e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676261065 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.3676261065
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.2936325752
Short name T225
Test name
Test status
Simulation time 2875040699 ps
CPU time 8.73 seconds
Started Aug 11 05:36:08 PM PDT 24
Finished Aug 11 05:36:17 PM PDT 24
Peak memory 213868 kb
Host smart-763308be-fddd-402d-b7f7-81c0436fe1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936325752 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.2936325752
Directory /workspace/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.279385674
Short name T300
Test name
Test status
Simulation time 8019442771 ps
CPU time 3.97 seconds
Started Aug 11 05:36:09 PM PDT 24
Finished Aug 11 05:36:13 PM PDT 24
Peak memory 215564 kb
Host smart-1e4c2e5b-08b0-4bde-827f-9b0388ad7ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279385674 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.279385674
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.341718756
Short name T181
Test name
Test status
Simulation time 2292467427 ps
CPU time 1.61 seconds
Started Aug 11 05:36:01 PM PDT 24
Finished Aug 11 05:36:03 PM PDT 24
Peak memory 205660 kb
Host smart-d1ee49ef-c33c-4241-97f0-d2a2551f0f68
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=341718756 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_tl
_access.341718756
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_halt_resume_whereto.1240820960
Short name T219
Test name
Test status
Simulation time 489666657 ps
CPU time 2.06 seconds
Started Aug 11 05:36:09 PM PDT 24
Finished Aug 11 05:36:11 PM PDT 24
Peak memory 205212 kb
Host smart-8fc9209f-31ff-4a1d-ac13-99496ea1312d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240820960 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_halt_resume_whereto.1240820960
Directory /workspace/2.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.1677321790
Short name T26
Test name
Test status
Simulation time 1022336431 ps
CPU time 2.14 seconds
Started Aug 11 05:36:10 PM PDT 24
Finished Aug 11 05:36:13 PM PDT 24
Peak memory 205160 kb
Host smart-8862c2bf-1c45-41df-944e-5a9e1dffa753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677321790 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.1677321790
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.2451448177
Short name T257
Test name
Test status
Simulation time 994275372 ps
CPU time 1.92 seconds
Started Aug 11 05:36:04 PM PDT 24
Finished Aug 11 05:36:06 PM PDT 24
Peak memory 205548 kb
Host smart-0670169b-d08c-4b23-9aeb-81d5fc27697d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451448177 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.2451448177
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.2493543767
Short name T59
Test name
Test status
Simulation time 706402686 ps
CPU time 2.89 seconds
Started Aug 11 05:36:11 PM PDT 24
Finished Aug 11 05:36:14 PM PDT 24
Peak memory 229576 kb
Host smart-b88ca146-a3fe-4248-8675-84b3c055f33d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493543767 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.2493543767
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/2.rv_dm_stress_all.1020346172
Short name T266
Test name
Test status
Simulation time 7802923916 ps
CPU time 12.9 seconds
Started Aug 11 05:36:10 PM PDT 24
Finished Aug 11 05:36:23 PM PDT 24
Peak memory 213792 kb
Host smart-eb0c98dd-a390-4cf5-a249-390162d44fc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020346172 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.1020346172
Directory /workspace/2.rv_dm_stress_all/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.4276431286
Short name T188
Test name
Test status
Simulation time 78279203 ps
CPU time 0.87 seconds
Started Aug 11 05:36:33 PM PDT 24
Finished Aug 11 05:36:34 PM PDT 24
Peak memory 205184 kb
Host smart-5da66419-f795-4a8c-b31b-97af80756a10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276431286 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.4276431286
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_stress_all.2770039967
Short name T147
Test name
Test status
Simulation time 4080061021 ps
CPU time 3.48 seconds
Started Aug 11 05:36:32 PM PDT 24
Finished Aug 11 05:36:36 PM PDT 24
Peak memory 213796 kb
Host smart-675ad6b2-061a-4c6e-a9c7-997ab29075a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770039967 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.2770039967
Directory /workspace/21.rv_dm_stress_all/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.2922975484
Short name T192
Test name
Test status
Simulation time 41551196 ps
CPU time 0.73 seconds
Started Aug 11 05:36:30 PM PDT 24
Finished Aug 11 05:36:31 PM PDT 24
Peak memory 205200 kb
Host smart-9277ef58-9693-4e72-ba4d-9aa92ffaee23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922975484 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.2922975484
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_stress_all.484561167
Short name T235
Test name
Test status
Simulation time 2056585591 ps
CPU time 3.66 seconds
Started Aug 11 05:36:31 PM PDT 24
Finished Aug 11 05:36:35 PM PDT 24
Peak memory 213636 kb
Host smart-2aef37cb-e0c8-4b53-aede-cdf06d0e40fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484561167 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.484561167
Directory /workspace/22.rv_dm_stress_all/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.1115848811
Short name T191
Test name
Test status
Simulation time 70907135 ps
CPU time 0.81 seconds
Started Aug 11 05:36:31 PM PDT 24
Finished Aug 11 05:36:32 PM PDT 24
Peak memory 205216 kb
Host smart-775ba17d-9d34-4fda-9544-e79428eb053a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115848811 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.1115848811
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_stress_all.1148170689
Short name T293
Test name
Test status
Simulation time 3482274544 ps
CPU time 6.49 seconds
Started Aug 11 05:36:34 PM PDT 24
Finished Aug 11 05:36:40 PM PDT 24
Peak memory 213732 kb
Host smart-b83e642d-0539-4b70-8855-4bda4a319aea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148170689 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.1148170689
Directory /workspace/23.rv_dm_stress_all/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.2961612073
Short name T244
Test name
Test status
Simulation time 42977514 ps
CPU time 0.81 seconds
Started Aug 11 05:36:33 PM PDT 24
Finished Aug 11 05:36:34 PM PDT 24
Peak memory 205196 kb
Host smart-e7e01156-85cf-4ac3-a8e3-c6c252cbd8aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961612073 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.2961612073
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_stress_all.2444045065
Short name T161
Test name
Test status
Simulation time 2489808918 ps
CPU time 2.74 seconds
Started Aug 11 05:36:32 PM PDT 24
Finished Aug 11 05:36:35 PM PDT 24
Peak memory 213788 kb
Host smart-a00581ba-629d-417b-a3fa-c668afca3d40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444045065 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.2444045065
Directory /workspace/24.rv_dm_stress_all/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.1741138395
Short name T281
Test name
Test status
Simulation time 64725628 ps
CPU time 0.87 seconds
Started Aug 11 05:36:29 PM PDT 24
Finished Aug 11 05:36:30 PM PDT 24
Peak memory 205464 kb
Host smart-f9fa8cef-2eef-4853-b5fd-16f7da3970c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741138395 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.1741138395
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_stress_all.1100636939
Short name T142
Test name
Test status
Simulation time 4922412123 ps
CPU time 8.19 seconds
Started Aug 11 05:36:30 PM PDT 24
Finished Aug 11 05:36:38 PM PDT 24
Peak memory 205484 kb
Host smart-285fe90b-406d-4e38-961b-4868deb418f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100636939 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.1100636939
Directory /workspace/25.rv_dm_stress_all/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.3683981421
Short name T207
Test name
Test status
Simulation time 54560147 ps
CPU time 0.8 seconds
Started Aug 11 05:36:30 PM PDT 24
Finished Aug 11 05:36:31 PM PDT 24
Peak memory 205268 kb
Host smart-4d9d9b3c-770d-4980-bbd0-a8de359dfc56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683981421 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.3683981421
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_stress_all.2231881905
Short name T121
Test name
Test status
Simulation time 4427847560 ps
CPU time 4.57 seconds
Started Aug 11 05:36:30 PM PDT 24
Finished Aug 11 05:36:35 PM PDT 24
Peak memory 213812 kb
Host smart-ad03d961-80ce-498f-baad-b2527bb0d907
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231881905 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.2231881905
Directory /workspace/26.rv_dm_stress_all/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.3897184332
Short name T65
Test name
Test status
Simulation time 80137606 ps
CPU time 0.7 seconds
Started Aug 11 05:36:29 PM PDT 24
Finished Aug 11 05:36:30 PM PDT 24
Peak memory 205224 kb
Host smart-26888397-0b30-46bd-b449-337dff319198
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897184332 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.3897184332
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_stress_all.2320030656
Short name T144
Test name
Test status
Simulation time 1836551568 ps
CPU time 5.42 seconds
Started Aug 11 05:36:32 PM PDT 24
Finished Aug 11 05:36:38 PM PDT 24
Peak memory 205404 kb
Host smart-3a41137f-4b3d-4a3b-b687-9dcff2ee8e6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320030656 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.2320030656
Directory /workspace/27.rv_dm_stress_all/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.2416861973
Short name T203
Test name
Test status
Simulation time 185784253 ps
CPU time 0.82 seconds
Started Aug 11 05:36:31 PM PDT 24
Finished Aug 11 05:36:32 PM PDT 24
Peak memory 205216 kb
Host smart-8451b9b7-8219-4e10-a4d4-866fd9c3b53b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416861973 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.2416861973
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_stress_all.3189151352
Short name T47
Test name
Test status
Simulation time 2253588436 ps
CPU time 5.69 seconds
Started Aug 11 05:36:37 PM PDT 24
Finished Aug 11 05:36:43 PM PDT 24
Peak memory 205580 kb
Host smart-96e1320f-78e3-4982-8bde-58cd67663f0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189151352 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.3189151352
Directory /workspace/28.rv_dm_stress_all/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.607813553
Short name T276
Test name
Test status
Simulation time 45434376 ps
CPU time 0.76 seconds
Started Aug 11 05:36:32 PM PDT 24
Finished Aug 11 05:36:33 PM PDT 24
Peak memory 205260 kb
Host smart-17692714-3d13-43bf-89e5-aef1179a1517
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607813553 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.607813553
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.2245847938
Short name T205
Test name
Test status
Simulation time 36781949 ps
CPU time 0.76 seconds
Started Aug 11 05:36:08 PM PDT 24
Finished Aug 11 05:36:09 PM PDT 24
Peak memory 205212 kb
Host smart-a6cbe493-3968-4199-8ce3-09fca0496437
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245847938 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.2245847938
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.1956425839
Short name T171
Test name
Test status
Simulation time 30737790805 ps
CPU time 76.48 seconds
Started Aug 11 05:36:06 PM PDT 24
Finished Aug 11 05:37:23 PM PDT 24
Peak memory 213968 kb
Host smart-4c624737-e98a-4705-803c-32ee91eded37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956425839 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.1956425839
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.2015722583
Short name T301
Test name
Test status
Simulation time 2088414310 ps
CPU time 2.91 seconds
Started Aug 11 05:36:07 PM PDT 24
Finished Aug 11 05:36:10 PM PDT 24
Peak memory 214192 kb
Host smart-74e0aa0d-fefa-4240-adf9-c8ac9bdfe43e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015722583 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.2015722583
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.2588573414
Short name T265
Test name
Test status
Simulation time 5124883831 ps
CPU time 8.35 seconds
Started Aug 11 05:36:08 PM PDT 24
Finished Aug 11 05:36:16 PM PDT 24
Peak memory 213980 kb
Host smart-9906fffb-0704-4cba-a90f-2ea31fda5749
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2588573414 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t
l_access.2588573414
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_halt_resume_whereto.3018794137
Short name T275
Test name
Test status
Simulation time 547323233 ps
CPU time 1.5 seconds
Started Aug 11 05:36:08 PM PDT 24
Finished Aug 11 05:36:10 PM PDT 24
Peak memory 205080 kb
Host smart-8b956da4-302a-4c13-aa4b-aa3b0acad317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018794137 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_halt_resume_whereto.3018794137
Directory /workspace/3.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.867125511
Short name T284
Test name
Test status
Simulation time 684531117 ps
CPU time 1.21 seconds
Started Aug 11 05:36:10 PM PDT 24
Finished Aug 11 05:36:11 PM PDT 24
Peak memory 205196 kb
Host smart-2a8506cf-4a30-46c4-81c7-05408620036a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867125511 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.867125511
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.1718510102
Short name T133
Test name
Test status
Simulation time 2166990620 ps
CPU time 1.98 seconds
Started Aug 11 05:36:10 PM PDT 24
Finished Aug 11 05:36:12 PM PDT 24
Peak memory 213852 kb
Host smart-f61582c0-c327-4762-8b27-c6f8e95dffdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718510102 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.1718510102
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_stress_all.2653349666
Short name T124
Test name
Test status
Simulation time 2422293847 ps
CPU time 2.4 seconds
Started Aug 11 05:36:09 PM PDT 24
Finished Aug 11 05:36:12 PM PDT 24
Peak memory 205508 kb
Host smart-013ad0b1-9682-454d-b87c-e8704a49b459
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653349666 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.2653349666
Directory /workspace/3.rv_dm_stress_all/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.3938875777
Short name T57
Test name
Test status
Simulation time 50988786 ps
CPU time 0.73 seconds
Started Aug 11 05:36:30 PM PDT 24
Finished Aug 11 05:36:31 PM PDT 24
Peak memory 205148 kb
Host smart-4269f640-1cc5-4407-adb4-a11ea24eb258
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938875777 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.3938875777
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/30.rv_dm_stress_all.1491992197
Short name T19
Test name
Test status
Simulation time 16411109101 ps
CPU time 45.29 seconds
Started Aug 11 05:36:31 PM PDT 24
Finished Aug 11 05:37:17 PM PDT 24
Peak memory 213716 kb
Host smart-cb4e01a1-da92-47cd-b342-127a733ca772
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491992197 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.1491992197
Directory /workspace/30.rv_dm_stress_all/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.3077918608
Short name T260
Test name
Test status
Simulation time 67459834 ps
CPU time 0.71 seconds
Started Aug 11 05:36:31 PM PDT 24
Finished Aug 11 05:36:32 PM PDT 24
Peak memory 205172 kb
Host smart-e1525b0f-e66a-4cb0-88f7-a67fa9bb285b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077918608 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.3077918608
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_stress_all.2830211235
Short name T10
Test name
Test status
Simulation time 5056155682 ps
CPU time 7.62 seconds
Started Aug 11 05:36:32 PM PDT 24
Finished Aug 11 05:36:40 PM PDT 24
Peak memory 205564 kb
Host smart-66b50830-2c8d-48d7-afb5-ea97cd75cddb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830211235 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.2830211235
Directory /workspace/31.rv_dm_stress_all/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.1023541585
Short name T245
Test name
Test status
Simulation time 225212776 ps
CPU time 0.88 seconds
Started Aug 11 05:36:30 PM PDT 24
Finished Aug 11 05:36:30 PM PDT 24
Peak memory 205112 kb
Host smart-08daad74-73da-4616-82e7-9dd8bbb4cd69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023541585 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.1023541585
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_stress_all.59547075
Short name T5
Test name
Test status
Simulation time 3331438086 ps
CPU time 2.67 seconds
Started Aug 11 05:36:30 PM PDT 24
Finished Aug 11 05:36:33 PM PDT 24
Peak memory 205532 kb
Host smart-5ae39630-f37c-4fa9-9f5c-628110d7f2f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59547075 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.59547075
Directory /workspace/32.rv_dm_stress_all/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.3116823398
Short name T278
Test name
Test status
Simulation time 282767727 ps
CPU time 0.82 seconds
Started Aug 11 05:36:31 PM PDT 24
Finished Aug 11 05:36:32 PM PDT 24
Peak memory 205200 kb
Host smart-6df59d89-77dd-4abb-a42a-b23b5d7487ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116823398 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.3116823398
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_stress_all.2051164026
Short name T21
Test name
Test status
Simulation time 4950192127 ps
CPU time 5.66 seconds
Started Aug 11 05:36:37 PM PDT 24
Finished Aug 11 05:36:43 PM PDT 24
Peak memory 205516 kb
Host smart-cbb22832-8165-4765-b45b-e1432319d330
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051164026 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.2051164026
Directory /workspace/33.rv_dm_stress_all/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.2532504221
Short name T168
Test name
Test status
Simulation time 117494967 ps
CPU time 0.75 seconds
Started Aug 11 05:36:37 PM PDT 24
Finished Aug 11 05:36:38 PM PDT 24
Peak memory 205200 kb
Host smart-13b1f46a-d174-4c8d-982d-cb03e58036f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532504221 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.2532504221
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_stress_all.2031590772
Short name T145
Test name
Test status
Simulation time 2476925967 ps
CPU time 4.4 seconds
Started Aug 11 05:36:36 PM PDT 24
Finished Aug 11 05:36:41 PM PDT 24
Peak memory 213768 kb
Host smart-86c8dc93-c4d4-4d3f-9e08-5a02278017a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031590772 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.2031590772
Directory /workspace/34.rv_dm_stress_all/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.196141677
Short name T237
Test name
Test status
Simulation time 70420735 ps
CPU time 0.71 seconds
Started Aug 11 05:36:38 PM PDT 24
Finished Aug 11 05:36:39 PM PDT 24
Peak memory 205220 kb
Host smart-28926453-ed94-4393-9db5-343cd8eafe7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196141677 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.196141677
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_stress_all.2550932501
Short name T206
Test name
Test status
Simulation time 9432903189 ps
CPU time 23.5 seconds
Started Aug 11 05:36:38 PM PDT 24
Finished Aug 11 05:37:02 PM PDT 24
Peak memory 213716 kb
Host smart-7bae06a0-f226-4ff9-a4f5-aa97809dda91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550932501 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.2550932501
Directory /workspace/35.rv_dm_stress_all/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.321242877
Short name T194
Test name
Test status
Simulation time 38203273 ps
CPU time 0.77 seconds
Started Aug 11 05:36:40 PM PDT 24
Finished Aug 11 05:36:41 PM PDT 24
Peak memory 205236 kb
Host smart-3460adea-2466-48d4-80c1-de880ae6e32e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321242877 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.321242877
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_stress_all.3388881236
Short name T119
Test name
Test status
Simulation time 8365129736 ps
CPU time 7.9 seconds
Started Aug 11 05:36:37 PM PDT 24
Finished Aug 11 05:36:45 PM PDT 24
Peak memory 213736 kb
Host smart-89c20aff-df44-4482-807d-1fadc4982850
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388881236 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.3388881236
Directory /workspace/36.rv_dm_stress_all/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.1148761755
Short name T173
Test name
Test status
Simulation time 43004659 ps
CPU time 0.76 seconds
Started Aug 11 05:36:37 PM PDT 24
Finished Aug 11 05:36:38 PM PDT 24
Peak memory 205176 kb
Host smart-b413f393-1ae1-4b7a-ad23-c816d5b1605e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148761755 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.1148761755
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_stress_all.2700469114
Short name T303
Test name
Test status
Simulation time 10022645319 ps
CPU time 11.2 seconds
Started Aug 11 05:36:36 PM PDT 24
Finished Aug 11 05:36:48 PM PDT 24
Peak memory 205448 kb
Host smart-819d0783-9c2d-4763-a5f4-c5d55dd048ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700469114 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.2700469114
Directory /workspace/37.rv_dm_stress_all/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.4217207394
Short name T209
Test name
Test status
Simulation time 64916018 ps
CPU time 0.82 seconds
Started Aug 11 05:36:38 PM PDT 24
Finished Aug 11 05:36:39 PM PDT 24
Peak memory 205224 kb
Host smart-d3e55c1e-996f-48a7-87e3-880e184dc7f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217207394 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.4217207394
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_stress_all.1309128215
Short name T163
Test name
Test status
Simulation time 1074095369 ps
CPU time 2.35 seconds
Started Aug 11 05:36:42 PM PDT 24
Finished Aug 11 05:36:45 PM PDT 24
Peak memory 213616 kb
Host smart-e0d25067-c760-4619-bb7b-debcb5153fc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309128215 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.1309128215
Directory /workspace/38.rv_dm_stress_all/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.2651604999
Short name T180
Test name
Test status
Simulation time 222512582 ps
CPU time 0.72 seconds
Started Aug 11 05:36:38 PM PDT 24
Finished Aug 11 05:36:39 PM PDT 24
Peak memory 205164 kb
Host smart-af9cc2a2-7676-4571-8c06-6ddf9a64fec5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651604999 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.2651604999
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_stress_all.3064544719
Short name T302
Test name
Test status
Simulation time 1965579962 ps
CPU time 3.6 seconds
Started Aug 11 05:36:41 PM PDT 24
Finished Aug 11 05:36:45 PM PDT 24
Peak memory 213680 kb
Host smart-9613e5d3-4ecf-4a43-a445-e0a9db5a9832
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064544719 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.3064544719
Directory /workspace/39.rv_dm_stress_all/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.1571160096
Short name T41
Test name
Test status
Simulation time 31782373 ps
CPU time 0.83 seconds
Started Aug 11 05:36:10 PM PDT 24
Finished Aug 11 05:36:12 PM PDT 24
Peak memory 205164 kb
Host smart-0a3bb47f-f610-4119-b95d-2f6ae64947f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571160096 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.1571160096
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.2428795199
Short name T14
Test name
Test status
Simulation time 811725244 ps
CPU time 1.95 seconds
Started Aug 11 05:36:14 PM PDT 24
Finished Aug 11 05:36:17 PM PDT 24
Peak memory 213724 kb
Host smart-30238a42-0872-48e5-8b2e-8089fca07748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428795199 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.2428795199
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.1642855065
Short name T261
Test name
Test status
Simulation time 913282099 ps
CPU time 1.66 seconds
Started Aug 11 05:36:13 PM PDT 24
Finished Aug 11 05:36:15 PM PDT 24
Peak memory 205592 kb
Host smart-e27c9be1-c80f-467a-9a84-0e4dc5d7a210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642855065 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.1642855065
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.3209878164
Short name T230
Test name
Test status
Simulation time 2099987601 ps
CPU time 7.19 seconds
Started Aug 11 05:36:14 PM PDT 24
Finished Aug 11 05:36:22 PM PDT 24
Peak memory 213680 kb
Host smart-f24fef23-6261-4b3f-be8d-e0613222dee3
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3209878164 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t
l_access.3209878164
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_halt_resume_whereto.2110399790
Short name T72
Test name
Test status
Simulation time 1101781196 ps
CPU time 1.92 seconds
Started Aug 11 05:36:15 PM PDT 24
Finished Aug 11 05:36:17 PM PDT 24
Peak memory 205152 kb
Host smart-9bf504d9-9871-4822-8aa0-443a221502c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110399790 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_halt_resume_whereto.2110399790
Directory /workspace/4.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.761954267
Short name T267
Test name
Test status
Simulation time 298250057 ps
CPU time 1.01 seconds
Started Aug 11 05:36:10 PM PDT 24
Finished Aug 11 05:36:11 PM PDT 24
Peak memory 205156 kb
Host smart-596b6931-ba40-4af1-9cf2-8fc7ca548b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761954267 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.761954267
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.2432906371
Short name T200
Test name
Test status
Simulation time 5782580159 ps
CPU time 8.8 seconds
Started Aug 11 05:36:09 PM PDT 24
Finished Aug 11 05:36:18 PM PDT 24
Peak memory 214452 kb
Host smart-f43982da-68c1-4594-8d19-7993684d4bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432906371 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.2432906371
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.4074096826
Short name T43
Test name
Test status
Simulation time 545853891 ps
CPU time 2.19 seconds
Started Aug 11 05:36:09 PM PDT 24
Finished Aug 11 05:36:12 PM PDT 24
Peak memory 228880 kb
Host smart-eb0fc289-9dd7-43ad-8340-4e10eb49baaa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074096826 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.4074096826
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/4.rv_dm_stress_all.1660019526
Short name T7
Test name
Test status
Simulation time 1892269559 ps
CPU time 4.3 seconds
Started Aug 11 05:36:11 PM PDT 24
Finished Aug 11 05:36:15 PM PDT 24
Peak memory 213560 kb
Host smart-8a855a8c-6b23-48b0-bbb3-c1834a745c55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660019526 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.1660019526
Directory /workspace/4.rv_dm_stress_all/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.1768315366
Short name T229
Test name
Test status
Simulation time 33978485 ps
CPU time 0.77 seconds
Started Aug 11 05:36:37 PM PDT 24
Finished Aug 11 05:36:38 PM PDT 24
Peak memory 205192 kb
Host smart-8eeb425e-24d8-48df-ac27-5b7e7f8fc29e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768315366 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.1768315366
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.3223883693
Short name T166
Test name
Test status
Simulation time 46004780 ps
CPU time 0.71 seconds
Started Aug 11 05:36:41 PM PDT 24
Finished Aug 11 05:36:42 PM PDT 24
Peak memory 205196 kb
Host smart-bdc236e4-0aaf-484c-97cd-1cb1c4433e1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223883693 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.3223883693
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_stress_all.1625311362
Short name T255
Test name
Test status
Simulation time 3477264322 ps
CPU time 5.39 seconds
Started Aug 11 05:36:37 PM PDT 24
Finished Aug 11 05:36:43 PM PDT 24
Peak memory 213720 kb
Host smart-a04b8d2b-9667-47c7-8cef-269de9231845
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625311362 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.1625311362
Directory /workspace/41.rv_dm_stress_all/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.1558622390
Short name T214
Test name
Test status
Simulation time 49934982 ps
CPU time 0.77 seconds
Started Aug 11 05:36:38 PM PDT 24
Finished Aug 11 05:36:39 PM PDT 24
Peak memory 205256 kb
Host smart-215c8773-117e-4455-b3ca-be1362d495ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558622390 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.1558622390
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.2151867466
Short name T195
Test name
Test status
Simulation time 73015218 ps
CPU time 0.7 seconds
Started Aug 11 05:36:41 PM PDT 24
Finished Aug 11 05:36:42 PM PDT 24
Peak memory 205192 kb
Host smart-d8ab1f77-bf30-4ed8-af3f-cc889c5deaa3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151867466 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.2151867466
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_stress_all.2679019234
Short name T146
Test name
Test status
Simulation time 2687422335 ps
CPU time 3.73 seconds
Started Aug 11 05:36:40 PM PDT 24
Finished Aug 11 05:36:43 PM PDT 24
Peak memory 213612 kb
Host smart-70da7c12-62bc-42dc-94e9-f150cbeb4ec0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679019234 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.2679019234
Directory /workspace/43.rv_dm_stress_all/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.3459630742
Short name T299
Test name
Test status
Simulation time 52769121 ps
CPU time 0.74 seconds
Started Aug 11 05:36:41 PM PDT 24
Finished Aug 11 05:36:42 PM PDT 24
Peak memory 205184 kb
Host smart-20222722-a642-4b67-b999-d9701ec1b57f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459630742 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.3459630742
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_stress_all.3001654986
Short name T130
Test name
Test status
Simulation time 1154429408 ps
CPU time 3.96 seconds
Started Aug 11 05:36:39 PM PDT 24
Finished Aug 11 05:36:43 PM PDT 24
Peak memory 213556 kb
Host smart-49672655-a9c7-4eba-9c1c-fb5d0df592e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001654986 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.3001654986
Directory /workspace/44.rv_dm_stress_all/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.2288531070
Short name T290
Test name
Test status
Simulation time 107039659 ps
CPU time 0.95 seconds
Started Aug 11 05:36:39 PM PDT 24
Finished Aug 11 05:36:40 PM PDT 24
Peak memory 205184 kb
Host smart-96f0a6ee-53d7-465c-97ef-5a63ada2f02c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288531070 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.2288531070
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_stress_all.1377110998
Short name T136
Test name
Test status
Simulation time 3872096198 ps
CPU time 3.72 seconds
Started Aug 11 05:36:39 PM PDT 24
Finished Aug 11 05:36:42 PM PDT 24
Peak memory 213704 kb
Host smart-eaeea74f-6b17-4925-9126-a8fc1e3583be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377110998 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.1377110998
Directory /workspace/45.rv_dm_stress_all/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.3480449437
Short name T294
Test name
Test status
Simulation time 39122462 ps
CPU time 0.7 seconds
Started Aug 11 05:36:42 PM PDT 24
Finished Aug 11 05:36:43 PM PDT 24
Peak memory 205276 kb
Host smart-31e4b5de-d737-4087-bf1d-9801ba0bfc4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480449437 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.3480449437
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_stress_all.1171816822
Short name T138
Test name
Test status
Simulation time 13191849559 ps
CPU time 16.3 seconds
Started Aug 11 05:36:41 PM PDT 24
Finished Aug 11 05:36:58 PM PDT 24
Peak memory 205524 kb
Host smart-7265f1cf-6f82-4ef3-a023-8ade7ae783a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171816822 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.1171816822
Directory /workspace/46.rv_dm_stress_all/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.2949291943
Short name T213
Test name
Test status
Simulation time 71565621 ps
CPU time 0.86 seconds
Started Aug 11 05:36:40 PM PDT 24
Finished Aug 11 05:36:41 PM PDT 24
Peak memory 205240 kb
Host smart-5b521590-49d6-4ae2-8c45-04eda2fa484a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949291943 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.2949291943
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_stress_all.1927954091
Short name T270
Test name
Test status
Simulation time 1743954366 ps
CPU time 1.96 seconds
Started Aug 11 05:36:37 PM PDT 24
Finished Aug 11 05:36:39 PM PDT 24
Peak memory 205368 kb
Host smart-3ec8a009-241f-4b53-9ae1-e3f7528246ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927954091 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.1927954091
Directory /workspace/47.rv_dm_stress_all/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.3229446761
Short name T279
Test name
Test status
Simulation time 105966811 ps
CPU time 0.95 seconds
Started Aug 11 05:36:42 PM PDT 24
Finished Aug 11 05:36:43 PM PDT 24
Peak memory 205208 kb
Host smart-c763d6c2-1429-45a9-8f4d-6ea942b35b22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229446761 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.3229446761
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_stress_all.1596390179
Short name T36
Test name
Test status
Simulation time 6889746905 ps
CPU time 3.58 seconds
Started Aug 11 05:36:38 PM PDT 24
Finished Aug 11 05:36:41 PM PDT 24
Peak memory 213684 kb
Host smart-666aae40-9766-4ea6-ba7c-6c6fd149a04e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596390179 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.1596390179
Directory /workspace/48.rv_dm_stress_all/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.2599748110
Short name T40
Test name
Test status
Simulation time 38885291 ps
CPU time 0.78 seconds
Started Aug 11 05:36:38 PM PDT 24
Finished Aug 11 05:36:39 PM PDT 24
Peak memory 205208 kb
Host smart-ca2c4247-d714-4df7-8a7d-ab5c1251486d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599748110 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.2599748110
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_stress_all.516731855
Short name T8
Test name
Test status
Simulation time 2336588156 ps
CPU time 8.11 seconds
Started Aug 11 05:36:42 PM PDT 24
Finished Aug 11 05:36:51 PM PDT 24
Peak memory 213760 kb
Host smart-4b3ced0e-0723-4f1b-a93b-158615ec4c75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516731855 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.516731855
Directory /workspace/49.rv_dm_stress_all/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.3547795411
Short name T164
Test name
Test status
Simulation time 72312757 ps
CPU time 0.76 seconds
Started Aug 11 05:36:11 PM PDT 24
Finished Aug 11 05:36:12 PM PDT 24
Peak memory 205212 kb
Host smart-de69e1df-1482-46fe-90ed-9da065d3bf08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547795411 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.3547795411
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.3103321210
Short name T246
Test name
Test status
Simulation time 27830933492 ps
CPU time 39.15 seconds
Started Aug 11 05:36:07 PM PDT 24
Finished Aug 11 05:36:47 PM PDT 24
Peak memory 218748 kb
Host smart-c1d2205c-c554-439f-81cf-24e609e26c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103321210 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.3103321210
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.1647656884
Short name T196
Test name
Test status
Simulation time 1473197210 ps
CPU time 3.05 seconds
Started Aug 11 05:36:09 PM PDT 24
Finished Aug 11 05:36:12 PM PDT 24
Peak memory 213716 kb
Host smart-7c2c6df9-0017-40d2-bc7e-7d92c0873ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647656884 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.1647656884
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.4093069913
Short name T256
Test name
Test status
Simulation time 8088161637 ps
CPU time 7.22 seconds
Started Aug 11 05:36:13 PM PDT 24
Finished Aug 11 05:36:20 PM PDT 24
Peak memory 213788 kb
Host smart-db9c442b-2e3f-47db-af00-639acd6ee03a
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4093069913 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t
l_access.4093069913
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_halt_resume_whereto.4262243705
Short name T243
Test name
Test status
Simulation time 796137569 ps
CPU time 1.78 seconds
Started Aug 11 05:36:10 PM PDT 24
Finished Aug 11 05:36:12 PM PDT 24
Peak memory 205148 kb
Host smart-42c445d6-af85-41ed-aca2-9db5773b6ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262243705 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_halt_resume_whereto.4262243705
Directory /workspace/5.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.130859226
Short name T63
Test name
Test status
Simulation time 3907616496 ps
CPU time 6.9 seconds
Started Aug 11 05:36:09 PM PDT 24
Finished Aug 11 05:36:16 PM PDT 24
Peak memory 205616 kb
Host smart-22c516d0-f67a-4088-a0db-e35e942f8765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130859226 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.130859226
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_stress_all.494653096
Short name T224
Test name
Test status
Simulation time 5907295618 ps
CPU time 16.81 seconds
Started Aug 11 05:36:08 PM PDT 24
Finished Aug 11 05:36:25 PM PDT 24
Peak memory 213716 kb
Host smart-6a0ad367-b29c-409c-9e4f-2edc21937978
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494653096 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.494653096
Directory /workspace/5.rv_dm_stress_all/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.859623408
Short name T217
Test name
Test status
Simulation time 52210991 ps
CPU time 0.76 seconds
Started Aug 11 05:36:11 PM PDT 24
Finished Aug 11 05:36:12 PM PDT 24
Peak memory 205240 kb
Host smart-df8b83d6-6d56-4f79-b6d2-dc28758ed840
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859623408 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.859623408
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.2696668876
Short name T27
Test name
Test status
Simulation time 46698474749 ps
CPU time 45.9 seconds
Started Aug 11 05:36:16 PM PDT 24
Finished Aug 11 05:37:02 PM PDT 24
Peak memory 213896 kb
Host smart-0fec09c2-72c9-4ac0-ad86-54a4d6064f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696668876 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.2696668876
Directory /workspace/6.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.2543621711
Short name T165
Test name
Test status
Simulation time 698567192 ps
CPU time 2.79 seconds
Started Aug 11 05:36:07 PM PDT 24
Finished Aug 11 05:36:10 PM PDT 24
Peak memory 213732 kb
Host smart-05492c3e-8d89-4176-a516-08dd832f90e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543621711 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.2543621711
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.2954647737
Short name T185
Test name
Test status
Simulation time 1048079792 ps
CPU time 3.72 seconds
Started Aug 11 05:36:06 PM PDT 24
Finished Aug 11 05:36:10 PM PDT 24
Peak memory 205544 kb
Host smart-14108ff9-b26c-46b2-a178-9ba81c565296
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2954647737 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t
l_access.2954647737
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_halt_resume_whereto.1742508442
Short name T4
Test name
Test status
Simulation time 583595247 ps
CPU time 1.71 seconds
Started Aug 11 05:36:11 PM PDT 24
Finished Aug 11 05:36:12 PM PDT 24
Peak memory 205176 kb
Host smart-af399749-e963-423a-b3ea-744dd93eb616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742508442 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_halt_resume_whereto.1742508442
Directory /workspace/6.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.3672717240
Short name T12
Test name
Test status
Simulation time 6446850306 ps
CPU time 5.78 seconds
Started Aug 11 05:36:11 PM PDT 24
Finished Aug 11 05:36:17 PM PDT 24
Peak memory 205632 kb
Host smart-6fd4fadd-168d-4ec4-84db-285bde5d0a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672717240 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.3672717240
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_stress_all.1826727501
Short name T288
Test name
Test status
Simulation time 4303541817 ps
CPU time 13.13 seconds
Started Aug 11 05:36:12 PM PDT 24
Finished Aug 11 05:36:26 PM PDT 24
Peak memory 205532 kb
Host smart-f3d8917c-5dd3-4ae8-bd95-3db86f2db766
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826727501 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.1826727501
Directory /workspace/6.rv_dm_stress_all/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.3643086269
Short name T167
Test name
Test status
Simulation time 99112653 ps
CPU time 0.7 seconds
Started Aug 11 05:36:21 PM PDT 24
Finished Aug 11 05:36:22 PM PDT 24
Peak memory 205264 kb
Host smart-2635f906-64b2-426d-b842-653e409d0821
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643086269 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.3643086269
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.4141037059
Short name T170
Test name
Test status
Simulation time 6723909604 ps
CPU time 7.05 seconds
Started Aug 11 05:36:16 PM PDT 24
Finished Aug 11 05:36:23 PM PDT 24
Peak memory 214144 kb
Host smart-5b9704d1-de44-463c-8678-f19d080c15f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141037059 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.4141037059
Directory /workspace/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.1617792505
Short name T254
Test name
Test status
Simulation time 8241824018 ps
CPU time 8.26 seconds
Started Aug 11 05:36:13 PM PDT 24
Finished Aug 11 05:36:22 PM PDT 24
Peak memory 213952 kb
Host smart-f54c1fc8-1114-469c-a548-1128e6547f08
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1617792505 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t
l_access.1617792505
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_halt_resume_whereto.1708445187
Short name T34
Test name
Test status
Simulation time 1374371897 ps
CPU time 1.67 seconds
Started Aug 11 05:36:16 PM PDT 24
Finished Aug 11 05:36:18 PM PDT 24
Peak memory 205176 kb
Host smart-056bbf3b-ba9f-4a00-a717-3e43a15232e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708445187 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_halt_resume_whereto.1708445187
Directory /workspace/7.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.893224752
Short name T127
Test name
Test status
Simulation time 2268097905 ps
CPU time 6.16 seconds
Started Aug 11 05:36:10 PM PDT 24
Finished Aug 11 05:36:16 PM PDT 24
Peak memory 205732 kb
Host smart-7cb2dd8f-5dce-47a9-a871-ee8fdbd6fdc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893224752 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.893224752
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_stress_all.994979119
Short name T271
Test name
Test status
Simulation time 2935975292 ps
CPU time 3.47 seconds
Started Aug 11 05:36:23 PM PDT 24
Finished Aug 11 05:36:27 PM PDT 24
Peak memory 205556 kb
Host smart-90ad8ff1-5f1c-49ba-933a-77f9fef7fd27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994979119 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.994979119
Directory /workspace/7.rv_dm_stress_all/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.1544185365
Short name T39
Test name
Test status
Simulation time 59667993 ps
CPU time 0.83 seconds
Started Aug 11 05:36:21 PM PDT 24
Finished Aug 11 05:36:22 PM PDT 24
Peak memory 205296 kb
Host smart-b1a873ae-e17a-4044-9752-4dbe6b8e87ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544185365 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.1544185365
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.2848608856
Short name T183
Test name
Test status
Simulation time 40675112392 ps
CPU time 98.4 seconds
Started Aug 11 05:36:24 PM PDT 24
Finished Aug 11 05:38:03 PM PDT 24
Peak memory 213876 kb
Host smart-bc0869de-1592-4944-bb23-f4b50d2c1101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848608856 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.2848608856
Directory /workspace/8.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.1065229453
Short name T216
Test name
Test status
Simulation time 1687318075 ps
CPU time 3.73 seconds
Started Aug 11 05:36:16 PM PDT 24
Finished Aug 11 05:36:20 PM PDT 24
Peak memory 205420 kb
Host smart-97ce21ec-353b-451e-8427-48fa8d10394b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065229453 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.1065229453
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.3789134703
Short name T296
Test name
Test status
Simulation time 9948179926 ps
CPU time 11.3 seconds
Started Aug 11 05:36:25 PM PDT 24
Finished Aug 11 05:36:37 PM PDT 24
Peak memory 205748 kb
Host smart-da832ead-8a57-4d93-a308-b5e54b3db828
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3789134703 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_t
l_access.3789134703
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.1236359301
Short name T248
Test name
Test status
Simulation time 2054506179 ps
CPU time 2.84 seconds
Started Aug 11 05:36:19 PM PDT 24
Finished Aug 11 05:36:21 PM PDT 24
Peak memory 205520 kb
Host smart-da433ac2-9998-48af-86a8-f04555b07323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236359301 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.1236359301
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_stress_all.4055464861
Short name T2
Test name
Test status
Simulation time 11440876750 ps
CPU time 8.71 seconds
Started Aug 11 05:36:17 PM PDT 24
Finished Aug 11 05:36:26 PM PDT 24
Peak memory 205476 kb
Host smart-f87890ad-7cc7-4fc2-b60a-f0834dc9aadf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055464861 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.4055464861
Directory /workspace/8.rv_dm_stress_all/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.3738593655
Short name T238
Test name
Test status
Simulation time 58794390 ps
CPU time 0.82 seconds
Started Aug 11 05:36:22 PM PDT 24
Finished Aug 11 05:36:23 PM PDT 24
Peak memory 205200 kb
Host smart-c734db98-0fee-449c-955b-ad29cc6a8bf9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738593655 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.3738593655
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.28047220
Short name T287
Test name
Test status
Simulation time 9361227446 ps
CPU time 6.91 seconds
Started Aug 11 05:36:21 PM PDT 24
Finished Aug 11 05:36:28 PM PDT 24
Peak memory 205740 kb
Host smart-fb8760e0-d050-494f-93fb-0e92bd9f8e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28047220 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.28047220
Directory /workspace/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.1461559999
Short name T182
Test name
Test status
Simulation time 2383909209 ps
CPU time 2.44 seconds
Started Aug 11 05:36:16 PM PDT 24
Finished Aug 11 05:36:19 PM PDT 24
Peak memory 213784 kb
Host smart-f580a209-109a-4483-a286-18a13ba159be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461559999 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.1461559999
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.3521309452
Short name T263
Test name
Test status
Simulation time 2346314117 ps
CPU time 4.35 seconds
Started Aug 11 05:36:17 PM PDT 24
Finished Aug 11 05:36:22 PM PDT 24
Peak memory 205788 kb
Host smart-1e8627c9-d934-40e3-b88a-c684b5ef7024
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3521309452 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t
l_access.3521309452
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.4087901029
Short name T212
Test name
Test status
Simulation time 6574240659 ps
CPU time 18.97 seconds
Started Aug 11 05:36:16 PM PDT 24
Finished Aug 11 05:36:35 PM PDT 24
Peak memory 213788 kb
Host smart-3c4f7275-a206-44b8-adfe-b0bc7a4f7dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087901029 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.4087901029
Directory /workspace/9.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_stress_all.2242352944
Short name T141
Test name
Test status
Simulation time 5717559336 ps
CPU time 6.02 seconds
Started Aug 11 05:36:19 PM PDT 24
Finished Aug 11 05:36:25 PM PDT 24
Peak memory 213696 kb
Host smart-c8bd99b7-c710-400e-9a61-e032b39eac87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242352944 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.2242352944
Directory /workspace/9.rv_dm_stress_all/latest

Test location /workspace/coverage/default/9.rv_dm_stress_all_with_rand_reset.4244513569
Short name T33
Test name
Test status
Simulation time 239631975503 ps
CPU time 1646.61 seconds
Started Aug 11 05:36:21 PM PDT 24
Finished Aug 11 06:03:48 PM PDT 24
Peak memory 247624 kb
Host smart-0e381191-fafa-473c-a027-ac12608b15ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244513569 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all_with_rand_reset.4244513569
Directory /workspace/9.rv_dm_stress_all_with_rand_reset/latest
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