Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 232401 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 572798 1 T2 2 T3 3 T4 2302



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 480930 1 T2 2 T3 1 T4 1750
values[0x0] 147299 1 T2 1 T3 2 T4 743
values[0x1] 176970 1 T2 2 T4 1857 T28 7



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 164942 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 640257 1 T2 4 T3 3 T4 3373



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 4392 1 T4 3 T43 21 T38 1
valid_sources[0x01] 3132 1 T4 3 T14 3 T43 28
valid_sources[0x02] 2969 1 T4 5 T43 19 T23 16
valid_sources[0x03] 2785 1 T4 47 T43 18 T23 22
valid_sources[0x04] 3085 1 T4 40 T43 11 T23 21
valid_sources[0x05] 2829 1 T4 9 T43 21 T23 30
valid_sources[0x06] 3021 1 T4 29 T28 1 T19 1
valid_sources[0x07] 2743 1 T4 15 T43 16 T23 28
valid_sources[0x08] 3170 1 T4 112 T43 22 T23 13
valid_sources[0x09] 3581 1 T4 11 T43 14 T23 24
valid_sources[0x0a] 2923 1 T4 25 T43 24 T44 1
valid_sources[0x0b] 7671 1 T4 49 T19 2 T43 21
valid_sources[0x0c] 2868 1 T4 1 T43 21 T44 1
valid_sources[0x0d] 2999 1 T4 20 T43 22 T23 23
valid_sources[0x0e] 2835 1 T4 1 T43 12 T38 2
valid_sources[0x0f] 2939 1 T4 62 T43 19 T101 1
valid_sources[0x10] 2878 1 T4 6 T43 24 T23 12
valid_sources[0x11] 3045 1 T4 29 T43 23 T23 15
valid_sources[0x12] 3188 1 T4 8 T43 21 T6 11
valid_sources[0x13] 2807 1 T4 2 T43 8 T23 29
valid_sources[0x14] 2773 1 T4 19 T28 1 T43 11
valid_sources[0x15] 2863 1 T4 21 T43 17 T100 1
valid_sources[0x16] 3125 1 T4 11 T31 1 T43 13
valid_sources[0x17] 2963 1 T4 17 T43 17 T151 1
valid_sources[0x18] 3118 1 T4 7 T43 10 T38 2
valid_sources[0x19] 2769 1 T4 8 T45 1 T43 21
valid_sources[0x1a] 2856 1 T4 12 T28 1 T43 17
valid_sources[0x1b] 2937 1 T4 25 T43 18 T38 1
valid_sources[0x1c] 3264 1 T4 16 T43 19 T23 20
valid_sources[0x1d] 2943 1 T4 32 T24 1 T43 19
valid_sources[0x1e] 2971 1 T4 26 T43 27 T151 1
valid_sources[0x1f] 3077 1 T4 11 T28 1 T43 19
valid_sources[0x20] 3340 1 T4 46 T43 23 T38 3
valid_sources[0x21] 2955 1 T4 23 T43 18 T23 31
valid_sources[0x22] 3132 1 T43 28 T23 29 T16 68
valid_sources[0x23] 3074 1 T28 1 T43 22 T23 27
valid_sources[0x24] 3014 1 T4 43 T43 18 T23 27
valid_sources[0x25] 3321 1 T4 5 T43 22 T23 17
valid_sources[0x26] 3121 1 T4 13 T43 13 T23 36
valid_sources[0x27] 2862 1 T4 9 T43 18 T23 10
valid_sources[0x28] 3263 1 T4 3 T5 8 T43 18
valid_sources[0x29] 3575 1 T4 9 T43 18 T23 21
valid_sources[0x2a] 2990 1 T4 5 T43 26 T23 23
valid_sources[0x2b] 3281 1 T4 2 T43 15 T23 23
valid_sources[0x2c] 3046 1 T4 3 T43 27 T22 1
valid_sources[0x2d] 2807 1 T4 9 T43 20 T23 22
valid_sources[0x2e] 3257 1 T4 21 T43 25 T23 18
valid_sources[0x2f] 2942 1 T4 9 T83 1 T43 24
valid_sources[0x30] 4262 1 T28 1 T43 10 T23 19
valid_sources[0x31] 2701 1 T4 13 T28 1 T43 27
valid_sources[0x32] 2845 1 T4 19 T43 18 T48 3
valid_sources[0x33] 2939 1 T4 16 T45 1 T43 21
valid_sources[0x34] 2979 1 T4 1 T43 24 T22 1
valid_sources[0x35] 3119 1 T4 120 T43 8 T23 32
valid_sources[0x36] 3285 1 T4 6 T43 18 T23 21
valid_sources[0x37] 2735 1 T4 16 T43 15 T23 22
valid_sources[0x38] 3316 1 T4 6 T43 20 T23 25
valid_sources[0x39] 2882 1 T4 9 T43 17 T23 26
valid_sources[0x3a] 2973 1 T4 24 T138 1 T43 12
valid_sources[0x3b] 2814 1 T4 4 T43 24 T23 21
valid_sources[0x3c] 2682 1 T4 9 T45 1 T43 18
valid_sources[0x3d] 3198 1 T4 7 T14 1 T43 22
valid_sources[0x3e] 3060 1 T4 6 T43 22 T23 19
valid_sources[0x3f] 3288 1 T43 18 T23 22 T164 2
valid_sources[0x40] 2881 1 T4 18 T43 19 T23 28
valid_sources[0x41] 2976 1 T45 1 T43 21 T38 2
valid_sources[0x42] 2841 1 T4 19 T43 22 T23 25
valid_sources[0x43] 3190 1 T4 11 T43 16 T23 17
valid_sources[0x44] 3330 1 T4 3 T43 18 T23 23
valid_sources[0x45] 3176 1 T4 12 T43 17 T23 20
valid_sources[0x46] 2890 1 T4 5 T43 18 T23 30
valid_sources[0x47] 2944 1 T4 34 T28 1 T43 24
valid_sources[0x48] 2766 1 T4 14 T29 7 T43 21
valid_sources[0x49] 2865 1 T4 26 T43 19 T23 17
valid_sources[0x4a] 3382 1 T4 20 T43 7 T23 14
valid_sources[0x4b] 3095 1 T4 12 T14 1 T43 17
valid_sources[0x4c] 3051 1 T4 17 T43 16 T23 25
valid_sources[0x4d] 3267 1 T4 28 T43 13 T151 2
valid_sources[0x4e] 2887 1 T14 1 T43 20 T23 25
valid_sources[0x4f] 2855 1 T4 16 T83 1 T43 20
valid_sources[0x50] 3005 1 T4 4 T15 3 T43 21
valid_sources[0x51] 3057 1 T4 7 T31 2 T43 18
valid_sources[0x52] 2908 1 T4 6 T15 1 T43 25
valid_sources[0x53] 3007 1 T4 27 T43 22 T38 2
valid_sources[0x54] 3246 1 T4 9 T43 18 T38 1
valid_sources[0x55] 3362 1 T4 19 T43 11 T101 2
valid_sources[0x56] 3031 1 T4 12 T43 21 T38 1
valid_sources[0x57] 3275 1 T4 44 T43 22 T23 18
valid_sources[0x58] 2730 1 T4 9 T43 17 T38 1
valid_sources[0x59] 2980 1 T4 25 T14 2 T43 18
valid_sources[0x5a] 3306 1 T4 18 T43 17 T38 1
valid_sources[0x5b] 3007 1 T4 26 T43 12 T23 35
valid_sources[0x5c] 3300 1 T4 4 T45 1 T43 18
valid_sources[0x5d] 2810 1 T4 1 T43 17 T38 1
valid_sources[0x5e] 3260 1 T4 22 T43 24 T23 21
valid_sources[0x5f] 3143 1 T4 22 T28 1 T43 18
valid_sources[0x60] 3275 1 T4 66 T43 20 T23 33
valid_sources[0x61] 3478 1 T4 150 T43 15 T23 18
valid_sources[0x62] 3037 1 T4 63 T43 20 T23 30
valid_sources[0x63] 2998 1 T4 17 T43 15 T9 2
valid_sources[0x64] 2946 1 T4 10 T43 20 T23 19
valid_sources[0x65] 2999 1 T4 11 T43 23 T38 1
valid_sources[0x66] 2994 1 T4 1 T43 19 T23 22
valid_sources[0x67] 2776 1 T4 11 T43 20 T23 14
valid_sources[0x68] 2888 1 T4 21 T43 20 T23 21
valid_sources[0x69] 4165 1 T4 21 T43 25 T23 22
valid_sources[0x6a] 3186 1 T4 6 T43 24 T23 30
valid_sources[0x6b] 3142 1 T4 10 T43 19 T23 25
valid_sources[0x6c] 2839 1 T4 2 T43 9 T23 30
valid_sources[0x6d] 2951 1 T3 3 T4 9 T43 12
valid_sources[0x6e] 3186 1 T4 83 T43 29 T38 4
valid_sources[0x6f] 3430 1 T4 17 T43 21 T23 24
valid_sources[0x70] 3968 1 T28 2 T43 22 T23 21
valid_sources[0x71] 2958 1 T4 6 T43 20 T23 24
valid_sources[0x72] 2939 1 T4 9 T43 23 T23 24
valid_sources[0x73] 2947 1 T4 18 T43 17 T23 22
valid_sources[0x74] 2960 1 T4 9 T43 27 T23 21
valid_sources[0x75] 2890 1 T4 8 T43 13 T38 1
valid_sources[0x76] 2984 1 T4 17 T43 22 T23 22
valid_sources[0x77] 3228 1 T4 9 T43 17 T100 1
valid_sources[0x78] 3566 1 T4 11 T43 20 T22 1
valid_sources[0x79] 2975 1 T4 14 T43 27 T38 3
valid_sources[0x7a] 3124 1 T4 15 T43 16 T23 24
valid_sources[0x7b] 2826 1 T4 16 T43 13 T23 20
valid_sources[0x7c] 2746 1 T4 2 T13 2 T43 8
valid_sources[0x7d] 3088 1 T43 17 T23 20 T16 46
valid_sources[0x7e] 3025 1 T4 22 T43 19 T23 16
valid_sources[0x7f] 3031 1 T4 18 T28 1 T43 13
valid_sources[0x80] 3155 1 T4 6 T43 15 T38 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 287034 1 T3 1 T4 1061 T28 4
values[0x0] all_enables biggest_size 142878 1 T2 1 T3 2 T4 623
values[0x1] all_enables biggest_size 142886 1 T2 1 T4 618 T28 2


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 6368 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 62843 1 T2 7 T3 6 T32 3



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 20537 1 T4 615 T43 698 T23 1170
values[0x0] 23524 1 T2 3 T3 3 T32 7
values[0x1] 25150 1 T2 4 T3 3 T32 4



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 4354 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 64857 1 T2 7 T3 6 T32 4



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 185 1 T4 7 T66 1 T43 1
valid_sources[0x01] 517 1 T4 7 T136 2 T43 10
valid_sources[0x02] 188 1 T4 10 T43 1 T16 58
valid_sources[0x03] 491 1 T4 12 T43 1 T23 134
valid_sources[0x04] 170 1 T4 5 T151 1 T157 1
valid_sources[0x05] 170 1 T4 9 T16 44 T41 4
valid_sources[0x06] 584 1 T4 14 T137 1 T23 404
valid_sources[0x07] 271 1 T4 7 T43 5 T151 1
valid_sources[0x08] 168 1 T4 10 T178 2 T179 3
valid_sources[0x09] 378 1 T4 12 T43 20 T16 40
valid_sources[0x0a] 318 1 T4 5 T13 1 T43 1
valid_sources[0x0b] 179 1 T4 9 T24 1 T180 1
valid_sources[0x0c] 374 1 T4 6 T43 32 T16 41
valid_sources[0x0d] 206 1 T4 6 T43 22 T16 55
valid_sources[0x0e] 183 1 T4 13 T43 11 T181 1
valid_sources[0x0f] 277 1 T4 10 T7 1 T16 41
valid_sources[0x10] 256 1 T4 14 T43 8 T16 37
valid_sources[0x11] 228 1 T4 6 T16 50 T41 28
valid_sources[0x12] 330 1 T4 9 T16 40 T41 3
valid_sources[0x13] 223 1 T4 4 T43 54 T182 1
valid_sources[0x14] 422 1 T4 6 T51 1 T43 1
valid_sources[0x15] 245 1 T4 9 T43 39 T16 40
valid_sources[0x16] 274 1 T4 4 T108 1 T7 1
valid_sources[0x17] 172 1 T4 7 T43 33 T181 2
valid_sources[0x18] 676 1 T4 8 T43 5 T23 483
valid_sources[0x19] 203 1 T4 11 T136 2 T183 1
valid_sources[0x1a] 452 1 T4 15 T43 59 T99 1
valid_sources[0x1b] 152 1 T4 7 T43 6 T16 42
valid_sources[0x1c] 280 1 T4 10 T43 1 T16 52
valid_sources[0x1d] 216 1 T4 12 T136 3 T43 2
valid_sources[0x1e] 153 1 T4 5 T16 40 T103 16
valid_sources[0x1f] 170 1 T4 14 T43 7 T16 40
valid_sources[0x20] 220 1 T4 6 T51 1 T43 8
valid_sources[0x21] 193 1 T4 6 T43 27 T180 1
valid_sources[0x22] 256 1 T4 11 T136 1 T19 1
valid_sources[0x23] 166 1 T4 7 T35 2 T184 1
valid_sources[0x24] 374 1 T4 6 T43 10 T23 1
valid_sources[0x25] 227 1 T4 4 T43 13 T16 42
valid_sources[0x26] 289 1 T4 6 T43 14 T9 1
valid_sources[0x27] 165 1 T4 10 T43 12 T16 58
valid_sources[0x28] 157 1 T4 4 T51 1 T55 1
valid_sources[0x29] 348 1 T4 10 T58 1 T43 37
valid_sources[0x2a] 217 1 T4 11 T43 11 T44 2
valid_sources[0x2b] 293 1 T4 10 T185 1 T154 1
valid_sources[0x2c] 160 1 T4 8 T16 53 T41 2
valid_sources[0x2d] 200 1 T4 12 T43 21 T16 47
valid_sources[0x2e] 340 1 T4 8 T16 52 T41 160
valid_sources[0x2f] 312 1 T4 8 T43 19 T6 1
valid_sources[0x30] 390 1 T4 8 T16 45 T41 215
valid_sources[0x31] 171 1 T4 13 T35 1 T43 1
valid_sources[0x32] 165 1 T4 10 T35 3 T43 4
valid_sources[0x33] 445 1 T4 17 T43 29 T185 1
valid_sources[0x34] 377 1 T4 9 T43 3 T179 1
valid_sources[0x35] 262 1 T4 13 T43 1 T23 87
valid_sources[0x36] 188 1 T4 11 T43 10 T158 1
valid_sources[0x37] 148 1 T4 12 T51 1 T16 34
valid_sources[0x38] 180 1 T4 17 T165 1 T16 35
valid_sources[0x39] 186 1 T4 11 T43 4 T16 39
valid_sources[0x3a] 487 1 T4 8 T43 3 T23 257
valid_sources[0x3b] 262 1 T4 6 T43 3 T16 34
valid_sources[0x3c] 346 1 T4 7 T82 2 T23 1
valid_sources[0x3d] 204 1 T4 11 T5 1 T137 1
valid_sources[0x3e] 403 1 T4 12 T28 1 T43 34
valid_sources[0x3f] 173 1 T4 13 T20 1 T43 1
valid_sources[0x40] 197 1 T4 12 T28 1 T8 1
valid_sources[0x41] 193 1 T4 2 T43 2 T186 1
valid_sources[0x42] 614 1 T4 6 T83 1 T180 1
valid_sources[0x43] 276 1 T4 11 T43 4 T16 45
valid_sources[0x44] 188 1 T4 8 T43 18 T183 1
valid_sources[0x45] 167 1 T4 9 T43 2 T185 1
valid_sources[0x46] 186 1 T4 8 T5 1 T16 49
valid_sources[0x47] 228 1 T4 13 T43 25 T16 38
valid_sources[0x48] 343 1 T4 11 T19 1 T43 23
valid_sources[0x49] 397 1 T4 15 T138 1 T43 29
valid_sources[0x4a] 251 1 T32 11 T4 5 T43 28
valid_sources[0x4b] 192 1 T4 5 T43 11 T16 53
valid_sources[0x4c] 195 1 T4 7 T43 2 T179 2
valid_sources[0x4d] 174 1 T4 8 T33 1 T82 1
valid_sources[0x4e] 384 1 T4 9 T43 30 T186 1
valid_sources[0x4f] 311 1 T4 13 T43 22 T16 57
valid_sources[0x50] 311 1 T4 9 T43 1 T16 46
valid_sources[0x51] 178 1 T4 16 T24 1 T15 4
valid_sources[0x52] 167 1 T4 5 T151 1 T23 2
valid_sources[0x53] 298 1 T4 6 T20 1 T6 1
valid_sources[0x54] 478 1 T4 10 T160 1 T16 44
valid_sources[0x55] 339 1 T4 8 T16 38 T41 166
valid_sources[0x56] 355 1 T4 7 T23 135 T16 37
valid_sources[0x57] 308 1 T4 10 T28 1 T31 2
valid_sources[0x58] 425 1 T4 18 T8 1 T16 45
valid_sources[0x59] 336 1 T4 12 T43 7 T16 48
valid_sources[0x5a] 177 1 T4 8 T14 2 T23 2
valid_sources[0x5b] 267 1 T4 7 T43 32 T187 1
valid_sources[0x5c] 213 1 T4 11 T31 1 T43 15
valid_sources[0x5d] 148 1 T4 12 T43 6 T16 28
valid_sources[0x5e] 291 1 T4 11 T35 1 T43 15
valid_sources[0x5f] 317 1 T4 8 T28 2 T5 1
valid_sources[0x60] 178 1 T4 6 T43 23 T7 1
valid_sources[0x61] 234 1 T4 10 T21 1 T43 1
valid_sources[0x62] 306 1 T4 8 T51 1 T31 1
valid_sources[0x63] 319 1 T4 9 T43 5 T7 1
valid_sources[0x64] 288 1 T4 6 T82 1 T15 1
valid_sources[0x65] 187 1 T4 8 T51 1 T43 2
valid_sources[0x66] 197 1 T4 10 T31 1 T188 12
valid_sources[0x67] 397 1 T4 7 T43 6 T16 39
valid_sources[0x68] 185 1 T3 2 T4 12 T178 2
valid_sources[0x69] 406 1 T4 11 T43 72 T16 40
valid_sources[0x6a] 312 1 T4 7 T43 8 T99 1
valid_sources[0x6b] 164 1 T4 3 T51 2 T187 1
valid_sources[0x6c] 207 1 T4 7 T43 35 T16 37
valid_sources[0x6d] 188 1 T4 21 T43 3 T154 1
valid_sources[0x6e] 249 1 T4 11 T43 44 T16 66
valid_sources[0x6f] 422 1 T4 11 T43 1 T186 1
valid_sources[0x70] 209 1 T4 12 T5 1 T43 2
valid_sources[0x71] 267 1 T4 5 T43 40 T16 44
valid_sources[0x72] 176 1 T4 4 T43 7 T102 2
valid_sources[0x73] 577 1 T4 14 T43 32 T23 112
valid_sources[0x74] 267 1 T4 15 T14 1 T43 5
valid_sources[0x75] 166 1 T4 9 T6 1 T16 47
valid_sources[0x76] 176 1 T4 11 T5 1 T15 2
valid_sources[0x77] 467 1 T4 12 T43 13 T102 1
valid_sources[0x78] 170 1 T4 17 T43 4 T186 1
valid_sources[0x79] 158 1 T4 7 T43 2 T16 34
valid_sources[0x7a] 259 1 T4 10 T43 7 T9 1
valid_sources[0x7b] 330 1 T4 10 T43 65 T16 42
valid_sources[0x7c] 181 1 T4 10 T24 1 T16 43
valid_sources[0x7d] 150 1 T4 9 T16 32 T163 3
valid_sources[0x7e] 166 1 T4 13 T43 12 T16 33
valid_sources[0x7f] 332 1 T4 14 T136 1 T43 36
valid_sources[0x80] 178 1 T4 6 T17 1 T5 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 17298 1 T4 584 T43 654 T23 1134
values[0x0] all_enables biggest_size 22655 1 T2 3 T3 3 T32 3
values[0x1] all_enables biggest_size 22890 1 T2 4 T3 3 T4 919

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%