SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[rv_dm_mem_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[rv_dm_regs_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 948539 | 1 | T2 | 5 | T3 | 3 | T4 | 9627 | ||||
auto[1] | 99912 | 1 | T4 | 3945 | T43 | 4918 | T38 | 80 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 1048250 | 1 | T2 | 5 | T3 | 3 | T4 | 13572 | ||||
values[1] | 16 | 1 | T143 | 1 | T166 | 2 | T167 | 3 | ||||
values[2] | 1 | 1 | T168 | 1 | - | - | - | - | ||||
values[3] | 109 | 1 | T104 | 8 | T98 | 4 | T143 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 1048255 | 1 | T2 | 5 | T3 | 3 | T4 | 13572 | ||||
values[1] | 29 | 1 | T104 | 2 | T98 | 2 | T169 | 1 | ||||
values[2] | 3 | 1 | T170 | 1 | T171 | 1 | T172 | 1 | ||||
values[3] | 100 | 1 | T104 | 2 | T98 | 6 | T143 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 1048161 | 1 | T2 | 5 | T3 | 3 | T4 | 13572 | ||||
auto[TlIntgErrCmd] | 94 | 1 | T104 | 5 | T98 | 4 | T143 | 3 | ||||
auto[TlIntgErrData] | 89 | 1 | T104 | 2 | T98 | 10 | T143 | 3 | ||||
auto[TlIntgErrBoth] | 107 | 1 | T104 | 3 | T98 | 6 | T143 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[0] | 168424 | 0 | T2 | 7 | T3 | 6 | T32 | 11 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 168235 | 1 | T2 | 7 | T3 | 6 | T32 | 11 | ||||
values[1] | 17 | 1 | T98 | 1 | T169 | 2 | T173 | 1 | ||||
values[2] | 5 | 1 | T166 | 1 | T69 | 2 | T75 | 2 | ||||
values[3] | 91 | 1 | T104 | 6 | T98 | 3 | T143 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 168222 | 1 | T2 | 7 | T3 | 6 | T32 | 11 | ||||
values[1] | 22 | 1 | T104 | 2 | T98 | 1 | T143 | 1 | ||||
values[2] | 4 | 1 | T98 | 2 | T173 | 1 | T76 | 1 | ||||
values[3] | 105 | 1 | T104 | 3 | T98 | 9 | T143 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 168134 | 1 | T2 | 7 | T3 | 6 | T32 | 11 | ||||
auto[TlIntgErrCmd] | 88 | 1 | T104 | 3 | T98 | 5 | T143 | 4 | ||||
auto[TlIntgErrData] | 101 | 1 | T104 | 3 | T98 | 9 | T143 | 5 | ||||
auto[TlIntgErrBoth] | 101 | 1 | T104 | 4 | T98 | 6 | T143 | 1 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |