Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

466989

1

T2

3

T4

10928

T28

13

full_word

581462

1

T2

2

T3

3

T4

2644

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	1048161	1			T2	5		T3	3		T4	13572
auto[TlIntgErrCmd]	94	1			T104	5		T98	4		T143	3
auto[TlIntgErrData]	89	1			T104	2		T98	10		T143	3
auto[TlIntgErrBoth]	107	1			T104	3		T98	6		T143	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

491239

1

T2

2

T3

1

T4

2126

auto[1]

557212

1

T2

3

T3

2

T4

11446

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	203094	1			T2	2		T4	1034		T28	4
auto[TlIntgErrNone]	partial	auto[1]	263638	1			T2	1		T4	9894		T28	9
auto[TlIntgErrNone]	full_word	auto[0]	288002	1			T3	1		T4	1092		T28	4
auto[TlIntgErrNone]	full_word	auto[1]	293427	1			T2	2		T3	2		T4	1552
auto[TlIntgErrCmd]	partial	auto[0]	34	1			T104	3		T98	2		T169	1
auto[TlIntgErrCmd]	partial	auto[1]	50	1			T104	1		T98	2		T143	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T104	1		T166	1		T167	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T143	1		T169	1		T173	1
auto[TlIntgErrData]	partial	auto[0]	43	1			T104	2		T98	6		T143	1
auto[TlIntgErrData]	partial	auto[1]	34	1			T98	1		T143	2		T174	2
auto[TlIntgErrData]	full_word	auto[0]	5	1			T98	1		T170	1		T69	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T98	2		T173	1		T75	1
auto[TlIntgErrBoth]	partial	auto[0]	53	1			T98	2		T143	4		T169	4
auto[TlIntgErrBoth]	partial	auto[1]	43	1			T104	3		T98	4		T169	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T170	2		T75	1		T72	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T170	1		T175	2		T176	2