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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
88.14 96.32 87.27 92.10 93.59 90.44 98.74 58.53


Total test records in report: 482
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T323 /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.3828524475 Aug 13 05:36:10 PM PDT 24 Aug 13 05:36:13 PM PDT 24 2925313862 ps
T96 /workspace/coverage/default/0.rv_dm_sba_debug_disabled.3180820070 Aug 13 05:35:50 PM PDT 24 Aug 13 05:35:53 PM PDT 24 861057560 ps
T45 /workspace/coverage/default/0.rv_dm_rom_read_access.2404633816 Aug 13 05:35:56 PM PDT 24 Aug 13 05:35:57 PM PDT 24 50793814 ps
T324 /workspace/coverage/default/47.rv_dm_stress_all.1928175568 Aug 13 05:36:39 PM PDT 24 Aug 13 05:36:49 PM PDT 24 3231373382 ps
T325 /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.3061914928 Aug 13 05:36:12 PM PDT 24 Aug 13 05:36:14 PM PDT 24 870985555 ps
T326 /workspace/coverage/default/40.rv_dm_stress_all.1594593901 Aug 13 05:36:38 PM PDT 24 Aug 13 05:36:41 PM PDT 24 2157996095 ps
T327 /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.972113353 Aug 13 05:36:34 PM PDT 24 Aug 13 05:36:43 PM PDT 24 2886521008 ps
T328 /workspace/coverage/default/14.rv_dm_alert_test.3687935140 Aug 13 05:36:29 PM PDT 24 Aug 13 05:36:30 PM PDT 24 153408247 ps
T329 /workspace/coverage/default/1.rv_dm_ndmreset_req.4195435899 Aug 13 05:35:54 PM PDT 24 Aug 13 05:35:56 PM PDT 24 396341245 ps
T330 /workspace/coverage/default/4.rv_dm_hart_unavail.3698297338 Aug 13 05:36:06 PM PDT 24 Aug 13 05:36:07 PM PDT 24 325491343 ps
T331 /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.2232031684 Aug 13 05:36:10 PM PDT 24 Aug 13 05:36:28 PM PDT 24 12555061796 ps
T61 /workspace/coverage/default/1.rv_dm_dmi_failed_op.2622395210 Aug 13 05:36:15 PM PDT 24 Aug 13 05:36:16 PM PDT 24 724491891 ps
T332 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.626741815 Aug 13 05:35:52 PM PDT 24 Aug 13 05:35:55 PM PDT 24 237656250 ps
T333 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.3547108484 Aug 13 05:35:25 PM PDT 24 Aug 13 05:35:26 PM PDT 24 102161704 ps
T103 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.185135450 Aug 13 05:35:52 PM PDT 24 Aug 13 05:35:54 PM PDT 24 107049835 ps
T119 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.997827089 Aug 13 05:35:22 PM PDT 24 Aug 13 05:35:23 PM PDT 24 272490902 ps
T160 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3449886718 Aug 13 05:35:53 PM PDT 24 Aug 13 05:35:55 PM PDT 24 529713278 ps
T125 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.3286387659 Aug 13 05:35:32 PM PDT 24 Aug 13 05:36:52 PM PDT 24 80724503364 ps
T126 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.2865578939 Aug 13 05:35:49 PM PDT 24 Aug 13 05:35:51 PM PDT 24 255243970 ps
T334 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.388362680 Aug 13 05:35:50 PM PDT 24 Aug 13 05:35:55 PM PDT 24 315442907 ps
T161 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.4174787904 Aug 13 05:35:22 PM PDT 24 Aug 13 05:35:29 PM PDT 24 501133713 ps
T163 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.2159365895 Aug 13 05:35:47 PM PDT 24 Aug 13 05:36:03 PM PDT 24 1734146853 ps
T162 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.3158137584 Aug 13 05:36:08 PM PDT 24 Aug 13 05:36:11 PM PDT 24 237816430 ps
T164 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.1792398780 Aug 13 05:35:25 PM PDT 24 Aug 13 05:35:47 PM PDT 24 2717832769 ps
T127 /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.1477685189 Aug 13 05:35:52 PM PDT 24 Aug 13 05:35:55 PM PDT 24 136754832 ps
T120 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.2546694428 Aug 13 05:35:27 PM PDT 24 Aug 13 05:35:29 PM PDT 24 752899754 ps
T121 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.926946179 Aug 13 05:35:14 PM PDT 24 Aug 13 05:35:16 PM PDT 24 357213834 ps
T128 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.3660835336 Aug 13 05:35:22 PM PDT 24 Aug 13 05:35:24 PM PDT 24 111404014 ps
T129 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.747232046 Aug 13 05:35:51 PM PDT 24 Aug 13 05:35:56 PM PDT 24 240414838 ps
T165 /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.2604178237 Aug 13 05:35:52 PM PDT 24 Aug 13 05:36:11 PM PDT 24 4465606250 ps
T335 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.2834879766 Aug 13 05:35:28 PM PDT 24 Aug 13 05:35:29 PM PDT 24 28955883 ps
T336 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.1540347999 Aug 13 05:35:22 PM PDT 24 Aug 13 05:40:27 PM PDT 24 222695241732 ps
T337 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.3465081900 Aug 13 05:35:29 PM PDT 24 Aug 13 05:35:34 PM PDT 24 2360540310 ps
T97 /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.846301425 Aug 13 05:35:48 PM PDT 24 Aug 13 05:36:46 PM PDT 24 17518090670 ps
T338 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.1765052358 Aug 13 05:35:46 PM PDT 24 Aug 13 05:35:52 PM PDT 24 3303504212 ps
T339 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.1620925896 Aug 13 05:35:28 PM PDT 24 Aug 13 05:37:25 PM PDT 24 93622177855 ps
T340 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.2290123066 Aug 13 05:35:54 PM PDT 24 Aug 13 05:35:56 PM PDT 24 59717762 ps
T341 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.1451885803 Aug 13 05:35:46 PM PDT 24 Aug 13 05:36:26 PM PDT 24 27625617866 ps
T192 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3411762895 Aug 13 05:35:44 PM PDT 24 Aug 13 05:35:54 PM PDT 24 2072233775 ps
T342 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.4136811469 Aug 13 05:35:34 PM PDT 24 Aug 13 05:35:54 PM PDT 24 21340422432 ps
T343 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.572867316 Aug 13 05:35:59 PM PDT 24 Aug 13 05:36:00 PM PDT 24 114113355 ps
T344 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.723362085 Aug 13 05:35:52 PM PDT 24 Aug 13 05:35:57 PM PDT 24 2318202943 ps
T345 /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.1752076486 Aug 13 05:35:43 PM PDT 24 Aug 13 05:35:48 PM PDT 24 203350290 ps
T346 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.3628675843 Aug 13 05:35:52 PM PDT 24 Aug 13 05:35:54 PM PDT 24 136317022 ps
T347 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.3887324212 Aug 13 05:35:28 PM PDT 24 Aug 13 05:36:56 PM PDT 24 70618460098 ps
T348 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.1928709122 Aug 13 05:35:54 PM PDT 24 Aug 13 05:35:58 PM PDT 24 2991038987 ps
T349 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.3219427595 Aug 13 05:35:54 PM PDT 24 Aug 13 05:36:00 PM PDT 24 139262665 ps
T107 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.640867527 Aug 13 05:35:46 PM PDT 24 Aug 13 05:35:50 PM PDT 24 116204617 ps
T350 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.4110626865 Aug 13 05:35:20 PM PDT 24 Aug 13 05:35:21 PM PDT 24 38245377 ps
T351 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.2207180786 Aug 13 05:35:34 PM PDT 24 Aug 13 05:35:40 PM PDT 24 4940409947 ps
T352 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.2973948355 Aug 13 05:35:46 PM PDT 24 Aug 13 05:35:47 PM PDT 24 105461242 ps
T130 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.2732156416 Aug 13 05:35:47 PM PDT 24 Aug 13 05:35:49 PM PDT 24 155420757 ps
T131 /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1094281765 Aug 13 05:35:51 PM PDT 24 Aug 13 05:35:58 PM PDT 24 614487873 ps
T353 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3593710744 Aug 13 05:35:22 PM PDT 24 Aug 13 05:35:24 PM PDT 24 289059188 ps
T132 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.299185702 Aug 13 05:35:24 PM PDT 24 Aug 13 05:36:16 PM PDT 24 1449035556 ps
T354 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.3445977563 Aug 13 05:35:23 PM PDT 24 Aug 13 05:35:26 PM PDT 24 929875300 ps
T355 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.4264906238 Aug 13 05:35:50 PM PDT 24 Aug 13 05:35:58 PM PDT 24 2113368757 ps
T133 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3325449308 Aug 13 05:35:25 PM PDT 24 Aug 13 05:35:28 PM PDT 24 144292150 ps
T356 /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.2060532265 Aug 13 05:35:23 PM PDT 24 Aug 13 05:35:59 PM PDT 24 2726177768 ps
T134 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.1128234441 Aug 13 05:35:21 PM PDT 24 Aug 13 05:35:23 PM PDT 24 203147245 ps
T140 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.1034278848 Aug 13 05:35:48 PM PDT 24 Aug 13 05:35:56 PM PDT 24 1159463089 ps
T357 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.812995388 Aug 13 05:35:50 PM PDT 24 Aug 13 05:36:26 PM PDT 24 31419494304 ps
T358 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1003367687 Aug 13 05:35:51 PM PDT 24 Aug 13 05:35:54 PM PDT 24 585870016 ps
T359 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.2758294802 Aug 13 05:35:45 PM PDT 24 Aug 13 05:35:46 PM PDT 24 49607636 ps
T105 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.3241751528 Aug 13 05:35:53 PM PDT 24 Aug 13 05:35:55 PM PDT 24 152878025 ps
T188 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.304451020 Aug 13 05:35:44 PM PDT 24 Aug 13 05:35:55 PM PDT 24 1182456444 ps
T360 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2990532782 Aug 13 05:35:52 PM PDT 24 Aug 13 05:35:55 PM PDT 24 214826890 ps
T141 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.1241138108 Aug 13 05:35:52 PM PDT 24 Aug 13 05:36:00 PM PDT 24 948585767 ps
T361 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.475193581 Aug 13 05:35:14 PM PDT 24 Aug 13 05:35:27 PM PDT 24 4680667526 ps
T362 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.2643022934 Aug 13 05:35:47 PM PDT 24 Aug 13 05:35:54 PM PDT 24 1049269225 ps
T363 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2798353904 Aug 13 05:35:30 PM PDT 24 Aug 13 05:35:50 PM PDT 24 22522545071 ps
T364 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.3177840185 Aug 13 05:35:33 PM PDT 24 Aug 13 05:35:39 PM PDT 24 6645216697 ps
T155 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.683624377 Aug 13 05:35:25 PM PDT 24 Aug 13 05:35:33 PM PDT 24 614285751 ps
T365 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.3903576348 Aug 13 05:35:22 PM PDT 24 Aug 13 05:35:28 PM PDT 24 5887064939 ps
T366 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.2734667891 Aug 13 05:35:23 PM PDT 24 Aug 13 05:35:57 PM PDT 24 2574559769 ps
T367 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.3803360151 Aug 13 05:35:46 PM PDT 24 Aug 13 05:35:57 PM PDT 24 3545018709 ps
T368 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.2270309383 Aug 13 05:35:47 PM PDT 24 Aug 13 05:39:30 PM PDT 24 86525694485 ps
T186 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3316242883 Aug 13 05:35:44 PM PDT 24 Aug 13 05:35:55 PM PDT 24 1242808474 ps
T369 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.3995191685 Aug 13 05:35:48 PM PDT 24 Aug 13 05:35:54 PM PDT 24 239327603 ps
T135 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.1049637713 Aug 13 05:35:14 PM PDT 24 Aug 13 05:35:16 PM PDT 24 4671349664 ps
T118 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.2290298597 Aug 13 05:35:50 PM PDT 24 Aug 13 05:35:53 PM PDT 24 112563218 ps
T370 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.1829659842 Aug 13 05:35:46 PM PDT 24 Aug 13 05:35:48 PM PDT 24 631791315 ps
T371 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.3076118975 Aug 13 05:35:45 PM PDT 24 Aug 13 05:35:49 PM PDT 24 1307867099 ps
T372 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.3016756640 Aug 13 05:35:52 PM PDT 24 Aug 13 05:35:55 PM PDT 24 56869220 ps
T373 /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.2211996740 Aug 13 05:35:27 PM PDT 24 Aug 13 05:35:31 PM PDT 24 259536169 ps
T113 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.2985128752 Aug 13 05:35:44 PM PDT 24 Aug 13 05:35:47 PM PDT 24 158388846 ps
T374 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.1595921235 Aug 13 05:35:26 PM PDT 24 Aug 13 05:35:32 PM PDT 24 2393022911 ps
T375 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.3761885455 Aug 13 05:35:33 PM PDT 24 Aug 13 05:35:34 PM PDT 24 120034537 ps
T112 /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.2384888871 Aug 13 05:35:46 PM PDT 24 Aug 13 05:35:48 PM PDT 24 57459574 ps
T194 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3288031607 Aug 13 05:35:28 PM PDT 24 Aug 13 05:35:51 PM PDT 24 6947364728 ps
T376 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.2142629431 Aug 13 05:35:46 PM PDT 24 Aug 13 05:35:49 PM PDT 24 181166074 ps
T377 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.3250262405 Aug 13 05:35:34 PM PDT 24 Aug 13 05:35:36 PM PDT 24 139723412 ps
T142 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.3522378021 Aug 13 05:35:45 PM PDT 24 Aug 13 05:35:54 PM PDT 24 2254403342 ps
T378 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.622217808 Aug 13 05:35:21 PM PDT 24 Aug 13 05:35:51 PM PDT 24 38409539849 ps
T379 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.3173930534 Aug 13 05:35:46 PM PDT 24 Aug 13 05:35:48 PM PDT 24 998957786 ps
T149 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.429016812 Aug 13 05:35:28 PM PDT 24 Aug 13 05:35:30 PM PDT 24 137931697 ps
T193 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.4218858567 Aug 13 05:35:52 PM PDT 24 Aug 13 05:36:03 PM PDT 24 1925031197 ps
T380 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.1684824446 Aug 13 05:35:47 PM PDT 24 Aug 13 05:36:28 PM PDT 24 12821059262 ps
T150 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.125046569 Aug 13 05:35:23 PM PDT 24 Aug 13 05:35:50 PM PDT 24 2176416369 ps
T189 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.3726061714 Aug 13 05:35:20 PM PDT 24 Aug 13 05:35:38 PM PDT 24 1285126789 ps
T381 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3018089340 Aug 13 05:35:21 PM PDT 24 Aug 13 05:35:23 PM PDT 24 495204927 ps
T382 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1768650359 Aug 13 05:35:26 PM PDT 24 Aug 13 05:35:27 PM PDT 24 105537445 ps
T383 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.3200392012 Aug 13 05:35:52 PM PDT 24 Aug 13 05:35:59 PM PDT 24 3474484121 ps
T151 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.1030416187 Aug 13 05:35:13 PM PDT 24 Aug 13 05:35:16 PM PDT 24 105535226 ps
T384 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.2464448808 Aug 13 05:35:28 PM PDT 24 Aug 13 05:36:04 PM PDT 24 21440131765 ps
T385 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.1492081962 Aug 13 05:35:25 PM PDT 24 Aug 13 05:35:57 PM PDT 24 5221766196 ps
T136 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.4019507888 Aug 13 05:35:29 PM PDT 24 Aug 13 05:35:33 PM PDT 24 3393305980 ps
T386 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1811258750 Aug 13 05:35:21 PM PDT 24 Aug 13 05:36:01 PM PDT 24 48850535810 ps
T387 /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.1567020411 Aug 13 05:35:46 PM PDT 24 Aug 13 05:35:49 PM PDT 24 225862181 ps
T388 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.1710837128 Aug 13 05:35:22 PM PDT 24 Aug 13 05:35:24 PM PDT 24 440357896 ps
T389 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3059546811 Aug 13 05:35:50 PM PDT 24 Aug 13 05:35:59 PM PDT 24 3177567096 ps
T390 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.1456415917 Aug 13 05:35:25 PM PDT 24 Aug 13 05:35:28 PM PDT 24 183713410 ps
T156 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.178444652 Aug 13 05:35:52 PM PDT 24 Aug 13 05:35:59 PM PDT 24 183625432 ps
T391 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.2926793393 Aug 13 05:35:21 PM PDT 24 Aug 13 05:35:23 PM PDT 24 172743863 ps
T143 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.3176277407 Aug 13 05:35:50 PM PDT 24 Aug 13 05:35:51 PM PDT 24 191587111 ps
T152 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.692533439 Aug 13 05:35:59 PM PDT 24 Aug 13 05:36:01 PM PDT 24 85571972 ps
T392 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.3746750304 Aug 13 05:35:30 PM PDT 24 Aug 13 05:35:58 PM PDT 24 9652830481 ps
T393 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2787307989 Aug 13 05:35:54 PM PDT 24 Aug 13 05:36:00 PM PDT 24 1959274856 ps
T394 /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.944365687 Aug 13 05:35:46 PM PDT 24 Aug 13 05:35:53 PM PDT 24 335529490 ps
T395 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.1620279994 Aug 13 05:35:44 PM PDT 24 Aug 13 05:35:45 PM PDT 24 85050960 ps
T396 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.752145189 Aug 13 05:35:47 PM PDT 24 Aug 13 05:35:48 PM PDT 24 344434551 ps
T157 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2289667623 Aug 13 05:35:51 PM PDT 24 Aug 13 05:35:58 PM PDT 24 557247131 ps
T397 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.2559610233 Aug 13 05:35:47 PM PDT 24 Aug 13 05:35:55 PM PDT 24 3906457630 ps
T158 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.1140865031 Aug 13 05:35:52 PM PDT 24 Aug 13 05:35:57 PM PDT 24 298826862 ps
T398 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.3006398099 Aug 13 05:35:44 PM PDT 24 Aug 13 05:35:46 PM PDT 24 59524815 ps
T399 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.3395769556 Aug 13 05:35:51 PM PDT 24 Aug 13 05:35:52 PM PDT 24 101458401 ps
T187 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.3757188073 Aug 13 05:35:52 PM PDT 24 Aug 13 05:36:12 PM PDT 24 3529507444 ps
T400 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.3476195928 Aug 13 05:35:50 PM PDT 24 Aug 13 05:35:52 PM PDT 24 455067287 ps
T401 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.3758018081 Aug 13 05:35:15 PM PDT 24 Aug 13 05:35:17 PM PDT 24 226136077 ps
T402 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.493665466 Aug 13 05:35:25 PM PDT 24 Aug 13 05:35:30 PM PDT 24 228592239 ps
T403 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1950798414 Aug 13 05:35:14 PM PDT 24 Aug 13 05:35:53 PM PDT 24 24956093178 ps
T404 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.712123112 Aug 13 05:35:51 PM PDT 24 Aug 13 05:36:05 PM PDT 24 9234900391 ps
T405 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.1272738120 Aug 13 05:35:22 PM PDT 24 Aug 13 05:35:23 PM PDT 24 73919576 ps
T159 /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.1696657318 Aug 13 05:35:50 PM PDT 24 Aug 13 05:35:54 PM PDT 24 176996258 ps
T406 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.988740381 Aug 13 05:35:23 PM PDT 24 Aug 13 05:35:24 PM PDT 24 162892123 ps
T407 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.2766827483 Aug 13 05:35:50 PM PDT 24 Aug 13 05:35:58 PM PDT 24 4115886453 ps
T408 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.2561720020 Aug 13 05:35:49 PM PDT 24 Aug 13 05:35:57 PM PDT 24 3094912956 ps
T153 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1688989345 Aug 13 05:35:50 PM PDT 24 Aug 13 05:35:52 PM PDT 24 137524706 ps
T409 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.2204868264 Aug 13 05:35:44 PM PDT 24 Aug 13 05:35:51 PM PDT 24 4082580340 ps
T116 /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.2379244808 Aug 13 05:35:31 PM PDT 24 Aug 13 05:35:35 PM PDT 24 224302619 ps
T410 /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.3851358050 Aug 13 05:35:53 PM PDT 24 Aug 13 05:35:55 PM PDT 24 144577349 ps
T411 /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.953262949 Aug 13 05:35:12 PM PDT 24 Aug 13 05:35:16 PM PDT 24 650900755 ps
T412 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.3537750357 Aug 13 05:35:51 PM PDT 24 Aug 13 05:35:53 PM PDT 24 115620434 ps
T413 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3122793156 Aug 13 05:35:22 PM PDT 24 Aug 13 05:35:55 PM PDT 24 2456081768 ps
T414 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.3061596024 Aug 13 05:35:49 PM PDT 24 Aug 13 05:35:51 PM PDT 24 119412996 ps
T111 /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.901528679 Aug 13 05:35:30 PM PDT 24 Aug 13 05:37:43 PM PDT 24 5373813171 ps
T415 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2153796936 Aug 13 05:35:46 PM PDT 24 Aug 13 05:35:47 PM PDT 24 324026440 ps
T190 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1403874282 Aug 13 05:35:30 PM PDT 24 Aug 13 05:35:49 PM PDT 24 2291880981 ps
T416 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.423419524 Aug 13 05:35:36 PM PDT 24 Aug 13 05:35:38 PM PDT 24 323196787 ps
T417 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.1175752316 Aug 13 05:35:43 PM PDT 24 Aug 13 05:35:45 PM PDT 24 69072853 ps
T191 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.3491856833 Aug 13 05:35:46 PM PDT 24 Aug 13 05:36:05 PM PDT 24 1921394094 ps
T418 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.69646428 Aug 13 05:35:45 PM PDT 24 Aug 13 05:35:57 PM PDT 24 14075117413 ps
T419 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.884765025 Aug 13 05:35:52 PM PDT 24 Aug 13 05:36:29 PM PDT 24 14555008496 ps
T154 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.338582082 Aug 13 05:35:21 PM PDT 24 Aug 13 05:35:24 PM PDT 24 239949774 ps
T420 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.2835963156 Aug 13 05:35:24 PM PDT 24 Aug 13 05:35:27 PM PDT 24 4091547954 ps
T114 /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.3544806712 Aug 13 05:35:29 PM PDT 24 Aug 13 05:36:59 PM PDT 24 4256828171 ps
T421 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.1578267467 Aug 13 05:35:28 PM PDT 24 Aug 13 05:35:29 PM PDT 24 54708308 ps
T422 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.554196158 Aug 13 05:35:51 PM PDT 24 Aug 13 05:36:38 PM PDT 24 16499992082 ps
T423 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.3459979379 Aug 13 05:35:21 PM PDT 24 Aug 13 05:35:23 PM PDT 24 1297759364 ps
T424 /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.3309333432 Aug 13 05:35:56 PM PDT 24 Aug 13 05:36:05 PM PDT 24 3208250321 ps
T425 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.2318548425 Aug 13 05:35:59 PM PDT 24 Aug 13 05:36:00 PM PDT 24 172397181 ps
T144 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.233181848 Aug 13 05:35:24 PM PDT 24 Aug 13 05:35:28 PM PDT 24 289152965 ps
T426 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3971173503 Aug 13 05:35:44 PM PDT 24 Aug 13 05:35:49 PM PDT 24 354872517 ps
T145 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.3874317173 Aug 13 05:35:59 PM PDT 24 Aug 13 05:36:04 PM PDT 24 369186835 ps
T115 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.1426126502 Aug 13 05:35:21 PM PDT 24 Aug 13 05:35:25 PM PDT 24 78990650 ps
T427 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.90248238 Aug 13 05:35:22 PM PDT 24 Aug 13 05:35:25 PM PDT 24 1537547179 ps
T428 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.1822381285 Aug 13 05:35:46 PM PDT 24 Aug 13 05:35:49 PM PDT 24 238428263 ps
T100 /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.4156872121 Aug 13 05:35:49 PM PDT 24 Aug 13 05:36:50 PM PDT 24 22377907832 ps
T429 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.3492523787 Aug 13 05:35:22 PM PDT 24 Aug 13 05:35:39 PM PDT 24 5959812782 ps
T430 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.36781925 Aug 13 05:35:54 PM PDT 24 Aug 13 05:35:56 PM PDT 24 87590231 ps
T431 /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3997225762 Aug 13 05:35:21 PM PDT 24 Aug 13 05:35:23 PM PDT 24 174049308 ps
T432 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.260569934 Aug 13 05:35:22 PM PDT 24 Aug 13 05:36:01 PM PDT 24 22420179340 ps
T433 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.2645535005 Aug 13 05:35:45 PM PDT 24 Aug 13 05:35:55 PM PDT 24 1199256602 ps
T434 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3504460813 Aug 13 05:35:50 PM PDT 24 Aug 13 05:35:52 PM PDT 24 216736242 ps
T435 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.980440763 Aug 13 05:35:17 PM PDT 24 Aug 13 05:35:20 PM PDT 24 214814756 ps
T436 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.4621810 Aug 13 05:35:52 PM PDT 24 Aug 13 05:37:09 PM PDT 24 73629600301 ps
T437 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.4168509687 Aug 13 05:35:24 PM PDT 24 Aug 13 05:35:25 PM PDT 24 103759424 ps
T146 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.2899426716 Aug 13 05:35:50 PM PDT 24 Aug 13 05:35:54 PM PDT 24 161770886 ps
T438 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.1911407439 Aug 13 05:35:49 PM PDT 24 Aug 13 05:35:50 PM PDT 24 423522834 ps
T439 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.435242551 Aug 13 05:35:52 PM PDT 24 Aug 13 05:35:55 PM PDT 24 127839841 ps
T440 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.2952763606 Aug 13 05:35:48 PM PDT 24 Aug 13 05:36:03 PM PDT 24 5912774120 ps
T441 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.362656261 Aug 13 05:35:25 PM PDT 24 Aug 13 05:35:26 PM PDT 24 260527699 ps
T442 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3856943533 Aug 13 05:35:20 PM PDT 24 Aug 13 05:35:22 PM PDT 24 136335926 ps
T443 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.3053644648 Aug 13 05:35:29 PM PDT 24 Aug 13 05:35:32 PM PDT 24 377616184 ps
T444 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.1666724925 Aug 13 05:35:54 PM PDT 24 Aug 13 05:36:12 PM PDT 24 5004180405 ps
T445 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2773682557 Aug 13 05:35:49 PM PDT 24 Aug 13 05:36:00 PM PDT 24 1579630346 ps
T446 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3404779343 Aug 13 05:36:06 PM PDT 24 Aug 13 05:36:15 PM PDT 24 622652363 ps
T147 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.866664677 Aug 13 05:35:22 PM PDT 24 Aug 13 05:36:38 PM PDT 24 8644674841 ps
T447 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.2488020726 Aug 13 05:35:49 PM PDT 24 Aug 13 05:35:52 PM PDT 24 172500372 ps
T448 /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.1918946335 Aug 13 05:35:25 PM PDT 24 Aug 13 05:36:03 PM PDT 24 5884518068 ps
T449 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.3792955378 Aug 13 05:35:25 PM PDT 24 Aug 13 05:35:35 PM PDT 24 3274283470 ps
T450 /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.601822262 Aug 13 05:36:08 PM PDT 24 Aug 13 05:36:12 PM PDT 24 116227007 ps
T451 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3565389805 Aug 13 05:35:49 PM PDT 24 Aug 13 05:35:50 PM PDT 24 202712593 ps
T110 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.3200336357 Aug 13 05:35:47 PM PDT 24 Aug 13 05:35:51 PM PDT 24 150022209 ps
T452 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.2499859448 Aug 13 05:35:53 PM PDT 24 Aug 13 05:36:22 PM PDT 24 2365786727 ps
T104 /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.40775790 Aug 13 05:35:16 PM PDT 24 Aug 13 05:36:40 PM PDT 24 4059358663 ps
T453 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2151517127 Aug 13 05:35:17 PM PDT 24 Aug 13 05:35:18 PM PDT 24 219898377 ps
T454 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.642786065 Aug 13 05:35:51 PM PDT 24 Aug 13 05:36:00 PM PDT 24 3236552398 ps
T455 /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.3078066093 Aug 13 05:35:49 PM PDT 24 Aug 13 05:35:55 PM PDT 24 736668321 ps
T456 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1448990337 Aug 13 05:35:25 PM PDT 24 Aug 13 05:35:26 PM PDT 24 248993651 ps
T457 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.2109182606 Aug 13 05:35:49 PM PDT 24 Aug 13 05:35:51 PM PDT 24 564076311 ps
T458 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.2974798727 Aug 13 05:35:45 PM PDT 24 Aug 13 05:35:55 PM PDT 24 2250329124 ps
T459 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.60478482 Aug 13 05:35:48 PM PDT 24 Aug 13 05:36:39 PM PDT 24 56045989044 ps
T460 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.675339926 Aug 13 05:35:28 PM PDT 24 Aug 13 05:35:31 PM PDT 24 136527281 ps
T461 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.68995463 Aug 13 05:35:26 PM PDT 24 Aug 13 05:35:59 PM PDT 24 8078309363 ps
T462 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.275133226 Aug 13 05:35:32 PM PDT 24 Aug 13 05:35:40 PM PDT 24 2884926113 ps
T463 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1191843478 Aug 13 05:35:20 PM PDT 24 Aug 13 05:35:21 PM PDT 24 42750350 ps
T464 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.134767943 Aug 13 05:35:59 PM PDT 24 Aug 13 05:36:00 PM PDT 24 332519338 ps
T465 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.1311711702 Aug 13 05:36:06 PM PDT 24 Aug 13 05:36:09 PM PDT 24 153512542 ps
T466 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.2352136069 Aug 13 05:35:48 PM PDT 24 Aug 13 05:35:58 PM PDT 24 3735624448 ps
T467 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.2299132974 Aug 13 05:35:46 PM PDT 24 Aug 13 05:35:48 PM PDT 24 4325207489 ps
T468 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.1570241035 Aug 13 05:35:49 PM PDT 24 Aug 13 05:36:05 PM PDT 24 1738322338 ps
T469 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.3266988147 Aug 13 05:35:31 PM PDT 24 Aug 13 05:35:33 PM PDT 24 213653828 ps
T470 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.3283446996 Aug 13 05:35:17 PM PDT 24 Aug 13 05:38:51 PM PDT 24 107913403356 ps
T117 /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.2741791370 Aug 13 05:35:34 PM PDT 24 Aug 13 05:36:42 PM PDT 24 7209299650 ps
T471 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.2487562230 Aug 13 05:35:47 PM PDT 24 Aug 13 05:35:58 PM PDT 24 10650361238 ps
T108 /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.2406353360 Aug 13 05:35:21 PM PDT 24 Aug 13 05:36:30 PM PDT 24 7461312038 ps
T148 /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.2435385941 Aug 13 05:35:51 PM PDT 24 Aug 13 05:35:58 PM PDT 24 277289045 ps
T472 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2545038149 Aug 13 05:35:50 PM PDT 24 Aug 13 05:35:51 PM PDT 24 120727139 ps
T473 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.2282698793 Aug 13 05:35:29 PM PDT 24 Aug 13 05:35:30 PM PDT 24 46822855 ps
T137 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.3661457122 Aug 13 05:35:14 PM PDT 24 Aug 13 05:35:21 PM PDT 24 2452406826 ps
T474 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.776388840 Aug 13 05:35:55 PM PDT 24 Aug 13 05:36:03 PM PDT 24 585553073 ps
T475 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.1476068439 Aug 13 05:35:50 PM PDT 24 Aug 13 05:35:59 PM PDT 24 1446675310 ps
T476 /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.978477684 Aug 13 05:35:25 PM PDT 24 Aug 13 05:35:27 PM PDT 24 163067315 ps
T477 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.389639334 Aug 13 05:35:12 PM PDT 24 Aug 13 05:35:12 PM PDT 24 181927764 ps
T478 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.2020432626 Aug 13 05:35:46 PM PDT 24 Aug 13 05:35:54 PM PDT 24 13956763446 ps
T106 /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.1642768258 Aug 13 05:35:45 PM PDT 24 Aug 13 05:36:46 PM PDT 24 4332642045 ps
T479 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.2129465206 Aug 13 05:35:20 PM PDT 24 Aug 13 05:35:35 PM PDT 24 11128265748 ps
T480 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.2872174260 Aug 13 05:35:48 PM PDT 24 Aug 13 05:36:02 PM PDT 24 4719969715 ps
T481 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.4051558899 Aug 13 05:35:51 PM PDT 24 Aug 13 05:36:38 PM PDT 24 16630608577 ps
T482 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.2374543618 Aug 13 05:35:27 PM PDT 24 Aug 13 05:35:28 PM PDT 24 63497884 ps
T138 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.3711505283 Aug 13 05:35:28 PM PDT 24 Aug 13 05:35:37 PM PDT 24 2591084231 ps

Test location /workspace/coverage/default/38.rv_dm_stress_all.2672221446
Short name T5
Test name
Test status
Simulation time 5162221280 ps
CPU time 9.27 seconds
Started Aug 13 05:36:27 PM PDT 24
Finished Aug 13 05:36:36 PM PDT 24
Peak memory 213260 kb
Host smart-d25472de-f8cc-486d-87b8-42280be7cbbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672221446 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.2672221446
Directory /workspace/38.rv_dm_stress_all/latest

Test location /workspace/coverage/default/2.rv_dm_stress_all_with_rand_reset.3980793856
Short name T53
Test name
Test status
Simulation time 3014161328 ps
CPU time 33 seconds
Started Aug 13 05:36:03 PM PDT 24
Finished Aug 13 05:36:36 PM PDT 24
Peak memory 221076 kb
Host smart-dad83f22-fe36-488c-9d6b-362d63959f10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980793856 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all_with_rand_reset.3980793856
Directory /workspace/2.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.3002607795
Short name T12
Test name
Test status
Simulation time 4404925901 ps
CPU time 3.55 seconds
Started Aug 13 05:35:59 PM PDT 24
Finished Aug 13 05:36:03 PM PDT 24
Peak memory 205476 kb
Host smart-c3d63d1a-8b0f-40c4-9cb0-812c7e488af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002607795 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.3002607795
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.4265011391
Short name T99
Test name
Test status
Simulation time 6794698803 ps
CPU time 7.01 seconds
Started Aug 13 05:35:53 PM PDT 24
Finished Aug 13 05:36:01 PM PDT 24
Peak memory 205160 kb
Host smart-33e3cf1e-f987-4984-a3ac-14f1c33e4326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265011391 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.4265011391
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/0.rv_dm_stress_all_with_rand_reset.786926746
Short name T63
Test name
Test status
Simulation time 14585982689 ps
CPU time 59.8 seconds
Started Aug 13 05:35:55 PM PDT 24
Finished Aug 13 05:36:55 PM PDT 24
Peak memory 229284 kb
Host smart-505fb536-a48f-4eaf-8dfc-1f73beb48b10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786926746 -assert nopostp
roc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all_with_rand_reset.786926746
Directory /workspace/0.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.2604178237
Short name T165
Test name
Test status
Simulation time 4465606250 ps
CPU time 18.94 seconds
Started Aug 13 05:35:52 PM PDT 24
Finished Aug 13 05:36:11 PM PDT 24
Peak memory 221720 kb
Host smart-874476f8-72e6-40b0-85f9-bf4fc8c0deba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604178237 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.2
604178237
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/1.rv_dm_stress_all_with_rand_reset.697021988
Short name T48
Test name
Test status
Simulation time 3770514280 ps
CPU time 60.03 seconds
Started Aug 13 05:35:55 PM PDT 24
Finished Aug 13 05:36:55 PM PDT 24
Peak memory 221528 kb
Host smart-a9e65909-7501-4f9d-b85d-3614c8cfdcbf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697021988 -assert nopostp
roc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all_with_rand_reset.697021988
Directory /workspace/1.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rv_dm_buffered_enable.565939598
Short name T41
Test name
Test status
Simulation time 605427625 ps
CPU time 1.46 seconds
Started Aug 13 05:36:05 PM PDT 24
Finished Aug 13 05:36:06 PM PDT 24
Peak memory 226056 kb
Host smart-7cda9d6c-c792-4d1e-8849-3ad4e5d80503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565939598 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_buffered_enable.565939598
Directory /workspace/8.rv_dm_buffered_enable/latest

Test location /workspace/coverage/default/5.rv_dm_stress_all_with_rand_reset.2233198392
Short name T82
Test name
Test status
Simulation time 1310305053 ps
CPU time 28.93 seconds
Started Aug 13 05:36:00 PM PDT 24
Finished Aug 13 05:36:29 PM PDT 24
Peak memory 215680 kb
Host smart-f40b0d04-687c-4705-9507-896217c98132
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233198392 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all_with_rand_reset.2233198392
Directory /workspace/5.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.3286648384
Short name T35
Test name
Test status
Simulation time 1412406011 ps
CPU time 1.99 seconds
Started Aug 13 05:36:08 PM PDT 24
Finished Aug 13 05:36:10 PM PDT 24
Peak memory 229556 kb
Host smart-4ee84d5b-327a-4ee9-a9aa-a72727a393d4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286648384 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.3286648384
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.1642768258
Short name T106
Test name
Test status
Simulation time 4332642045 ps
CPU time 60.66 seconds
Started Aug 13 05:35:45 PM PDT 24
Finished Aug 13 05:36:46 PM PDT 24
Peak memory 217924 kb
Host smart-20b8eabc-02db-40f6-83a6-258b86f0840a
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642768258 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.1642768258
Directory /workspace/9.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/0.rv_dm_dmi_failed_op.3654809385
Short name T60
Test name
Test status
Simulation time 626624079 ps
CPU time 1.58 seconds
Started Aug 13 05:36:16 PM PDT 24
Finished Aug 13 05:36:17 PM PDT 24
Peak memory 204904 kb
Host smart-8583121e-9c1d-442d-bceb-6b0f1b4cbe5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654809385 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dmi_failed_op.3654809385
Directory /workspace/0.rv_dm_dmi_failed_op/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.1570850245
Short name T32
Test name
Test status
Simulation time 5480383418 ps
CPU time 8.36 seconds
Started Aug 13 05:36:15 PM PDT 24
Finished Aug 13 05:36:24 PM PDT 24
Peak memory 213628 kb
Host smart-45f65f6a-ce1b-49a2-99d6-67daab6ef1dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570850245 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.1570850245
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.3176277407
Short name T143
Test name
Test status
Simulation time 191587111 ps
CPU time 1.47 seconds
Started Aug 13 05:35:50 PM PDT 24
Finished Aug 13 05:35:51 PM PDT 24
Peak memory 213532 kb
Host smart-c4c862d2-ec07-4a41-a57c-296a0cf32688
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176277407 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.3176277407
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.2290298597
Short name T118
Test name
Test status
Simulation time 112563218 ps
CPU time 3.25 seconds
Started Aug 13 05:35:50 PM PDT 24
Finished Aug 13 05:35:53 PM PDT 24
Peak memory 221304 kb
Host smart-0240783a-f17f-4d90-9bba-253c368b70e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290298597 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.2290298597
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/22.rv_dm_stress_all.3517916167
Short name T55
Test name
Test status
Simulation time 5970326336 ps
CPU time 5.97 seconds
Started Aug 13 05:36:30 PM PDT 24
Finished Aug 13 05:36:36 PM PDT 24
Peak memory 205200 kb
Host smart-937e64df-df14-4517-9b90-e8bdd2f651ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517916167 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.3517916167
Directory /workspace/22.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.1426126502
Short name T115
Test name
Test status
Simulation time 78990650 ps
CPU time 4.16 seconds
Started Aug 13 05:35:21 PM PDT 24
Finished Aug 13 05:35:25 PM PDT 24
Peak memory 219536 kb
Host smart-8540067a-bb07-43f8-a7a7-edf14ae7f865
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426126502 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.1426126502
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.3200336357
Short name T110
Test name
Test status
Simulation time 150022209 ps
CPU time 3.68 seconds
Started Aug 13 05:35:47 PM PDT 24
Finished Aug 13 05:35:51 PM PDT 24
Peak memory 219600 kb
Host smart-c3892830-9a8c-4bae-8c3e-138467b66441
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200336357 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.3200336357
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/1.rv_dm_dmi_failed_op.2622395210
Short name T61
Test name
Test status
Simulation time 724491891 ps
CPU time 0.79 seconds
Started Aug 13 05:36:15 PM PDT 24
Finished Aug 13 05:36:16 PM PDT 24
Peak memory 204908 kb
Host smart-dcce7519-6086-402f-8d4c-f5aeb7ceb9f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622395210 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dmi_failed_op.2622395210
Directory /workspace/1.rv_dm_dmi_failed_op/latest

Test location /workspace/coverage/default/3.rv_dm_stress_all_with_rand_reset.3418364180
Short name T109
Test name
Test status
Simulation time 1067709338 ps
CPU time 18.15 seconds
Started Aug 13 05:36:01 PM PDT 24
Finished Aug 13 05:36:19 PM PDT 24
Peak memory 221536 kb
Host smart-91e10e77-3234-498f-aaec-e0bd160113c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418364180 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all_with_rand_reset.3418364180
Directory /workspace/3.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.1174446433
Short name T18
Test name
Test status
Simulation time 344398309 ps
CPU time 1.09 seconds
Started Aug 13 05:35:47 PM PDT 24
Finished Aug 13 05:35:49 PM PDT 24
Peak memory 204844 kb
Host smart-9346be41-349b-48cd-b716-da8154f1fe76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174446433 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.1174446433
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.3726061714
Short name T189
Test name
Test status
Simulation time 1285126789 ps
CPU time 17.94 seconds
Started Aug 13 05:35:20 PM PDT 24
Finished Aug 13 05:35:38 PM PDT 24
Peak memory 221480 kb
Host smart-974e3305-ba21-49a4-b02f-b488b08ca0df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726061714 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.3726061714
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/13.rv_dm_stress_all.3700924509
Short name T23
Test name
Test status
Simulation time 3618488730 ps
CPU time 6.56 seconds
Started Aug 13 05:36:31 PM PDT 24
Finished Aug 13 05:36:37 PM PDT 24
Peak memory 205104 kb
Host smart-aff60471-9e48-424d-a03e-794229808f35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700924509 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.3700924509
Directory /workspace/13.rv_dm_stress_all/latest

Test location /workspace/coverage/default/3.rv_dm_stress_all.3781886992
Short name T17
Test name
Test status
Simulation time 5803432770 ps
CPU time 5.03 seconds
Started Aug 13 05:36:02 PM PDT 24
Finished Aug 13 05:36:07 PM PDT 24
Peak memory 205164 kb
Host smart-f1ad9cdb-7134-43e7-b533-c932a7fa9a64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781886992 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.3781886992
Directory /workspace/3.rv_dm_stress_all/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.3989514764
Short name T1
Test name
Test status
Simulation time 32532033 ps
CPU time 0.75 seconds
Started Aug 13 05:36:27 PM PDT 24
Finished Aug 13 05:36:28 PM PDT 24
Peak memory 205080 kb
Host smart-bc6b6be4-10de-42a3-bf02-197f0a3743a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989514764 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.3989514764
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_stress_all.3465256930
Short name T245
Test name
Test status
Simulation time 4662679187 ps
CPU time 4.9 seconds
Started Aug 13 05:36:36 PM PDT 24
Finished Aug 13 05:36:41 PM PDT 24
Peak memory 205112 kb
Host smart-0fb5e023-e6e7-471a-b72e-181de9e748f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465256930 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.3465256930
Directory /workspace/41.rv_dm_stress_all/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.4086867797
Short name T44
Test name
Test status
Simulation time 143967705 ps
CPU time 1.2 seconds
Started Aug 13 05:35:57 PM PDT 24
Finished Aug 13 05:35:58 PM PDT 24
Peak memory 213404 kb
Host smart-c4ddaef2-3017-44d7-89c0-90ca6ea29ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086867797 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.4086867797
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1094281765
Short name T131
Test name
Test status
Simulation time 614487873 ps
CPU time 7.44 seconds
Started Aug 13 05:35:51 PM PDT 24
Finished Aug 13 05:35:58 PM PDT 24
Peak memory 205272 kb
Host smart-44e0d793-c0c9-4227-b9e0-7d8a0f1f3e3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094281765 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.1094281765
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.3438751079
Short name T239
Test name
Test status
Simulation time 18530362069 ps
CPU time 15.3 seconds
Started Aug 13 05:36:02 PM PDT 24
Finished Aug 13 05:36:18 PM PDT 24
Peak memory 213608 kb
Host smart-c0f86f70-1991-46c5-b8dc-b2ff4ddcf34e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438751079 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.3438751079
Directory /workspace/6.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.1210131704
Short name T277
Test name
Test status
Simulation time 1751726054 ps
CPU time 2.79 seconds
Started Aug 13 05:36:21 PM PDT 24
Finished Aug 13 05:36:24 PM PDT 24
Peak memory 205452 kb
Host smart-ff4746b1-2a00-4e81-bc86-64175d0ffcc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210131704 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.1210131704
Directory /workspace/18.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_buffered_enable.325921387
Short name T94
Test name
Test status
Simulation time 268091677 ps
CPU time 1.22 seconds
Started Aug 13 05:35:54 PM PDT 24
Finished Aug 13 05:35:55 PM PDT 24
Peak memory 226456 kb
Host smart-ee709406-49ef-48b1-84eb-f5662a9b8d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325921387 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_buffered_enable.325921387
Directory /workspace/0.rv_dm_buffered_enable/latest

Test location /workspace/coverage/default/3.rv_dm_sparse_lc_gate_fsm.2953678202
Short name T69
Test name
Test status
Simulation time 56863414 ps
CPU time 0.81 seconds
Started Aug 13 05:36:04 PM PDT 24
Finished Aug 13 05:36:05 PM PDT 24
Peak memory 213268 kb
Host smart-00bbfa54-3a83-4477-b80c-51970cc1d2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953678202 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sparse_lc_gate_fsm.2953678202
Directory /workspace/3.rv_dm_sparse_lc_gate_fsm/latest

Test location /workspace/coverage/default/9.rv_dm_stress_all_with_rand_reset.3542488769
Short name T65
Test name
Test status
Simulation time 1521160787 ps
CPU time 24.25 seconds
Started Aug 13 05:36:16 PM PDT 24
Finished Aug 13 05:36:41 PM PDT 24
Peak memory 221644 kb
Host smart-9d6937da-087a-4099-b124-8c912c33dfb2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542488769 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all_with_rand_reset.3542488769
Directory /workspace/9.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.rv_dm_sba_debug_disabled.3180820070
Short name T96
Test name
Test status
Simulation time 861057560 ps
CPU time 1.96 seconds
Started Aug 13 05:35:50 PM PDT 24
Finished Aug 13 05:35:53 PM PDT 24
Peak memory 204968 kb
Host smart-8324f105-6059-45df-9e1e-7b74dd8ce37a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180820070 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.3180820070
Directory /workspace/0.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.995667498
Short name T292
Test name
Test status
Simulation time 2027793296 ps
CPU time 2.15 seconds
Started Aug 13 05:36:23 PM PDT 24
Finished Aug 13 05:36:25 PM PDT 24
Peak memory 213624 kb
Host smart-5b148f4f-5e91-4a6d-a84f-68e236613903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995667498 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.995667498
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.1792398780
Short name T164
Test name
Test status
Simulation time 2717832769 ps
CPU time 21.67 seconds
Started Aug 13 05:35:25 PM PDT 24
Finished Aug 13 05:35:47 PM PDT 24
Peak memory 213344 kb
Host smart-0245476a-3288-4c82-993f-30f6cf91c510
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792398780 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.1792398780
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.3560665959
Short name T322
Test name
Test status
Simulation time 7464993123 ps
CPU time 8.13 seconds
Started Aug 13 05:36:07 PM PDT 24
Finished Aug 13 05:36:15 PM PDT 24
Peak memory 213532 kb
Host smart-195e42af-0c4e-4eb4-b7d9-8a7bfb3a0837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560665959 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.3560665959
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.3177840185
Short name T364
Test name
Test status
Simulation time 6645216697 ps
CPU time 5.86 seconds
Started Aug 13 05:35:33 PM PDT 24
Finished Aug 13 05:35:39 PM PDT 24
Peak memory 205116 kb
Host smart-aff45cde-3e18-40b5-99a6-820f19c8b033
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177840185 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_bit_bash.3177840185
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/default/0.rv_dm_abstractcmd_status.97260260
Short name T56
Test name
Test status
Simulation time 281725744 ps
CPU time 0.94 seconds
Started Aug 13 05:36:02 PM PDT 24
Finished Aug 13 05:36:04 PM PDT 24
Peak memory 204908 kb
Host smart-77a0d424-fa06-47f9-9fa2-ad2a938ed742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97260260 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.97260260
Directory /workspace/0.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.846301425
Short name T97
Test name
Test status
Simulation time 17518090670 ps
CPU time 58.15 seconds
Started Aug 13 05:35:48 PM PDT 24
Finished Aug 13 05:36:46 PM PDT 24
Peak memory 213684 kb
Host smart-6bf2e825-c565-4a85-ad42-9f8e4b44e753
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846301425 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.846301425
Directory /workspace/8.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.75588546
Short name T42
Test name
Test status
Simulation time 489858702 ps
CPU time 2.1 seconds
Started Aug 13 05:35:51 PM PDT 24
Finished Aug 13 05:35:53 PM PDT 24
Peak memory 204896 kb
Host smart-2aa73a89-16d1-48bc-addd-570372c0cee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75588546 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.75588546
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.2974798727
Short name T458
Test name
Test status
Simulation time 2250329124 ps
CPU time 10.5 seconds
Started Aug 13 05:35:45 PM PDT 24
Finished Aug 13 05:35:55 PM PDT 24
Peak memory 221496 kb
Host smart-c83c4abb-5dc2-47d9-92de-30693052d280
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974798727 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.2
974798727
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3288031607
Short name T194
Test name
Test status
Simulation time 6947364728 ps
CPU time 22.99 seconds
Started Aug 13 05:35:28 PM PDT 24
Finished Aug 13 05:35:51 PM PDT 24
Peak memory 221764 kb
Host smart-af028b00-5866-498e-bf51-b9bc2549b7c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288031607 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.3288031607
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.1853674384
Short name T182
Test name
Test status
Simulation time 201847162 ps
CPU time 0.87 seconds
Started Aug 13 05:35:52 PM PDT 24
Finished Aug 13 05:35:53 PM PDT 24
Peak memory 204884 kb
Host smart-9e224487-2947-46d3-a608-24f4bd68df63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853674384 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.1853674384
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.4195435899
Short name T329
Test name
Test status
Simulation time 396341245 ps
CPU time 1.34 seconds
Started Aug 13 05:35:54 PM PDT 24
Finished Aug 13 05:35:56 PM PDT 24
Peak memory 212960 kb
Host smart-67789709-0f0b-4c9a-9a2e-a4baac065fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195435899 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.4195435899
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/11.rv_dm_stress_all.2917678553
Short name T50
Test name
Test status
Simulation time 3755705202 ps
CPU time 3.09 seconds
Started Aug 13 05:36:21 PM PDT 24
Finished Aug 13 05:36:25 PM PDT 24
Peak memory 204364 kb
Host smart-2e9f40e7-c824-4fbd-bf92-83db732a1dc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917678553 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.2917678553
Directory /workspace/11.rv_dm_stress_all/latest

Test location /workspace/coverage/default/12.rv_dm_stress_all.1694455
Short name T21
Test name
Test status
Simulation time 6420316526 ps
CPU time 17.98 seconds
Started Aug 13 05:36:31 PM PDT 24
Finished Aug 13 05:36:49 PM PDT 24
Peak memory 205060 kb
Host smart-57ab8595-e560-4fb5-969e-d3fd43f92abb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694455 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.1694455
Directory /workspace/12.rv_dm_stress_all/latest

Test location /workspace/coverage/default/2.rv_dm_sparse_lc_gate_fsm.982258164
Short name T36
Test name
Test status
Simulation time 65270807 ps
CPU time 0.86 seconds
Started Aug 13 05:36:07 PM PDT 24
Finished Aug 13 05:36:08 PM PDT 24
Peak memory 213404 kb
Host smart-b7841502-83b3-4f4b-80ad-d4f7886168ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982258164 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sparse_lc_gate_fsm.982258164
Directory /workspace/2.rv_dm_sparse_lc_gate_fsm/latest

Test location /workspace/coverage/default/30.rv_dm_stress_all.2760216723
Short name T3
Test name
Test status
Simulation time 6410850601 ps
CPU time 18.37 seconds
Started Aug 13 05:36:26 PM PDT 24
Finished Aug 13 05:36:44 PM PDT 24
Peak memory 213428 kb
Host smart-682f47e6-0337-407a-a44f-9f3f00a3f58b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760216723 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.2760216723
Directory /workspace/30.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3122793156
Short name T413
Test name
Test status
Simulation time 2456081768 ps
CPU time 32.66 seconds
Started Aug 13 05:35:22 PM PDT 24
Finished Aug 13 05:35:55 PM PDT 24
Peak memory 205348 kb
Host smart-38648d73-8752-4026-9876-ac9b085b7909
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122793156 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.3122793156
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.2734667891
Short name T366
Test name
Test status
Simulation time 2574559769 ps
CPU time 33.24 seconds
Started Aug 13 05:35:23 PM PDT 24
Finished Aug 13 05:35:57 PM PDT 24
Peak memory 205312 kb
Host smart-a50ce8cd-e85b-4fe3-8e92-4348d2c60fb6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734667891 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.2734667891
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3856943533
Short name T442
Test name
Test status
Simulation time 136335926 ps
CPU time 1.85 seconds
Started Aug 13 05:35:20 PM PDT 24
Finished Aug 13 05:35:22 PM PDT 24
Peak memory 213384 kb
Host smart-42883cc7-d1b7-408a-9f6d-eff986cf895e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856943533 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.3856943533
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.2926793393
Short name T391
Test name
Test status
Simulation time 172743863 ps
CPU time 1.92 seconds
Started Aug 13 05:35:21 PM PDT 24
Finished Aug 13 05:35:23 PM PDT 24
Peak memory 213648 kb
Host smart-7c3864e7-2a10-4b92-a356-620ac28353ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926793393 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.2926793393
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.1030416187
Short name T151
Test name
Test status
Simulation time 105535226 ps
CPU time 2.41 seconds
Started Aug 13 05:35:13 PM PDT 24
Finished Aug 13 05:35:16 PM PDT 24
Peak memory 219220 kb
Host smart-81a19104-4810-47c9-bc0b-1dbf8e694bc6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030416187 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.1030416187
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1811258750
Short name T386
Test name
Test status
Simulation time 48850535810 ps
CPU time 40.34 seconds
Started Aug 13 05:35:21 PM PDT 24
Finished Aug 13 05:36:01 PM PDT 24
Peak memory 205100 kb
Host smart-6556e1e4-2ff2-430d-b079-233edee742d5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811258750 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_aliasing.1811258750
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1950798414
Short name T403
Test name
Test status
Simulation time 24956093178 ps
CPU time 39.18 seconds
Started Aug 13 05:35:14 PM PDT 24
Finished Aug 13 05:35:53 PM PDT 24
Peak memory 205300 kb
Host smart-5301cb62-3434-4156-86aa-59acd5268d0e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950798414 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
rv_dm_jtag_dmi_csr_bit_bash.1950798414
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.1049637713
Short name T135
Test name
Test status
Simulation time 4671349664 ps
CPU time 2.17 seconds
Started Aug 13 05:35:14 PM PDT 24
Finished Aug 13 05:35:16 PM PDT 24
Peak memory 205324 kb
Host smart-0f2e2c9d-8551-47f0-aa45-dfb26b89578f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049637713 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_hw_reset.1049637713
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.90248238
Short name T427
Test name
Test status
Simulation time 1537547179 ps
CPU time 3.03 seconds
Started Aug 13 05:35:22 PM PDT 24
Finished Aug 13 05:35:25 PM PDT 24
Peak memory 205136 kb
Host smart-69793f16-3fe1-4be9-8c2d-21b90bbf064b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90248238 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.90248238
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2151517127
Short name T453
Test name
Test status
Simulation time 219898377 ps
CPU time 0.86 seconds
Started Aug 13 05:35:17 PM PDT 24
Finished Aug 13 05:35:18 PM PDT 24
Peak memory 204928 kb
Host smart-e98ba9f6-350a-4966-a5dd-ec29dd0a3313
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151517127 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.2151517127
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.3792955378
Short name T449
Test name
Test status
Simulation time 3274283470 ps
CPU time 9.99 seconds
Started Aug 13 05:35:25 PM PDT 24
Finished Aug 13 05:35:35 PM PDT 24
Peak memory 205144 kb
Host smart-ad0903fe-a3f3-40cc-b7f2-63828cba2b89
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792955378 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_bit_bash.3792955378
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3018089340
Short name T381
Test name
Test status
Simulation time 495204927 ps
CPU time 1.99 seconds
Started Aug 13 05:35:21 PM PDT 24
Finished Aug 13 05:35:23 PM PDT 24
Peak memory 204932 kb
Host smart-ab5c3669-25d6-450c-a91b-4ffd48f87dd3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018089340 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.3018089340
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1448990337
Short name T456
Test name
Test status
Simulation time 248993651 ps
CPU time 0.92 seconds
Started Aug 13 05:35:25 PM PDT 24
Finished Aug 13 05:35:26 PM PDT 24
Peak memory 204984 kb
Host smart-7f80a5a3-d1c8-42a0-8733-52ea4e49a844
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448990337 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.1
448990337
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1191843478
Short name T463
Test name
Test status
Simulation time 42750350 ps
CPU time 0.71 seconds
Started Aug 13 05:35:20 PM PDT 24
Finished Aug 13 05:35:21 PM PDT 24
Peak memory 204980 kb
Host smart-67a4e39b-8c3a-445c-940b-1aaee5412211
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191843478 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.1191843478
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.389639334
Short name T477
Test name
Test status
Simulation time 181927764 ps
CPU time 0.75 seconds
Started Aug 13 05:35:12 PM PDT 24
Finished Aug 13 05:35:12 PM PDT 24
Peak memory 204964 kb
Host smart-b2a11502-34c7-43e7-83ab-ba44699aff35
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389639334 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.389639334
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.953262949
Short name T411
Test name
Test status
Simulation time 650900755 ps
CPU time 3.65 seconds
Started Aug 13 05:35:12 PM PDT 24
Finished Aug 13 05:35:16 PM PDT 24
Peak memory 205228 kb
Host smart-9b50ccf2-05cc-4b12-b7cf-be61cf155c96
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953262949 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_c
sr_outstanding.953262949
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.40775790
Short name T104
Test name
Test status
Simulation time 4059358663 ps
CPU time 84.22 seconds
Started Aug 13 05:35:16 PM PDT 24
Finished Aug 13 05:36:40 PM PDT 24
Peak memory 218180 kb
Host smart-448cf00e-b1d1-49a5-995e-46216f33dadc
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40775790 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.40775790
Directory /workspace/0.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.4174787904
Short name T161
Test name
Test status
Simulation time 501133713 ps
CPU time 6.44 seconds
Started Aug 13 05:35:22 PM PDT 24
Finished Aug 13 05:35:29 PM PDT 24
Peak memory 213556 kb
Host smart-51fd2ade-dbfa-4cbd-b534-962c9c3542f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174787904 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.4174787904
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.1492081962
Short name T385
Test name
Test status
Simulation time 5221766196 ps
CPU time 31.39 seconds
Started Aug 13 05:35:25 PM PDT 24
Finished Aug 13 05:35:57 PM PDT 24
Peak memory 221704 kb
Host smart-754ee3dd-09c2-4d83-9546-b85ed880af20
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492081962 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.1492081962
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.68995463
Short name T461
Test name
Test status
Simulation time 8078309363 ps
CPU time 32.79 seconds
Started Aug 13 05:35:26 PM PDT 24
Finished Aug 13 05:35:59 PM PDT 24
Peak memory 205312 kb
Host smart-91d5d9c5-fcfd-480c-a62b-1eddef003164
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68995463 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UV
M_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 1.rv_dm_csr_aliasing.68995463
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.299185702
Short name T132
Test name
Test status
Simulation time 1449035556 ps
CPU time 52.13 seconds
Started Aug 13 05:35:24 PM PDT 24
Finished Aug 13 05:36:16 PM PDT 24
Peak memory 205316 kb
Host smart-1f643fcd-02dd-4ea5-ba44-b5d5f34974c8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299185702 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.299185702
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.338582082
Short name T154
Test name
Test status
Simulation time 239949774 ps
CPU time 2.61 seconds
Started Aug 13 05:35:21 PM PDT 24
Finished Aug 13 05:35:24 PM PDT 24
Peak memory 213432 kb
Host smart-d51e5283-e452-43e6-96fb-6ef82ba457f2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338582082 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.338582082
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.978477684
Short name T476
Test name
Test status
Simulation time 163067315 ps
CPU time 1.64 seconds
Started Aug 13 05:35:25 PM PDT 24
Finished Aug 13 05:35:27 PM PDT 24
Peak memory 218392 kb
Host smart-c197343a-6b0c-4526-b1cd-3aaaf2945731
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978477684 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.978477684
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.3283446996
Short name T470
Test name
Test status
Simulation time 107913403356 ps
CPU time 214 seconds
Started Aug 13 05:35:17 PM PDT 24
Finished Aug 13 05:38:51 PM PDT 24
Peak memory 205296 kb
Host smart-32ae2c7e-8395-4217-b928-a5a98e878071
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283446996 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_aliasing.3283446996
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.4136811469
Short name T342
Test name
Test status
Simulation time 21340422432 ps
CPU time 18.93 seconds
Started Aug 13 05:35:34 PM PDT 24
Finished Aug 13 05:35:54 PM PDT 24
Peak memory 205164 kb
Host smart-dbc40e81-353c-428f-a607-74ffa9553883
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136811469 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
rv_dm_jtag_dmi_csr_bit_bash.4136811469
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.3661457122
Short name T137
Test name
Test status
Simulation time 2452406826 ps
CPU time 6.86 seconds
Started Aug 13 05:35:14 PM PDT 24
Finished Aug 13 05:35:21 PM PDT 24
Peak memory 205360 kb
Host smart-4ef61960-7ece-4954-8008-565e7090c88c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661457122 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.3661457122
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.475193581
Short name T361
Test name
Test status
Simulation time 4680667526 ps
CPU time 12.53 seconds
Started Aug 13 05:35:14 PM PDT 24
Finished Aug 13 05:35:27 PM PDT 24
Peak memory 205252 kb
Host smart-c2ab847a-be52-429e-ac63-e3cf53156966
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475193581 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.475193581
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.3758018081
Short name T401
Test name
Test status
Simulation time 226136077 ps
CPU time 1.35 seconds
Started Aug 13 05:35:15 PM PDT 24
Finished Aug 13 05:35:17 PM PDT 24
Peak memory 204836 kb
Host smart-c54fb602-55cd-4135-bd00-c60634417d09
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758018081 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_aliasing.3758018081
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.4168509687
Short name T437
Test name
Test status
Simulation time 103759424 ps
CPU time 0.88 seconds
Started Aug 13 05:35:24 PM PDT 24
Finished Aug 13 05:35:25 PM PDT 24
Peak memory 204960 kb
Host smart-b2323b09-c462-498d-ab43-b7a2b9bd1313
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168509687 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.4168509687
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.926946179
Short name T121
Test name
Test status
Simulation time 357213834 ps
CPU time 1.52 seconds
Started Aug 13 05:35:14 PM PDT 24
Finished Aug 13 05:35:16 PM PDT 24
Peak memory 204984 kb
Host smart-b0d010c8-e6cf-49a5-b952-43d31cbcffb8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926946179 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.926946179
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.2374543618
Short name T482
Test name
Test status
Simulation time 63497884 ps
CPU time 0.74 seconds
Started Aug 13 05:35:27 PM PDT 24
Finished Aug 13 05:35:28 PM PDT 24
Peak memory 204952 kb
Host smart-07a796bf-98a4-46b2-8832-a12fe9dde3f7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374543618 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.2374543618
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.1578267467
Short name T421
Test name
Test status
Simulation time 54708308 ps
CPU time 0.71 seconds
Started Aug 13 05:35:28 PM PDT 24
Finished Aug 13 05:35:29 PM PDT 24
Peak memory 204948 kb
Host smart-ab21d775-5db1-4085-8f66-3430a910f29f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578267467 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.1578267467
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.683624377
Short name T155
Test name
Test status
Simulation time 614285751 ps
CPU time 8.25 seconds
Started Aug 13 05:35:25 PM PDT 24
Finished Aug 13 05:35:33 PM PDT 24
Peak memory 205180 kb
Host smart-0e8d9bfb-6f6b-407a-8276-179f30be0af7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683624377 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_c
sr_outstanding.683624377
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.2060532265
Short name T356
Test name
Test status
Simulation time 2726177768 ps
CPU time 35.97 seconds
Started Aug 13 05:35:23 PM PDT 24
Finished Aug 13 05:35:59 PM PDT 24
Peak memory 216648 kb
Host smart-492df19c-c261-4053-a3ba-7af0fb3b97d4
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060532265 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.2060532265
Directory /workspace/1.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.980440763
Short name T435
Test name
Test status
Simulation time 214814756 ps
CPU time 3.64 seconds
Started Aug 13 05:35:17 PM PDT 24
Finished Aug 13 05:35:20 PM PDT 24
Peak memory 213556 kb
Host smart-e69852c1-6eb8-4709-ad49-3e01dd66d6a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980440763 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.980440763
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.2384888871
Short name T112
Test name
Test status
Simulation time 57459574 ps
CPU time 1.96 seconds
Started Aug 13 05:35:46 PM PDT 24
Finished Aug 13 05:35:48 PM PDT 24
Peak memory 217380 kb
Host smart-079c7eb7-e84e-4c9a-9574-f91dd11cefae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384888871 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.2384888871
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.3006398099
Short name T398
Test name
Test status
Simulation time 59524815 ps
CPU time 1.53 seconds
Started Aug 13 05:35:44 PM PDT 24
Finished Aug 13 05:35:46 PM PDT 24
Peak memory 218520 kb
Host smart-45b04c30-30dd-404c-8bbd-b1147036bdf7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006398099 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.3006398099
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.2766827483
Short name T407
Test name
Test status
Simulation time 4115886453 ps
CPU time 8.24 seconds
Started Aug 13 05:35:50 PM PDT 24
Finished Aug 13 05:35:58 PM PDT 24
Peak memory 205268 kb
Host smart-a5bc92d3-ea04-4663-85fe-e2e448de0fe4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766827483 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.rv_dm_jtag_dmi_csr_bit_bash.2766827483
Directory /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.1765052358
Short name T338
Test name
Test status
Simulation time 3303504212 ps
CPU time 5.51 seconds
Started Aug 13 05:35:46 PM PDT 24
Finished Aug 13 05:35:52 PM PDT 24
Peak memory 205220 kb
Host smart-c42c06fa-3578-4530-9c24-6f05aaaa2fb4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765052358 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.
1765052358
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.3173930534
Short name T379
Test name
Test status
Simulation time 998957786 ps
CPU time 0.98 seconds
Started Aug 13 05:35:46 PM PDT 24
Finished Aug 13 05:35:48 PM PDT 24
Peak memory 204920 kb
Host smart-1365a91a-b862-4c64-85da-620ca1117680
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173930534 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
3173930534
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.776388840
Short name T474
Test name
Test status
Simulation time 585553073 ps
CPU time 8.04 seconds
Started Aug 13 05:35:55 PM PDT 24
Finished Aug 13 05:36:03 PM PDT 24
Peak memory 205252 kb
Host smart-6202b9eb-ddfd-4755-8235-9e236690e678
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776388840 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same_
csr_outstanding.776388840
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.2643022934
Short name T362
Test name
Test status
Simulation time 1049269225 ps
CPU time 6.07 seconds
Started Aug 13 05:35:47 PM PDT 24
Finished Aug 13 05:35:54 PM PDT 24
Peak memory 213588 kb
Host smart-dea92739-0e52-4bfa-9d64-2aefbe25fc41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643022934 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.2643022934
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3449886718
Short name T160
Test name
Test status
Simulation time 529713278 ps
CPU time 2.29 seconds
Started Aug 13 05:35:53 PM PDT 24
Finished Aug 13 05:35:55 PM PDT 24
Peak memory 217268 kb
Host smart-b2bf3332-5905-4e1d-aa7c-8dde9f40e0e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449886718 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.3449886718
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.69646428
Short name T418
Test name
Test status
Simulation time 14075117413 ps
CPU time 12.14 seconds
Started Aug 13 05:35:45 PM PDT 24
Finished Aug 13 05:35:57 PM PDT 24
Peak memory 205236 kb
Host smart-db699a64-0fb3-475a-b5a7-84bafb4df72c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69646428 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.r
v_dm_jtag_dmi_csr_bit_bash.69646428
Directory /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3059546811
Short name T389
Test name
Test status
Simulation time 3177567096 ps
CPU time 8.78 seconds
Started Aug 13 05:35:50 PM PDT 24
Finished Aug 13 05:35:59 PM PDT 24
Peak memory 205248 kb
Host smart-b44965f4-7e76-443e-a669-267ca428db4d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059546811 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
3059546811
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.572867316
Short name T343
Test name
Test status
Simulation time 114113355 ps
CPU time 0.93 seconds
Started Aug 13 05:35:59 PM PDT 24
Finished Aug 13 05:36:00 PM PDT 24
Peak memory 204876 kb
Host smart-e3adea41-d38f-4fd5-96df-9abcac227a7d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572867316 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.572867316
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.2899426716
Short name T146
Test name
Test status
Simulation time 161770886 ps
CPU time 3.65 seconds
Started Aug 13 05:35:50 PM PDT 24
Finished Aug 13 05:35:54 PM PDT 24
Peak memory 205144 kb
Host smart-6a5e3ca3-424b-4385-8333-1bc368e965a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899426716 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same
_csr_outstanding.2899426716
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.3016756640
Short name T372
Test name
Test status
Simulation time 56869220 ps
CPU time 2.83 seconds
Started Aug 13 05:35:52 PM PDT 24
Finished Aug 13 05:35:55 PM PDT 24
Peak memory 213664 kb
Host smart-9a085ed4-3d26-4e3d-83d1-569d5cbc83ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016756640 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.3016756640
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.1570241035
Short name T468
Test name
Test status
Simulation time 1738322338 ps
CPU time 16.5 seconds
Started Aug 13 05:35:49 PM PDT 24
Finished Aug 13 05:36:05 PM PDT 24
Peak memory 221524 kb
Host smart-d0223021-16df-4f65-b9f2-585db1664d10
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570241035 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.1
570241035
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.3851358050
Short name T410
Test name
Test status
Simulation time 144577349 ps
CPU time 2.07 seconds
Started Aug 13 05:35:53 PM PDT 24
Finished Aug 13 05:35:55 PM PDT 24
Peak memory 213612 kb
Host smart-3804c8d9-c4d6-44af-81c4-073cc619e6ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851358050 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.3851358050
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.1567020411
Short name T387
Test name
Test status
Simulation time 225862181 ps
CPU time 2.36 seconds
Started Aug 13 05:35:46 PM PDT 24
Finished Aug 13 05:35:49 PM PDT 24
Peak memory 218772 kb
Host smart-ea08695b-136e-4602-90af-daa3743a7d6b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567020411 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.1567020411
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.4621810
Short name T436
Test name
Test status
Simulation time 73629600301 ps
CPU time 77.01 seconds
Started Aug 13 05:35:52 PM PDT 24
Finished Aug 13 05:37:09 PM PDT 24
Peak memory 205164 kb
Host smart-2b60f0f9-4d19-48c6-a49f-7583e2b0d7b0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4621810 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv
_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv
_dm_jtag_dmi_csr_bit_bash.4621810
Directory /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.2204868264
Short name T409
Test name
Test status
Simulation time 4082580340 ps
CPU time 6.91 seconds
Started Aug 13 05:35:44 PM PDT 24
Finished Aug 13 05:35:51 PM PDT 24
Peak memory 205424 kb
Host smart-3374c457-4cc4-41e9-8748-2923ef8269ec
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204868264 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.
2204868264
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.2973948355
Short name T352
Test name
Test status
Simulation time 105461242 ps
CPU time 0.83 seconds
Started Aug 13 05:35:46 PM PDT 24
Finished Aug 13 05:35:47 PM PDT 24
Peak memory 204972 kb
Host smart-265a77be-f3c3-4858-b1c9-aa429e7ffb00
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973948355 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
2973948355
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.2142629431
Short name T376
Test name
Test status
Simulation time 181166074 ps
CPU time 2.59 seconds
Started Aug 13 05:35:46 PM PDT 24
Finished Aug 13 05:35:49 PM PDT 24
Peak memory 213624 kb
Host smart-6f15fcb8-37b0-429f-af14-095d701c4310
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142629431 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.2142629431
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3411762895
Short name T192
Test name
Test status
Simulation time 2072233775 ps
CPU time 10.41 seconds
Started Aug 13 05:35:44 PM PDT 24
Finished Aug 13 05:35:54 PM PDT 24
Peak memory 221628 kb
Host smart-1ad60d54-7f2e-40cf-9d86-dbd737182fcb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411762895 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.3
411762895
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.1477685189
Short name T127
Test name
Test status
Simulation time 136754832 ps
CPU time 2.54 seconds
Started Aug 13 05:35:52 PM PDT 24
Finished Aug 13 05:35:55 PM PDT 24
Peak memory 213508 kb
Host smart-97198ee5-ae6d-4ef7-a54e-11dec365c424
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477685189 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.1477685189
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.2872174260
Short name T480
Test name
Test status
Simulation time 4719969715 ps
CPU time 14.3 seconds
Started Aug 13 05:35:48 PM PDT 24
Finished Aug 13 05:36:02 PM PDT 24
Peak memory 205248 kb
Host smart-af918507-d4e2-4c02-8bb3-8b528b32d738
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872174260 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.rv_dm_jtag_dmi_csr_bit_bash.2872174260
Directory /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.2559610233
Short name T397
Test name
Test status
Simulation time 3906457630 ps
CPU time 7.55 seconds
Started Aug 13 05:35:47 PM PDT 24
Finished Aug 13 05:35:55 PM PDT 24
Peak memory 205220 kb
Host smart-1e873081-b16e-4ee0-bd28-936b674c19cb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559610233 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
2559610233
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2153796936
Short name T415
Test name
Test status
Simulation time 324026440 ps
CPU time 1.04 seconds
Started Aug 13 05:35:46 PM PDT 24
Finished Aug 13 05:35:47 PM PDT 24
Peak memory 204972 kb
Host smart-5394285f-268b-4995-8e02-c98e270187d6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153796936 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
2153796936
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.3078066093
Short name T455
Test name
Test status
Simulation time 736668321 ps
CPU time 6.46 seconds
Started Aug 13 05:35:49 PM PDT 24
Finished Aug 13 05:35:55 PM PDT 24
Peak memory 205112 kb
Host smart-51a9b3d2-a0cb-4be6-9e9d-14440ad2a890
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078066093 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.3078066093
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.3537750357
Short name T412
Test name
Test status
Simulation time 115620434 ps
CPU time 2.65 seconds
Started Aug 13 05:35:51 PM PDT 24
Finished Aug 13 05:35:53 PM PDT 24
Peak memory 213468 kb
Host smart-aabaf62c-930a-4c83-b740-757dc7ff4a5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537750357 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.3537750357
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.2159365895
Short name T163
Test name
Test status
Simulation time 1734146853 ps
CPU time 15.92 seconds
Started Aug 13 05:35:47 PM PDT 24
Finished Aug 13 05:36:03 PM PDT 24
Peak memory 215684 kb
Host smart-e0e7e1eb-627a-4791-854f-c657415b672b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159365895 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.2
159365895
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.435242551
Short name T439
Test name
Test status
Simulation time 127839841 ps
CPU time 2.36 seconds
Started Aug 13 05:35:52 PM PDT 24
Finished Aug 13 05:35:55 PM PDT 24
Peak memory 217360 kb
Host smart-a1377c92-b4f0-4e43-b214-08a92557ebc5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435242551 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.435242551
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.2488020726
Short name T447
Test name
Test status
Simulation time 172500372 ps
CPU time 2.39 seconds
Started Aug 13 05:35:49 PM PDT 24
Finished Aug 13 05:35:52 PM PDT 24
Peak memory 213484 kb
Host smart-afc47296-ace7-4bfa-a982-d8b446e4725e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488020726 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.2488020726
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.60478482
Short name T459
Test name
Test status
Simulation time 56045989044 ps
CPU time 50.16 seconds
Started Aug 13 05:35:48 PM PDT 24
Finished Aug 13 05:36:39 PM PDT 24
Peak memory 205172 kb
Host smart-d4f5fc80-ede9-443d-a53d-6e8e73bf26cc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60478482 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.r
v_dm_jtag_dmi_csr_bit_bash.60478482
Directory /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.3200392012
Short name T383
Test name
Test status
Simulation time 3474484121 ps
CPU time 6.67 seconds
Started Aug 13 05:35:52 PM PDT 24
Finished Aug 13 05:35:59 PM PDT 24
Peak memory 205192 kb
Host smart-28154ca0-7d3d-4eee-8686-9864e519a9ba
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200392012 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
3200392012
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.1620279994
Short name T395
Test name
Test status
Simulation time 85050960 ps
CPU time 0.88 seconds
Started Aug 13 05:35:44 PM PDT 24
Finished Aug 13 05:35:45 PM PDT 24
Peak memory 204956 kb
Host smart-101b84d3-0802-45cc-92b9-b7386127fd15
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620279994 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
1620279994
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3971173503
Short name T426
Test name
Test status
Simulation time 354872517 ps
CPU time 4.49 seconds
Started Aug 13 05:35:44 PM PDT 24
Finished Aug 13 05:35:49 PM PDT 24
Peak memory 205084 kb
Host smart-cdf74b47-eefa-4d75-b84d-f75798ec421c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971173503 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.3971173503
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.626741815
Short name T332
Test name
Test status
Simulation time 237656250 ps
CPU time 2.69 seconds
Started Aug 13 05:35:52 PM PDT 24
Finished Aug 13 05:35:55 PM PDT 24
Peak memory 213560 kb
Host smart-59ff6214-fa70-46c7-add2-a94ccf17cae2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626741815 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.626741815
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3316242883
Short name T186
Test name
Test status
Simulation time 1242808474 ps
CPU time 10.73 seconds
Started Aug 13 05:35:44 PM PDT 24
Finished Aug 13 05:35:55 PM PDT 24
Peak memory 221452 kb
Host smart-20d43079-a353-4894-8583-c04c51f73bb4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316242883 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.3
316242883
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1003367687
Short name T358
Test name
Test status
Simulation time 585870016 ps
CPU time 2.92 seconds
Started Aug 13 05:35:51 PM PDT 24
Finished Aug 13 05:35:54 PM PDT 24
Peak memory 217252 kb
Host smart-50108aa0-12fb-4066-b8b3-a54ec5c13683
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003367687 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.1003367687
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2990532782
Short name T360
Test name
Test status
Simulation time 214826890 ps
CPU time 2.5 seconds
Started Aug 13 05:35:52 PM PDT 24
Finished Aug 13 05:35:55 PM PDT 24
Peak memory 218876 kb
Host smart-8368ef4d-1c6f-4960-9722-2637eb58d1d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990532782 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.2990532782
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.554196158
Short name T422
Test name
Test status
Simulation time 16499992082 ps
CPU time 46.7 seconds
Started Aug 13 05:35:51 PM PDT 24
Finished Aug 13 05:36:38 PM PDT 24
Peak memory 205288 kb
Host smart-1d899f04-57aa-423f-a91b-fccaa378729a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554196158 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
rv_dm_jtag_dmi_csr_bit_bash.554196158
Directory /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.2487562230
Short name T471
Test name
Test status
Simulation time 10650361238 ps
CPU time 10.82 seconds
Started Aug 13 05:35:47 PM PDT 24
Finished Aug 13 05:35:58 PM PDT 24
Peak memory 205216 kb
Host smart-15b1f816-9621-43f6-932b-ceca39ae5c31
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487562230 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
2487562230
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3504460813
Short name T434
Test name
Test status
Simulation time 216736242 ps
CPU time 1.2 seconds
Started Aug 13 05:35:50 PM PDT 24
Finished Aug 13 05:35:52 PM PDT 24
Peak memory 204948 kb
Host smart-a9e5166d-41b3-4ea1-a108-a8fe363e0067
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504460813 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
3504460813
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.1696657318
Short name T159
Test name
Test status
Simulation time 176996258 ps
CPU time 3.76 seconds
Started Aug 13 05:35:50 PM PDT 24
Finished Aug 13 05:35:54 PM PDT 24
Peak memory 205272 kb
Host smart-0283c87f-e074-4361-837c-cd3bdc4bec5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696657318 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.1696657318
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.3995191685
Short name T369
Test name
Test status
Simulation time 239327603 ps
CPU time 5.86 seconds
Started Aug 13 05:35:48 PM PDT 24
Finished Aug 13 05:35:54 PM PDT 24
Peak memory 213512 kb
Host smart-19d6e893-0b87-4df8-8240-120cb3812013
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995191685 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.3995191685
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2773682557
Short name T445
Test name
Test status
Simulation time 1579630346 ps
CPU time 11.37 seconds
Started Aug 13 05:35:49 PM PDT 24
Finished Aug 13 05:36:00 PM PDT 24
Peak memory 221652 kb
Host smart-277e3ce4-87dd-4d86-bd4d-4a9a7fa31bca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773682557 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.2
773682557
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.1311711702
Short name T465
Test name
Test status
Simulation time 153512542 ps
CPU time 2.55 seconds
Started Aug 13 05:36:06 PM PDT 24
Finished Aug 13 05:36:09 PM PDT 24
Peak memory 217248 kb
Host smart-edaf9061-7179-463d-8c0a-906f0af62097
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311711702 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.1311711702
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.2318548425
Short name T425
Test name
Test status
Simulation time 172397181 ps
CPU time 1.52 seconds
Started Aug 13 05:35:59 PM PDT 24
Finished Aug 13 05:36:00 PM PDT 24
Peak memory 213396 kb
Host smart-6ebfedaa-3dd8-41ee-9318-590e29df21ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318548425 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.2318548425
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.1451885803
Short name T341
Test name
Test status
Simulation time 27625617866 ps
CPU time 39.66 seconds
Started Aug 13 05:35:46 PM PDT 24
Finished Aug 13 05:36:26 PM PDT 24
Peak memory 205216 kb
Host smart-ec1e20c3-b76d-4f8e-8b96-ecb87b36b05b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451885803 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.rv_dm_jtag_dmi_csr_bit_bash.1451885803
Directory /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.3803360151
Short name T367
Test name
Test status
Simulation time 3545018709 ps
CPU time 10.82 seconds
Started Aug 13 05:35:46 PM PDT 24
Finished Aug 13 05:35:57 PM PDT 24
Peak memory 205148 kb
Host smart-35b37f97-0c73-4ed9-8a99-b7bcf29450a9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803360151 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
3803360151
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3565389805
Short name T451
Test name
Test status
Simulation time 202712593 ps
CPU time 0.87 seconds
Started Aug 13 05:35:49 PM PDT 24
Finished Aug 13 05:35:50 PM PDT 24
Peak memory 204832 kb
Host smart-f38b37c0-53c2-451a-88e9-629fd97eeb8b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565389805 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
3565389805
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.178444652
Short name T156
Test name
Test status
Simulation time 183625432 ps
CPU time 6.52 seconds
Started Aug 13 05:35:52 PM PDT 24
Finished Aug 13 05:35:59 PM PDT 24
Peak memory 205252 kb
Host smart-3363cf67-9710-40c3-8aea-fb4312d7326d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178444652 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same_
csr_outstanding.178444652
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.388362680
Short name T334
Test name
Test status
Simulation time 315442907 ps
CPU time 5.42 seconds
Started Aug 13 05:35:50 PM PDT 24
Finished Aug 13 05:35:55 PM PDT 24
Peak memory 213552 kb
Host smart-912e960c-21e8-42b6-a3ca-a799586a12bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388362680 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.388362680
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.2645535005
Short name T433
Test name
Test status
Simulation time 1199256602 ps
CPU time 9.69 seconds
Started Aug 13 05:35:45 PM PDT 24
Finished Aug 13 05:35:55 PM PDT 24
Peak memory 213396 kb
Host smart-5b0febf3-5250-4e58-9d13-bc537f450a41
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645535005 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.2
645535005
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.2290123066
Short name T340
Test name
Test status
Simulation time 59717762 ps
CPU time 1.95 seconds
Started Aug 13 05:35:54 PM PDT 24
Finished Aug 13 05:35:56 PM PDT 24
Peak memory 213608 kb
Host smart-91b84834-6718-43d7-9b65-57a71a982a64
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290123066 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.2290123066
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.36781925
Short name T430
Test name
Test status
Simulation time 87590231 ps
CPU time 2.24 seconds
Started Aug 13 05:35:54 PM PDT 24
Finished Aug 13 05:35:56 PM PDT 24
Peak memory 218820 kb
Host smart-b1112e71-fc96-4e67-8a01-1cafc7755cb4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36781925 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.36781925
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.2270309383
Short name T368
Test name
Test status
Simulation time 86525694485 ps
CPU time 223.24 seconds
Started Aug 13 05:35:47 PM PDT 24
Finished Aug 13 05:39:30 PM PDT 24
Peak memory 205268 kb
Host smart-e672e8fa-0b2f-49de-b20b-8145089b317d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270309383 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.rv_dm_jtag_dmi_csr_bit_bash.2270309383
Directory /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.2561720020
Short name T408
Test name
Test status
Simulation time 3094912956 ps
CPU time 8.4 seconds
Started Aug 13 05:35:49 PM PDT 24
Finished Aug 13 05:35:57 PM PDT 24
Peak memory 205184 kb
Host smart-d095cc50-8487-4195-a81e-cf0104a26ee2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561720020 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.
2561720020
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.134767943
Short name T464
Test name
Test status
Simulation time 332519338 ps
CPU time 1.17 seconds
Started Aug 13 05:35:59 PM PDT 24
Finished Aug 13 05:36:00 PM PDT 24
Peak memory 204872 kb
Host smart-bee36f75-8764-46c2-abec-7f51ced7e2f3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134767943 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.134767943
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.3874317173
Short name T145
Test name
Test status
Simulation time 369186835 ps
CPU time 4.8 seconds
Started Aug 13 05:35:59 PM PDT 24
Finished Aug 13 05:36:04 PM PDT 24
Peak memory 205192 kb
Host smart-2c02593a-4e23-4093-ab76-1ac56a9c1517
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874317173 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.3874317173
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.3158137584
Short name T162
Test name
Test status
Simulation time 237816430 ps
CPU time 3.38 seconds
Started Aug 13 05:36:08 PM PDT 24
Finished Aug 13 05:36:11 PM PDT 24
Peak memory 213568 kb
Host smart-2e4da170-6b69-4e6c-a598-831ad0f8c144
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158137584 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.3158137584
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.640867527
Short name T107
Test name
Test status
Simulation time 116204617 ps
CPU time 3.67 seconds
Started Aug 13 05:35:46 PM PDT 24
Finished Aug 13 05:35:50 PM PDT 24
Peak memory 221728 kb
Host smart-924e6fba-8a05-4ee4-b18c-f47efc573367
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640867527 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.640867527
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.2865578939
Short name T126
Test name
Test status
Simulation time 255243970 ps
CPU time 1.62 seconds
Started Aug 13 05:35:49 PM PDT 24
Finished Aug 13 05:35:51 PM PDT 24
Peak memory 218568 kb
Host smart-64b17832-7902-4c40-baf6-1e5135a6669b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865578939 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.2865578939
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.812995388
Short name T357
Test name
Test status
Simulation time 31419494304 ps
CPU time 35.24 seconds
Started Aug 13 05:35:50 PM PDT 24
Finished Aug 13 05:36:26 PM PDT 24
Peak memory 205312 kb
Host smart-453f0f86-8a82-472a-b8ce-8dc0745f8dda
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812995388 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
rv_dm_jtag_dmi_csr_bit_bash.812995388
Directory /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.1928709122
Short name T348
Test name
Test status
Simulation time 2991038987 ps
CPU time 4.35 seconds
Started Aug 13 05:35:54 PM PDT 24
Finished Aug 13 05:35:58 PM PDT 24
Peak memory 205280 kb
Host smart-f3d5ffb0-39f8-48dd-b029-86c5752ce2d7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928709122 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
1928709122
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2545038149
Short name T472
Test name
Test status
Simulation time 120727139 ps
CPU time 0.75 seconds
Started Aug 13 05:35:50 PM PDT 24
Finished Aug 13 05:35:51 PM PDT 24
Peak memory 204860 kb
Host smart-ed962b5e-d622-410d-9cb7-3e749ec78d24
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545038149 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
2545038149
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.1140865031
Short name T158
Test name
Test status
Simulation time 298826862 ps
CPU time 4.43 seconds
Started Aug 13 05:35:52 PM PDT 24
Finished Aug 13 05:35:57 PM PDT 24
Peak memory 205116 kb
Host smart-3052d3e3-8006-49fa-ba5b-67d412e32b3e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140865031 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.1140865031
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.3219427595
Short name T349
Test name
Test status
Simulation time 139262665 ps
CPU time 5.86 seconds
Started Aug 13 05:35:54 PM PDT 24
Finished Aug 13 05:36:00 PM PDT 24
Peak memory 213596 kb
Host smart-dc540709-f362-43b3-93c6-04e3b5ad4134
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219427595 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.3219427595
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.1666724925
Short name T444
Test name
Test status
Simulation time 5004180405 ps
CPU time 17.47 seconds
Started Aug 13 05:35:54 PM PDT 24
Finished Aug 13 05:36:12 PM PDT 24
Peak memory 221776 kb
Host smart-d71a79de-c697-418f-8fb8-079f77e37310
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666724925 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.1
666724925
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.185135450
Short name T103
Test name
Test status
Simulation time 107049835 ps
CPU time 2.04 seconds
Started Aug 13 05:35:52 PM PDT 24
Finished Aug 13 05:35:54 PM PDT 24
Peak memory 213620 kb
Host smart-9ec8e279-64c7-4974-a9e8-688ff785a55c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185135450 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.185135450
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.692533439
Short name T152
Test name
Test status
Simulation time 85571972 ps
CPU time 1.45 seconds
Started Aug 13 05:35:59 PM PDT 24
Finished Aug 13 05:36:01 PM PDT 24
Peak memory 218792 kb
Host smart-aafe908a-47ab-4147-b8b9-f54d4ba3aa1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692533439 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.692533439
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.4051558899
Short name T481
Test name
Test status
Simulation time 16630608577 ps
CPU time 46.96 seconds
Started Aug 13 05:35:51 PM PDT 24
Finished Aug 13 05:36:38 PM PDT 24
Peak memory 205248 kb
Host smart-32abe8e7-3560-42f3-b67f-02a06a19e471
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051558899 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.rv_dm_jtag_dmi_csr_bit_bash.4051558899
Directory /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2787307989
Short name T393
Test name
Test status
Simulation time 1959274856 ps
CPU time 5.98 seconds
Started Aug 13 05:35:54 PM PDT 24
Finished Aug 13 05:36:00 PM PDT 24
Peak memory 205200 kb
Host smart-4874d01e-ffd4-46de-9124-5045598afcec
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787307989 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.
2787307989
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.3395769556
Short name T399
Test name
Test status
Simulation time 101458401 ps
CPU time 0.93 seconds
Started Aug 13 05:35:51 PM PDT 24
Finished Aug 13 05:35:52 PM PDT 24
Peak memory 204960 kb
Host smart-f6bb6c47-f8cf-4481-8568-7a64348d0444
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395769556 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
3395769556
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.3309333432
Short name T424
Test name
Test status
Simulation time 3208250321 ps
CPU time 8.93 seconds
Started Aug 13 05:35:56 PM PDT 24
Finished Aug 13 05:36:05 PM PDT 24
Peak memory 205176 kb
Host smart-1f52904a-1540-4b86-b58d-d7e2da28c2ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309333432 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.3309333432
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.944365687
Short name T394
Test name
Test status
Simulation time 335529490 ps
CPU time 6.13 seconds
Started Aug 13 05:35:46 PM PDT 24
Finished Aug 13 05:35:53 PM PDT 24
Peak memory 213496 kb
Host smart-43c38387-5438-4619-8a20-5e314a1c9683
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944365687 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.944365687
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.3757188073
Short name T187
Test name
Test status
Simulation time 3529507444 ps
CPU time 20.11 seconds
Started Aug 13 05:35:52 PM PDT 24
Finished Aug 13 05:36:12 PM PDT 24
Peak memory 216444 kb
Host smart-4d74d071-9d35-4778-a949-12a9e314fb43
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757188073 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.3
757188073
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.125046569
Short name T150
Test name
Test status
Simulation time 2176416369 ps
CPU time 27.36 seconds
Started Aug 13 05:35:23 PM PDT 24
Finished Aug 13 05:35:50 PM PDT 24
Peak memory 214476 kb
Host smart-056624ca-bb0f-474e-a8e7-322cbaa7e89e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125046569 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.rv_dm_csr_aliasing.125046569
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.260569934
Short name T432
Test name
Test status
Simulation time 22420179340 ps
CPU time 38.35 seconds
Started Aug 13 05:35:22 PM PDT 24
Finished Aug 13 05:36:01 PM PDT 24
Peak memory 205336 kb
Host smart-e46c4b89-62a8-4a5f-b944-c6bcc46af817
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260569934 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.260569934
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3325449308
Short name T133
Test name
Test status
Simulation time 144292150 ps
CPU time 2.62 seconds
Started Aug 13 05:35:25 PM PDT 24
Finished Aug 13 05:35:28 PM PDT 24
Peak memory 213372 kb
Host smart-e2e662bc-1740-4655-a762-e528951bfe95
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325449308 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.3325449308
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3997225762
Short name T431
Test name
Test status
Simulation time 174049308 ps
CPU time 2.13 seconds
Started Aug 13 05:35:21 PM PDT 24
Finished Aug 13 05:35:23 PM PDT 24
Peak memory 213592 kb
Host smart-152c8134-fb7a-4846-b790-ac9db4ea0fa6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997225762 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.3997225762
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.3660835336
Short name T128
Test name
Test status
Simulation time 111404014 ps
CPU time 1.56 seconds
Started Aug 13 05:35:22 PM PDT 24
Finished Aug 13 05:35:24 PM PDT 24
Peak memory 213336 kb
Host smart-d589fc43-151c-49f4-b890-d2d83c8b6334
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660835336 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.3660835336
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.1540347999
Short name T336
Test name
Test status
Simulation time 222695241732 ps
CPU time 304.87 seconds
Started Aug 13 05:35:22 PM PDT 24
Finished Aug 13 05:40:27 PM PDT 24
Peak memory 205128 kb
Host smart-33c211f5-2d2d-4257-a958-6261f23263d5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540347999 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_aliasing.1540347999
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.2835963156
Short name T420
Test name
Test status
Simulation time 4091547954 ps
CPU time 2.84 seconds
Started Aug 13 05:35:24 PM PDT 24
Finished Aug 13 05:35:27 PM PDT 24
Peak memory 205124 kb
Host smart-afc4947d-3d7d-4e76-9541-dce2192d32fe
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835963156 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
rv_dm_jtag_dmi_csr_bit_bash.2835963156
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.3711505283
Short name T138
Test name
Test status
Simulation time 2591084231 ps
CPU time 8.48 seconds
Started Aug 13 05:35:28 PM PDT 24
Finished Aug 13 05:35:37 PM PDT 24
Peak memory 205308 kb
Host smart-3dbb888f-2d7c-4566-b8f0-989d081ae4ad
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711505283 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.3711505283
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.2129465206
Short name T479
Test name
Test status
Simulation time 11128265748 ps
CPU time 14.76 seconds
Started Aug 13 05:35:20 PM PDT 24
Finished Aug 13 05:35:35 PM PDT 24
Peak memory 205088 kb
Host smart-98e1d295-f27e-45e5-b9d9-9a1a5d008a65
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129465206 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.2
129465206
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.3459979379
Short name T423
Test name
Test status
Simulation time 1297759364 ps
CPU time 1.78 seconds
Started Aug 13 05:35:21 PM PDT 24
Finished Aug 13 05:35:23 PM PDT 24
Peak memory 204952 kb
Host smart-02031ec6-1098-4321-9b1b-1eb7996e1eba
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459979379 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_aliasing.3459979379
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.3903576348
Short name T365
Test name
Test status
Simulation time 5887064939 ps
CPU time 6.37 seconds
Started Aug 13 05:35:22 PM PDT 24
Finished Aug 13 05:35:28 PM PDT 24
Peak memory 205220 kb
Host smart-060dbb4d-4280-41e4-a34b-139e053fe858
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903576348 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_bit_bash.3903576348
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3593710744
Short name T353
Test name
Test status
Simulation time 289059188 ps
CPU time 1.55 seconds
Started Aug 13 05:35:22 PM PDT 24
Finished Aug 13 05:35:24 PM PDT 24
Peak memory 204900 kb
Host smart-98e86a41-554b-44fb-b15d-6601177fca0a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593710744 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.3593710744
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.362656261
Short name T441
Test name
Test status
Simulation time 260527699 ps
CPU time 0.87 seconds
Started Aug 13 05:35:25 PM PDT 24
Finished Aug 13 05:35:26 PM PDT 24
Peak memory 204660 kb
Host smart-d25978a9-a737-48f8-934b-b7e6004c032a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362656261 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.362656261
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.4110626865
Short name T350
Test name
Test status
Simulation time 38245377 ps
CPU time 0.76 seconds
Started Aug 13 05:35:20 PM PDT 24
Finished Aug 13 05:35:21 PM PDT 24
Peak memory 204924 kb
Host smart-2dfc35a6-0697-45c7-9904-336ecb46ca10
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110626865 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.4110626865
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.3547108484
Short name T333
Test name
Test status
Simulation time 102161704 ps
CPU time 0.94 seconds
Started Aug 13 05:35:25 PM PDT 24
Finished Aug 13 05:35:26 PM PDT 24
Peak memory 204800 kb
Host smart-c22ad6ae-9f99-4414-b732-0f6770ee39b2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547108484 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.3547108484
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.233181848
Short name T144
Test name
Test status
Simulation time 289152965 ps
CPU time 3.69 seconds
Started Aug 13 05:35:24 PM PDT 24
Finished Aug 13 05:35:28 PM PDT 24
Peak memory 205236 kb
Host smart-81e579bc-6f77-46f2-a2f3-4d95e9dfb127
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233181848 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_c
sr_outstanding.233181848
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.1918946335
Short name T448
Test name
Test status
Simulation time 5884518068 ps
CPU time 37.92 seconds
Started Aug 13 05:35:25 PM PDT 24
Finished Aug 13 05:36:03 PM PDT 24
Peak memory 216716 kb
Host smart-2fbd8a2b-818b-48c4-9487-95dfc859d70b
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918946335 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.1918946335
Directory /workspace/2.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.3445977563
Short name T354
Test name
Test status
Simulation time 929875300 ps
CPU time 2.54 seconds
Started Aug 13 05:35:23 PM PDT 24
Finished Aug 13 05:35:26 PM PDT 24
Peak memory 213508 kb
Host smart-baea245b-3da3-49be-abc9-8b525967743e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445977563 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.3445977563
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.866664677
Short name T147
Test name
Test status
Simulation time 8644674841 ps
CPU time 76.03 seconds
Started Aug 13 05:35:22 PM PDT 24
Finished Aug 13 05:36:38 PM PDT 24
Peak memory 213584 kb
Host smart-0c66aef2-3924-4f5c-a078-25f961fee2c4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866664677 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.rv_dm_csr_aliasing.866664677
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.884765025
Short name T419
Test name
Test status
Simulation time 14555008496 ps
CPU time 37.71 seconds
Started Aug 13 05:35:52 PM PDT 24
Finished Aug 13 05:36:29 PM PDT 24
Peak memory 213492 kb
Host smart-ac0d5c76-a7f8-41da-b2d1-28961cc5a78f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884765025 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.884765025
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.1128234441
Short name T134
Test name
Test status
Simulation time 203147245 ps
CPU time 1.55 seconds
Started Aug 13 05:35:21 PM PDT 24
Finished Aug 13 05:35:23 PM PDT 24
Peak memory 213436 kb
Host smart-23a3e8c5-eee2-4d17-9b15-d5770745ee17
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128234441 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.1128234441
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.2211996740
Short name T373
Test name
Test status
Simulation time 259536169 ps
CPU time 3.45 seconds
Started Aug 13 05:35:27 PM PDT 24
Finished Aug 13 05:35:31 PM PDT 24
Peak memory 219856 kb
Host smart-c3936f51-fd71-4fa9-9036-3ce68434f961
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211996740 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.2211996740
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.3053644648
Short name T443
Test name
Test status
Simulation time 377616184 ps
CPU time 2.35 seconds
Started Aug 13 05:35:29 PM PDT 24
Finished Aug 13 05:35:32 PM PDT 24
Peak memory 213420 kb
Host smart-503cd6a5-50bf-419b-85e5-9a4862342e9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053644648 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.3053644648
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.2464448808
Short name T384
Test name
Test status
Simulation time 21440131765 ps
CPU time 35.59 seconds
Started Aug 13 05:35:28 PM PDT 24
Finished Aug 13 05:36:04 PM PDT 24
Peak memory 205224 kb
Host smart-4d939b6f-c843-4995-b6ad-ebff43e247c9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464448808 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.2464448808
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.2282698793
Short name T473
Test name
Test status
Simulation time 46822855 ps
CPU time 0.77 seconds
Started Aug 13 05:35:29 PM PDT 24
Finished Aug 13 05:35:30 PM PDT 24
Peak memory 204948 kb
Host smart-29bf7398-8bb1-4fd9-ba0f-00e146a78b61
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282698793 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
rv_dm_jtag_dmi_csr_bit_bash.2282698793
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.4019507888
Short name T136
Test name
Test status
Simulation time 3393305980 ps
CPU time 3.47 seconds
Started Aug 13 05:35:29 PM PDT 24
Finished Aug 13 05:35:33 PM PDT 24
Peak memory 205280 kb
Host smart-6b2075e9-c70b-493e-96da-565c584eec3a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019507888 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_hw_reset.4019507888
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.3492523787
Short name T429
Test name
Test status
Simulation time 5959812782 ps
CPU time 16.99 seconds
Started Aug 13 05:35:22 PM PDT 24
Finished Aug 13 05:35:39 PM PDT 24
Peak memory 205256 kb
Host smart-94e9237a-2bbe-48c8-b589-d32d21dee050
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492523787 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.3
492523787
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.997827089
Short name T119
Test name
Test status
Simulation time 272490902 ps
CPU time 0.81 seconds
Started Aug 13 05:35:22 PM PDT 24
Finished Aug 13 05:35:23 PM PDT 24
Peak memory 204836 kb
Host smart-d577af13-0ec6-49b0-b791-19545a3113a3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997827089 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr
_aliasing.997827089
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.622217808
Short name T378
Test name
Test status
Simulation time 38409539849 ps
CPU time 29.91 seconds
Started Aug 13 05:35:21 PM PDT 24
Finished Aug 13 05:35:51 PM PDT 24
Peak memory 205204 kb
Host smart-1fb3a8f4-f2d1-4092-8a6e-a1ac79ca8eec
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622217808 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr
_bit_bash.622217808
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1768650359
Short name T382
Test name
Test status
Simulation time 105537445 ps
CPU time 0.94 seconds
Started Aug 13 05:35:26 PM PDT 24
Finished Aug 13 05:35:27 PM PDT 24
Peak memory 204944 kb
Host smart-1bbece32-d445-4fdc-af89-300b71f31157
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768650359 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_hw_reset.1768650359
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.1710837128
Short name T388
Test name
Test status
Simulation time 440357896 ps
CPU time 1.31 seconds
Started Aug 13 05:35:22 PM PDT 24
Finished Aug 13 05:35:24 PM PDT 24
Peak memory 205000 kb
Host smart-3e8cdac8-96fd-4cf7-a9ce-140b21be7f6c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710837128 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.1
710837128
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.1272738120
Short name T405
Test name
Test status
Simulation time 73919576 ps
CPU time 0.82 seconds
Started Aug 13 05:35:22 PM PDT 24
Finished Aug 13 05:35:23 PM PDT 24
Peak memory 204868 kb
Host smart-cf6a9093-2804-4324-b897-7b1454b521f8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272738120 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.1272738120
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.988740381
Short name T406
Test name
Test status
Simulation time 162892123 ps
CPU time 0.75 seconds
Started Aug 13 05:35:23 PM PDT 24
Finished Aug 13 05:35:24 PM PDT 24
Peak memory 204964 kb
Host smart-272ffed4-cd77-4833-8642-09e1247ea4c4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988740381 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.988740381
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.1241138108
Short name T141
Test name
Test status
Simulation time 948585767 ps
CPU time 7.67 seconds
Started Aug 13 05:35:52 PM PDT 24
Finished Aug 13 05:36:00 PM PDT 24
Peak memory 205244 kb
Host smart-626bb5fe-3654-4c71-a850-d3fabdfe9177
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241138108 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_
csr_outstanding.1241138108
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.2406353360
Short name T108
Test name
Test status
Simulation time 7461312038 ps
CPU time 68.12 seconds
Started Aug 13 05:35:21 PM PDT 24
Finished Aug 13 05:36:30 PM PDT 24
Peak memory 218200 kb
Host smart-d7ac5a4e-be8e-446e-a3cf-47943a6ae1f5
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406353360 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.2406353360
Directory /workspace/3.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.1456415917
Short name T390
Test name
Test status
Simulation time 183713410 ps
CPU time 2.37 seconds
Started Aug 13 05:35:25 PM PDT 24
Finished Aug 13 05:35:28 PM PDT 24
Peak memory 213532 kb
Host smart-c74f1ee1-0558-4f6f-a279-e5f9b0ef82ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456415917 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.1456415917
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.2499859448
Short name T452
Test name
Test status
Simulation time 2365786727 ps
CPU time 28.12 seconds
Started Aug 13 05:35:53 PM PDT 24
Finished Aug 13 05:36:22 PM PDT 24
Peak memory 205292 kb
Host smart-69a95cec-b389-482d-a2c7-420e547b5c4d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499859448 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.2499859448
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.3286387659
Short name T125
Test name
Test status
Simulation time 80724503364 ps
CPU time 79.92 seconds
Started Aug 13 05:35:32 PM PDT 24
Finished Aug 13 05:36:52 PM PDT 24
Peak memory 213456 kb
Host smart-fb2eb118-014e-4daf-b324-7b44ef2c9d44
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286387659 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.3286387659
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.3266988147
Short name T469
Test name
Test status
Simulation time 213653828 ps
CPU time 2.14 seconds
Started Aug 13 05:35:31 PM PDT 24
Finished Aug 13 05:35:33 PM PDT 24
Peak memory 213424 kb
Host smart-18855d3b-0c59-4109-80cd-f0cb7e73281a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266988147 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.3266988147
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.429016812
Short name T149
Test name
Test status
Simulation time 137931697 ps
CPU time 1.51 seconds
Started Aug 13 05:35:28 PM PDT 24
Finished Aug 13 05:35:30 PM PDT 24
Peak memory 218800 kb
Host smart-4ed20cae-0e62-4e86-91ae-536aa378fa60
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429016812 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.429016812
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.1620925896
Short name T339
Test name
Test status
Simulation time 93622177855 ps
CPU time 116.22 seconds
Started Aug 13 05:35:28 PM PDT 24
Finished Aug 13 05:37:25 PM PDT 24
Peak memory 205264 kb
Host smart-91bcc28b-8e96-4fe4-ba81-35176cbd5b3f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620925896 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_aliasing.1620925896
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.712123112
Short name T404
Test name
Test status
Simulation time 9234900391 ps
CPU time 14.12 seconds
Started Aug 13 05:35:51 PM PDT 24
Finished Aug 13 05:36:05 PM PDT 24
Peak memory 205200 kb
Host smart-730170d2-c406-45a2-a1db-62b7e8aeb0b7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712123112 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.r
v_dm_jtag_dmi_csr_bit_bash.712123112
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.3465081900
Short name T337
Test name
Test status
Simulation time 2360540310 ps
CPU time 4.89 seconds
Started Aug 13 05:35:29 PM PDT 24
Finished Aug 13 05:35:34 PM PDT 24
Peak memory 205100 kb
Host smart-ed235566-f3a2-49da-8479-ae213cb9b4f1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465081900 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.3465081900
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.1595921235
Short name T374
Test name
Test status
Simulation time 2393022911 ps
CPU time 6.06 seconds
Started Aug 13 05:35:26 PM PDT 24
Finished Aug 13 05:35:32 PM PDT 24
Peak memory 205232 kb
Host smart-7e45bccf-f5aa-4124-8990-b296a5380b09
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595921235 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.1
595921235
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.2546694428
Short name T120
Test name
Test status
Simulation time 752899754 ps
CPU time 1.75 seconds
Started Aug 13 05:35:27 PM PDT 24
Finished Aug 13 05:35:29 PM PDT 24
Peak memory 204856 kb
Host smart-a5ab7377-8e9d-4858-a497-26cef79b90d3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546694428 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_aliasing.2546694428
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2798353904
Short name T363
Test name
Test status
Simulation time 22522545071 ps
CPU time 20.21 seconds
Started Aug 13 05:35:30 PM PDT 24
Finished Aug 13 05:35:50 PM PDT 24
Peak memory 205196 kb
Host smart-bc9ccf58-b360-407a-b69a-6675079368d3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798353904 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.2798353904
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.3250262405
Short name T377
Test name
Test status
Simulation time 139723412 ps
CPU time 0.99 seconds
Started Aug 13 05:35:34 PM PDT 24
Finished Aug 13 05:35:36 PM PDT 24
Peak memory 204844 kb
Host smart-0a0e0633-cc81-4029-86aa-4655f8fb7b50
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250262405 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.3250262405
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.752145189
Short name T396
Test name
Test status
Simulation time 344434551 ps
CPU time 0.94 seconds
Started Aug 13 05:35:47 PM PDT 24
Finished Aug 13 05:35:48 PM PDT 24
Peak memory 204992 kb
Host smart-2388ff2b-d3ec-4312-85f2-d7cdfc9c6ad5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752145189 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.752145189
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.2758294802
Short name T359
Test name
Test status
Simulation time 49607636 ps
CPU time 0.69 seconds
Started Aug 13 05:35:45 PM PDT 24
Finished Aug 13 05:35:46 PM PDT 24
Peak memory 204992 kb
Host smart-f6337d3d-f999-427a-a103-0f107d2aceda
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758294802 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.2758294802
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.2834879766
Short name T335
Test name
Test status
Simulation time 28955883 ps
CPU time 0.71 seconds
Started Aug 13 05:35:28 PM PDT 24
Finished Aug 13 05:35:29 PM PDT 24
Peak memory 204908 kb
Host smart-e7af9799-7840-4b07-b861-1278ccc32fe8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834879766 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.2834879766
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3404779343
Short name T446
Test name
Test status
Simulation time 622652363 ps
CPU time 8.24 seconds
Started Aug 13 05:36:06 PM PDT 24
Finished Aug 13 05:36:15 PM PDT 24
Peak memory 205276 kb
Host smart-2acfd54a-f68f-4a2f-a8fa-67a6e445abed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404779343 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.3404779343
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.901528679
Short name T111
Test name
Test status
Simulation time 5373813171 ps
CPU time 132.59 seconds
Started Aug 13 05:35:30 PM PDT 24
Finished Aug 13 05:37:43 PM PDT 24
Peak memory 213672 kb
Host smart-dd9259b4-7e6c-4496-b37a-d161fe4303ef
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901528679 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.901528679
Directory /workspace/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.493665466
Short name T402
Test name
Test status
Simulation time 228592239 ps
CPU time 4.58 seconds
Started Aug 13 05:35:25 PM PDT 24
Finished Aug 13 05:35:30 PM PDT 24
Peak memory 213500 kb
Host smart-1ed7994d-abfc-4765-af9e-57750b646ee6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493665466 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.493665466
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1403874282
Short name T190
Test name
Test status
Simulation time 2291880981 ps
CPU time 18.91 seconds
Started Aug 13 05:35:30 PM PDT 24
Finished Aug 13 05:35:49 PM PDT 24
Peak memory 221700 kb
Host smart-139b84e7-0897-4f40-aceb-d9e4ed1aa451
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403874282 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.1403874282
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.2379244808
Short name T116
Test name
Test status
Simulation time 224302619 ps
CPU time 3.34 seconds
Started Aug 13 05:35:31 PM PDT 24
Finished Aug 13 05:35:35 PM PDT 24
Peak memory 217612 kb
Host smart-19c237ca-fdee-4163-97aa-c437bd459f88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379244808 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.2379244808
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.423419524
Short name T416
Test name
Test status
Simulation time 323196787 ps
CPU time 2.33 seconds
Started Aug 13 05:35:36 PM PDT 24
Finished Aug 13 05:35:38 PM PDT 24
Peak memory 218612 kb
Host smart-0dcf508c-3894-4c62-bdd9-268836f95e28
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423419524 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.423419524
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.3746750304
Short name T392
Test name
Test status
Simulation time 9652830481 ps
CPU time 28.19 seconds
Started Aug 13 05:35:30 PM PDT 24
Finished Aug 13 05:35:58 PM PDT 24
Peak memory 205276 kb
Host smart-9a357d2c-508f-4dab-a2f0-5aae940aecbd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746750304 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
rv_dm_jtag_dmi_csr_bit_bash.3746750304
Directory /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.2207180786
Short name T351
Test name
Test status
Simulation time 4940409947 ps
CPU time 5.46 seconds
Started Aug 13 05:35:34 PM PDT 24
Finished Aug 13 05:35:40 PM PDT 24
Peak memory 205168 kb
Host smart-27c69760-ca05-4ac9-a8d4-46d6e7a33bf5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207180786 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.2
207180786
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.3761885455
Short name T375
Test name
Test status
Simulation time 120034537 ps
CPU time 0.8 seconds
Started Aug 13 05:35:33 PM PDT 24
Finished Aug 13 05:35:34 PM PDT 24
Peak memory 204852 kb
Host smart-ec58bc12-11fa-45fb-aa65-7642e610a8af
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761885455 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.3
761885455
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.747232046
Short name T129
Test name
Test status
Simulation time 240414838 ps
CPU time 4.07 seconds
Started Aug 13 05:35:51 PM PDT 24
Finished Aug 13 05:35:56 PM PDT 24
Peak memory 205144 kb
Host smart-28695837-f95c-41bb-9255-fe9bb72cdbe7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747232046 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_c
sr_outstanding.747232046
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.2741791370
Short name T117
Test name
Test status
Simulation time 7209299650 ps
CPU time 67.34 seconds
Started Aug 13 05:35:34 PM PDT 24
Finished Aug 13 05:36:42 PM PDT 24
Peak memory 213572 kb
Host smart-88fb184d-8fce-4499-be06-2ad646960e7f
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741791370 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.2741791370
Directory /workspace/5.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.675339926
Short name T460
Test name
Test status
Simulation time 136527281 ps
CPU time 3.28 seconds
Started Aug 13 05:35:28 PM PDT 24
Finished Aug 13 05:35:31 PM PDT 24
Peak memory 213456 kb
Host smart-5f7f9bc8-9e7b-4c9a-a2e5-c65e609f06ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675339926 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.675339926
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.304451020
Short name T188
Test name
Test status
Simulation time 1182456444 ps
CPU time 10.85 seconds
Started Aug 13 05:35:44 PM PDT 24
Finished Aug 13 05:35:55 PM PDT 24
Peak memory 221640 kb
Host smart-57eff9fe-f1d7-482f-91de-90938a504ddd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304451020 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.304451020
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.3628675843
Short name T346
Test name
Test status
Simulation time 136317022 ps
CPU time 1.8 seconds
Started Aug 13 05:35:52 PM PDT 24
Finished Aug 13 05:35:54 PM PDT 24
Peak memory 216052 kb
Host smart-e9cbbf3b-1498-4b01-9e19-f39f69d71e87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628675843 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.3628675843
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.3061596024
Short name T414
Test name
Test status
Simulation time 119412996 ps
CPU time 2.32 seconds
Started Aug 13 05:35:49 PM PDT 24
Finished Aug 13 05:35:51 PM PDT 24
Peak memory 218956 kb
Host smart-f537c7d6-6a87-4709-a941-cb26d230f02e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061596024 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.3061596024
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.3887324212
Short name T347
Test name
Test status
Simulation time 70618460098 ps
CPU time 87.64 seconds
Started Aug 13 05:35:28 PM PDT 24
Finished Aug 13 05:36:56 PM PDT 24
Peak memory 205172 kb
Host smart-c0911df0-29da-4182-baae-9a6350eff3d1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887324212 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
rv_dm_jtag_dmi_csr_bit_bash.3887324212
Directory /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.723362085
Short name T344
Test name
Test status
Simulation time 2318202943 ps
CPU time 4.16 seconds
Started Aug 13 05:35:52 PM PDT 24
Finished Aug 13 05:35:57 PM PDT 24
Peak memory 205244 kb
Host smart-7679c426-a34b-4a05-a072-fc6fe05f84f6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723362085 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.723362085
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.1911407439
Short name T438
Test name
Test status
Simulation time 423522834 ps
CPU time 0.84 seconds
Started Aug 13 05:35:49 PM PDT 24
Finished Aug 13 05:35:50 PM PDT 24
Peak memory 204988 kb
Host smart-cf5fb712-ba3e-46bd-8ecd-4eab96793593
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911407439 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.1
911407439
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2289667623
Short name T157
Test name
Test status
Simulation time 557247131 ps
CPU time 6.63 seconds
Started Aug 13 05:35:51 PM PDT 24
Finished Aug 13 05:35:58 PM PDT 24
Peak memory 205176 kb
Host smart-8d5c34aa-69e2-4d63-8bcf-4e80a34c5381
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289667623 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.2289667623
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.3544806712
Short name T114
Test name
Test status
Simulation time 4256828171 ps
CPU time 90.53 seconds
Started Aug 13 05:35:29 PM PDT 24
Finished Aug 13 05:36:59 PM PDT 24
Peak memory 213648 kb
Host smart-b752fce9-f78b-4e32-b3ef-979d1b4fcf07
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544806712 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.3544806712
Directory /workspace/6.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.275133226
Short name T462
Test name
Test status
Simulation time 2884926113 ps
CPU time 8.24 seconds
Started Aug 13 05:35:32 PM PDT 24
Finished Aug 13 05:35:40 PM PDT 24
Peak memory 213640 kb
Host smart-07c50ef6-8270-44e1-a94c-2c377fa8667b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275133226 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.275133226
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.4218858567
Short name T193
Test name
Test status
Simulation time 1925031197 ps
CPU time 10.46 seconds
Started Aug 13 05:35:52 PM PDT 24
Finished Aug 13 05:36:03 PM PDT 24
Peak memory 221712 kb
Host smart-245def35-0aeb-498e-b67f-cfae974261ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218858567 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.4218858567
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.601822262
Short name T450
Test name
Test status
Simulation time 116227007 ps
CPU time 3.58 seconds
Started Aug 13 05:36:08 PM PDT 24
Finished Aug 13 05:36:12 PM PDT 24
Peak memory 219424 kb
Host smart-46ab5774-9a4a-4efc-862b-7e9f0cbe25d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601822262 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.601822262
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.2732156416
Short name T130
Test name
Test status
Simulation time 155420757 ps
CPU time 1.74 seconds
Started Aug 13 05:35:47 PM PDT 24
Finished Aug 13 05:35:49 PM PDT 24
Peak memory 218640 kb
Host smart-cc31c19a-b54d-41ee-a901-2a987d596023
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732156416 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.2732156416
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.2020432626
Short name T478
Test name
Test status
Simulation time 13956763446 ps
CPU time 7.95 seconds
Started Aug 13 05:35:46 PM PDT 24
Finished Aug 13 05:35:54 PM PDT 24
Peak memory 205252 kb
Host smart-a9714540-0422-4d71-84c9-80bffaaa9304
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020432626 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
rv_dm_jtag_dmi_csr_bit_bash.2020432626
Directory /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.2352136069
Short name T466
Test name
Test status
Simulation time 3735624448 ps
CPU time 9.83 seconds
Started Aug 13 05:35:48 PM PDT 24
Finished Aug 13 05:35:58 PM PDT 24
Peak memory 205140 kb
Host smart-fdea1fa8-58d9-4c3e-b442-7cf62c4ba49d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352136069 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.2
352136069
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.3476195928
Short name T400
Test name
Test status
Simulation time 455067287 ps
CPU time 0.87 seconds
Started Aug 13 05:35:50 PM PDT 24
Finished Aug 13 05:35:52 PM PDT 24
Peak memory 204924 kb
Host smart-20b29291-757c-4fba-a66b-2065a34243b0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476195928 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.3
476195928
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.3522378021
Short name T142
Test name
Test status
Simulation time 2254403342 ps
CPU time 9.25 seconds
Started Aug 13 05:35:45 PM PDT 24
Finished Aug 13 05:35:54 PM PDT 24
Peak memory 205332 kb
Host smart-af85f503-b3db-4970-b7b1-40b1a3908994
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522378021 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.3522378021
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.4156872121
Short name T100
Test name
Test status
Simulation time 22377907832 ps
CPU time 60.63 seconds
Started Aug 13 05:35:49 PM PDT 24
Finished Aug 13 05:36:50 PM PDT 24
Peak memory 213700 kb
Host smart-7490f8eb-6d0e-41ee-a0c8-b5aa2d01916b
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156872121 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.4156872121
Directory /workspace/7.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.1752076486
Short name T345
Test name
Test status
Simulation time 203350290 ps
CPU time 4.8 seconds
Started Aug 13 05:35:43 PM PDT 24
Finished Aug 13 05:35:48 PM PDT 24
Peak memory 213464 kb
Host smart-86465f52-8bd5-450d-a5e6-3d52b5b6d432
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752076486 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.1752076486
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.642786065
Short name T454
Test name
Test status
Simulation time 3236552398 ps
CPU time 8.94 seconds
Started Aug 13 05:35:51 PM PDT 24
Finished Aug 13 05:36:00 PM PDT 24
Peak memory 213476 kb
Host smart-b1599149-25ec-4504-a8d6-440426723116
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642786065 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.642786065
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.3241751528
Short name T105
Test name
Test status
Simulation time 152878025 ps
CPU time 2.47 seconds
Started Aug 13 05:35:53 PM PDT 24
Finished Aug 13 05:35:55 PM PDT 24
Peak memory 217608 kb
Host smart-a837dfa2-c30f-4e09-8d8a-d3cb89da1ba0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241751528 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.3241751528
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.1175752316
Short name T417
Test name
Test status
Simulation time 69072853 ps
CPU time 1.64 seconds
Started Aug 13 05:35:43 PM PDT 24
Finished Aug 13 05:35:45 PM PDT 24
Peak memory 213404 kb
Host smart-f0435fe7-262f-46ee-b9d7-f20b8b749c83
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175752316 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.1175752316
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.1684824446
Short name T380
Test name
Test status
Simulation time 12821059262 ps
CPU time 41.03 seconds
Started Aug 13 05:35:47 PM PDT 24
Finished Aug 13 05:36:28 PM PDT 24
Peak memory 205284 kb
Host smart-ad2094c4-5bf1-410e-be13-baac3c1a30cc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684824446 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
rv_dm_jtag_dmi_csr_bit_bash.1684824446
Directory /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.2299132974
Short name T467
Test name
Test status
Simulation time 4325207489 ps
CPU time 2.23 seconds
Started Aug 13 05:35:46 PM PDT 24
Finished Aug 13 05:35:48 PM PDT 24
Peak memory 205176 kb
Host smart-24233597-7b65-4c1d-99a1-8ec2398d42ff
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299132974 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.2
299132974
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.1829659842
Short name T370
Test name
Test status
Simulation time 631791315 ps
CPU time 2.42 seconds
Started Aug 13 05:35:46 PM PDT 24
Finished Aug 13 05:35:48 PM PDT 24
Peak memory 204912 kb
Host smart-fb3ff2c1-7059-4e89-aaea-a795310069b1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829659842 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.1
829659842
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.1034278848
Short name T140
Test name
Test status
Simulation time 1159463089 ps
CPU time 8.19 seconds
Started Aug 13 05:35:48 PM PDT 24
Finished Aug 13 05:35:56 PM PDT 24
Peak memory 205156 kb
Host smart-e4dfe425-eb67-4555-a8bb-fca1843c0344
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034278848 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_
csr_outstanding.1034278848
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.3076118975
Short name T371
Test name
Test status
Simulation time 1307867099 ps
CPU time 3.41 seconds
Started Aug 13 05:35:45 PM PDT 24
Finished Aug 13 05:35:49 PM PDT 24
Peak memory 213576 kb
Host smart-c799d9b7-1474-4f2a-8b80-532c00aff407
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076118975 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.3076118975
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.1476068439
Short name T475
Test name
Test status
Simulation time 1446675310 ps
CPU time 9.03 seconds
Started Aug 13 05:35:50 PM PDT 24
Finished Aug 13 05:35:59 PM PDT 24
Peak memory 213508 kb
Host smart-903f0729-23e5-4b4c-895d-640aeded2f23
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476068439 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.1476068439
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.2985128752
Short name T113
Test name
Test status
Simulation time 158388846 ps
CPU time 3.4 seconds
Started Aug 13 05:35:44 PM PDT 24
Finished Aug 13 05:35:47 PM PDT 24
Peak memory 221308 kb
Host smart-b43d98a5-3f24-4ee6-80e0-13f303f0de5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985128752 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.2985128752
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1688989345
Short name T153
Test name
Test status
Simulation time 137524706 ps
CPU time 1.71 seconds
Started Aug 13 05:35:50 PM PDT 24
Finished Aug 13 05:35:52 PM PDT 24
Peak memory 218924 kb
Host smart-a2dcc65a-dd7b-4963-946d-472d4b1f633b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688989345 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.1688989345
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.2952763606
Short name T440
Test name
Test status
Simulation time 5912774120 ps
CPU time 14.97 seconds
Started Aug 13 05:35:48 PM PDT 24
Finished Aug 13 05:36:03 PM PDT 24
Peak memory 205284 kb
Host smart-8f5e6e36-d7be-4842-a48c-bda4f3e80862
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952763606 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
rv_dm_jtag_dmi_csr_bit_bash.2952763606
Directory /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.4264906238
Short name T355
Test name
Test status
Simulation time 2113368757 ps
CPU time 7.6 seconds
Started Aug 13 05:35:50 PM PDT 24
Finished Aug 13 05:35:58 PM PDT 24
Peak memory 205156 kb
Host smart-bc0327f5-f1c8-4e08-8223-b17c578ab128
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264906238 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.4
264906238
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.2109182606
Short name T457
Test name
Test status
Simulation time 564076311 ps
CPU time 1.66 seconds
Started Aug 13 05:35:49 PM PDT 24
Finished Aug 13 05:35:51 PM PDT 24
Peak memory 204924 kb
Host smart-afec1c7b-a6b1-4596-8fbf-a119c54fd1c5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109182606 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.2
109182606
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.2435385941
Short name T148
Test name
Test status
Simulation time 277289045 ps
CPU time 6.82 seconds
Started Aug 13 05:35:51 PM PDT 24
Finished Aug 13 05:35:58 PM PDT 24
Peak memory 205300 kb
Host smart-15f705ae-c891-49b6-a2a3-c6b308c7e1f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435385941 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_
csr_outstanding.2435385941
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.1822381285
Short name T428
Test name
Test status
Simulation time 238428263 ps
CPU time 2.72 seconds
Started Aug 13 05:35:46 PM PDT 24
Finished Aug 13 05:35:49 PM PDT 24
Peak memory 205320 kb
Host smart-816ca512-5857-4756-94f4-2c56756b02b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822381285 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.1822381285
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.3491856833
Short name T191
Test name
Test status
Simulation time 1921394094 ps
CPU time 19.12 seconds
Started Aug 13 05:35:46 PM PDT 24
Finished Aug 13 05:36:05 PM PDT 24
Peak memory 221656 kb
Host smart-80693d7e-eebb-43cb-82d3-8c0e541c8a42
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491856833 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.3491856833
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.2577150358
Short name T246
Test name
Test status
Simulation time 81773195 ps
CPU time 0.71 seconds
Started Aug 13 05:36:16 PM PDT 24
Finished Aug 13 05:36:17 PM PDT 24
Peak memory 205020 kb
Host smart-971a9bca-aedd-4181-9f05-bc629fdb1274
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577150358 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.2577150358
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.435807249
Short name T171
Test name
Test status
Simulation time 5867390849 ps
CPU time 18.52 seconds
Started Aug 13 05:35:53 PM PDT 24
Finished Aug 13 05:36:12 PM PDT 24
Peak memory 213592 kb
Host smart-f1cb5b2d-a68c-40f2-80ba-7356b3740999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435807249 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.435807249
Directory /workspace/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.3635213492
Short name T259
Test name
Test status
Simulation time 1271033057 ps
CPU time 4.34 seconds
Started Aug 13 05:35:54 PM PDT 24
Finished Aug 13 05:35:58 PM PDT 24
Peak memory 205372 kb
Host smart-74077960-0bde-443c-b7a7-3c61d402eb5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635213492 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.3635213492
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.1103395133
Short name T290
Test name
Test status
Simulation time 184837331 ps
CPU time 0.86 seconds
Started Aug 13 05:35:52 PM PDT 24
Finished Aug 13 05:35:53 PM PDT 24
Peak memory 204728 kb
Host smart-250858da-ea67-49e8-ae9b-392225764ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103395133 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.1103395133
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.320932826
Short name T184
Test name
Test status
Simulation time 245069849 ps
CPU time 1.29 seconds
Started Aug 13 05:35:53 PM PDT 24
Finished Aug 13 05:35:54 PM PDT 24
Peak memory 204928 kb
Host smart-98a03e9f-564b-4e53-9493-560676389ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320932826 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.320932826
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.3971646661
Short name T167
Test name
Test status
Simulation time 235178093 ps
CPU time 0.78 seconds
Started Aug 13 05:36:06 PM PDT 24
Finished Aug 13 05:36:07 PM PDT 24
Peak memory 204920 kb
Host smart-cd666577-6268-4927-8df1-10f3ab602e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971646661 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.3971646661
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_debug_disabled.336722964
Short name T7
Test name
Test status
Simulation time 72003465 ps
CPU time 0.87 seconds
Started Aug 13 05:36:15 PM PDT 24
Finished Aug 13 05:36:16 PM PDT 24
Peak memory 214904 kb
Host smart-5ce48a15-6ec8-432d-a319-ae3a29686048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336722964 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.336722964
Directory /workspace/0.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.1422944588
Short name T177
Test name
Test status
Simulation time 2511044110 ps
CPU time 8.08 seconds
Started Aug 13 05:35:54 PM PDT 24
Finished Aug 13 05:36:02 PM PDT 24
Peak memory 205300 kb
Host smart-7dfa37c9-005f-4015-b18d-eb61a6523b49
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1422944588 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t
l_access.1422944588
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.2480852839
Short name T4
Test name
Test status
Simulation time 241926298 ps
CPU time 1.01 seconds
Started Aug 13 05:35:54 PM PDT 24
Finished Aug 13 05:36:00 PM PDT 24
Peak memory 204776 kb
Host smart-4f92392d-8a28-450a-ae94-da6745c007f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480852839 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.2480852839
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.995485428
Short name T317
Test name
Test status
Simulation time 307097435 ps
CPU time 1.38 seconds
Started Aug 13 05:36:07 PM PDT 24
Finished Aug 13 05:36:09 PM PDT 24
Peak memory 204924 kb
Host smart-03b85b7c-6918-4d3d-9669-c22698ac50ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995485428 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.995485428
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_hartsel_warl.2054132905
Short name T210
Test name
Test status
Simulation time 385372536 ps
CPU time 1.05 seconds
Started Aug 13 05:36:02 PM PDT 24
Finished Aug 13 05:36:03 PM PDT 24
Peak memory 204900 kb
Host smart-5e9ecf03-f668-4164-b265-11c59640cc6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054132905 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hartsel_warl_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hartsel_warl.2054132905
Directory /workspace/0.rv_dm_hartsel_warl/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.3945051328
Short name T224
Test name
Test status
Simulation time 584423912 ps
CPU time 1.04 seconds
Started Aug 13 05:36:03 PM PDT 24
Finished Aug 13 05:36:04 PM PDT 24
Peak memory 204896 kb
Host smart-ffd6df79-3730-41b4-bdff-3ea3f8202e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945051328 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.3945051328
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.1611406251
Short name T282
Test name
Test status
Simulation time 396032211 ps
CPU time 1.82 seconds
Started Aug 13 05:35:56 PM PDT 24
Finished Aug 13 05:35:58 PM PDT 24
Peak memory 204784 kb
Host smart-09970124-9fda-47ae-9d99-e1cc87afb9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611406251 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.1611406251
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.3061914928
Short name T325
Test name
Test status
Simulation time 870985555 ps
CPU time 1.1 seconds
Started Aug 13 05:36:12 PM PDT 24
Finished Aug 13 05:36:14 PM PDT 24
Peak memory 204900 kb
Host smart-b7031883-4624-4ca3-b1be-aa45208d2587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061914928 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.3061914928
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.1962190819
Short name T262
Test name
Test status
Simulation time 122599324 ps
CPU time 0.94 seconds
Started Aug 13 05:35:57 PM PDT 24
Finished Aug 13 05:35:58 PM PDT 24
Peak memory 204840 kb
Host smart-2574ddaa-f848-4ab2-a256-14b1deca872f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962190819 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.1962190819
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.3362209954
Short name T269
Test name
Test status
Simulation time 219105891 ps
CPU time 1.17 seconds
Started Aug 13 05:36:08 PM PDT 24
Finished Aug 13 05:36:09 PM PDT 24
Peak memory 204924 kb
Host smart-4de9184b-be88-41ec-8371-7978b2062c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362209954 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.3362209954
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.1580891019
Short name T169
Test name
Test status
Simulation time 324667094 ps
CPU time 1.5 seconds
Started Aug 13 05:35:54 PM PDT 24
Finished Aug 13 05:35:55 PM PDT 24
Peak memory 204796 kb
Host smart-ff866b1b-c927-4b55-a304-61a9bfb64859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580891019 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.1580891019
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.2828956131
Short name T102
Test name
Test status
Simulation time 171034660 ps
CPU time 0.9 seconds
Started Aug 13 05:35:50 PM PDT 24
Finished Aug 13 05:35:51 PM PDT 24
Peak memory 213036 kb
Host smart-d6b24dae-a92e-4983-b716-3ca6a8bbb7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828956131 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.2828956131
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.2196856121
Short name T176
Test name
Test status
Simulation time 307806932 ps
CPU time 1.18 seconds
Started Aug 13 05:36:09 PM PDT 24
Finished Aug 13 05:36:11 PM PDT 24
Peak memory 204896 kb
Host smart-88f843e2-0653-4037-b392-41532dccc2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196856121 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.2196856121
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.2404633816
Short name T45
Test name
Test status
Simulation time 50793814 ps
CPU time 0.9 seconds
Started Aug 13 05:35:56 PM PDT 24
Finished Aug 13 05:35:57 PM PDT 24
Peak memory 213136 kb
Host smart-35aae944-6030-4318-9cde-17997d5a59f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404633816 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.2404633816
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.3301688890
Short name T312
Test name
Test status
Simulation time 5203238974 ps
CPU time 4.61 seconds
Started Aug 13 05:35:54 PM PDT 24
Finished Aug 13 05:35:59 PM PDT 24
Peak memory 205428 kb
Host smart-7b35030c-8725-42b3-a597-a1af08954232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301688890 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.3301688890
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.1616547580
Short name T72
Test name
Test status
Simulation time 716933677 ps
CPU time 1.08 seconds
Started Aug 13 05:35:56 PM PDT 24
Finished Aug 13 05:35:57 PM PDT 24
Peak memory 228368 kb
Host smart-a74df08e-36e8-472d-8ac1-f568660b0b3f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616547580 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.1616547580
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.1399599236
Short name T234
Test name
Test status
Simulation time 797413481 ps
CPU time 3.09 seconds
Started Aug 13 05:35:54 PM PDT 24
Finished Aug 13 05:35:57 PM PDT 24
Peak memory 204888 kb
Host smart-1051edd5-7621-411c-b47e-3a083a12ba3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399599236 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.1399599236
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/0.rv_dm_sparse_lc_gate_fsm.2300984663
Short name T66
Test name
Test status
Simulation time 66952041 ps
CPU time 0.9 seconds
Started Aug 13 05:35:55 PM PDT 24
Finished Aug 13 05:35:56 PM PDT 24
Peak memory 213304 kb
Host smart-c1de8b97-9100-4f35-8551-6117a6ad4fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300984663 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sparse_lc_gate_fsm.2300984663
Directory /workspace/0.rv_dm_sparse_lc_gate_fsm/latest

Test location /workspace/coverage/default/0.rv_dm_stress_all.3910550992
Short name T270
Test name
Test status
Simulation time 6453840381 ps
CPU time 11.18 seconds
Started Aug 13 05:35:51 PM PDT 24
Finished Aug 13 05:36:03 PM PDT 24
Peak memory 213340 kb
Host smart-04d4c5c0-532c-4345-a859-6e29b15a8fac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910550992 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.3910550992
Directory /workspace/0.rv_dm_stress_all/latest

Test location /workspace/coverage/default/1.rv_dm_abstractcmd_status.4177425280
Short name T57
Test name
Test status
Simulation time 214297792 ps
CPU time 1 seconds
Started Aug 13 05:35:54 PM PDT 24
Finished Aug 13 05:35:56 PM PDT 24
Peak memory 204900 kb
Host smart-80ad07e0-f65f-46b6-8ede-d8edcce80ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177425280 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.4177425280
Directory /workspace/1.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.904988937
Short name T321
Test name
Test status
Simulation time 159872960 ps
CPU time 1.13 seconds
Started Aug 13 05:36:15 PM PDT 24
Finished Aug 13 05:36:16 PM PDT 24
Peak memory 205044 kb
Host smart-2b5492e8-73f3-4ffa-808f-162731aa792a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904988937 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.904988937
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.2315254279
Short name T221
Test name
Test status
Simulation time 6702888118 ps
CPU time 13.07 seconds
Started Aug 13 05:35:55 PM PDT 24
Finished Aug 13 05:36:08 PM PDT 24
Peak memory 205484 kb
Host smart-2bd085d9-d46a-4924-a46d-443ea4414c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315254279 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.2315254279
Directory /workspace/1.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.2436977386
Short name T213
Test name
Test status
Simulation time 3213489631 ps
CPU time 6.13 seconds
Started Aug 13 05:36:10 PM PDT 24
Finished Aug 13 05:36:17 PM PDT 24
Peak memory 205444 kb
Host smart-369e326b-31d3-47ca-b995-f36d47021eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436977386 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.2436977386
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_buffered_enable.749684265
Short name T13
Test name
Test status
Simulation time 122799736 ps
CPU time 0.9 seconds
Started Aug 13 05:35:55 PM PDT 24
Finished Aug 13 05:35:56 PM PDT 24
Peak memory 225532 kb
Host smart-05307e55-cad0-4778-a24a-9219ca5d21d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749684265 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_buffered_enable.749684265
Directory /workspace/1.rv_dm_buffered_enable/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.4080840951
Short name T25
Test name
Test status
Simulation time 196373390 ps
CPU time 1.26 seconds
Started Aug 13 05:35:55 PM PDT 24
Finished Aug 13 05:35:56 PM PDT 24
Peak memory 204912 kb
Host smart-b9957f15-0d86-49f2-9a35-99a03e15a78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080840951 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.4080840951
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.1609857618
Short name T19
Test name
Test status
Simulation time 527537623 ps
CPU time 1.52 seconds
Started Aug 13 05:35:55 PM PDT 24
Finished Aug 13 05:35:57 PM PDT 24
Peak memory 204904 kb
Host smart-2a2ed6d9-3cb6-46d1-8299-65dbcc2ff79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609857618 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.1609857618
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.1325094432
Short name T43
Test name
Test status
Simulation time 567061142 ps
CPU time 1.02 seconds
Started Aug 13 05:35:55 PM PDT 24
Finished Aug 13 05:35:56 PM PDT 24
Peak memory 204872 kb
Host smart-8a6cd0e9-c9cd-41ec-b84e-8f83ad41b3c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325094432 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.1325094432
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.1323015946
Short name T291
Test name
Test status
Simulation time 156242638 ps
CPU time 1.06 seconds
Started Aug 13 05:36:08 PM PDT 24
Finished Aug 13 05:36:09 PM PDT 24
Peak memory 204852 kb
Host smart-0ba58a1f-07ca-430f-ae84-a56abd62619b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323015946 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.1323015946
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_debug_disabled.889846610
Short name T95
Test name
Test status
Simulation time 110003047 ps
CPU time 1.01 seconds
Started Aug 13 05:36:04 PM PDT 24
Finished Aug 13 05:36:05 PM PDT 24
Peak memory 214968 kb
Host smart-88d5ec9b-a9ab-40fe-845e-415d15d90ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889846610 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.889846610
Directory /workspace/1.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.3125167799
Short name T265
Test name
Test status
Simulation time 3113711991 ps
CPU time 5.86 seconds
Started Aug 13 05:35:56 PM PDT 24
Finished Aug 13 05:36:02 PM PDT 24
Peak memory 205468 kb
Host smart-c89b1f9e-9cdb-4863-b126-676e5071a537
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3125167799 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t
l_access.3125167799
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.3252185842
Short name T40
Test name
Test status
Simulation time 527436246 ps
CPU time 2.1 seconds
Started Aug 13 05:35:56 PM PDT 24
Finished Aug 13 05:35:58 PM PDT 24
Peak memory 204828 kb
Host smart-39fb0d50-af9f-462f-94e1-0648352aeab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252185842 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.3252185842
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.210221074
Short name T2
Test name
Test status
Simulation time 138233023 ps
CPU time 1.05 seconds
Started Aug 13 05:36:07 PM PDT 24
Finished Aug 13 05:36:09 PM PDT 24
Peak memory 204904 kb
Host smart-e9cc160c-06d1-4853-98fd-087481acb36c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210221074 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.210221074
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.3693665363
Short name T166
Test name
Test status
Simulation time 261467709 ps
CPU time 1.37 seconds
Started Aug 13 05:36:09 PM PDT 24
Finished Aug 13 05:36:11 PM PDT 24
Peak memory 204904 kb
Host smart-10d0b271-84ad-4d2e-bff5-df5bb6765129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693665363 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.3693665363
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.381541692
Short name T214
Test name
Test status
Simulation time 1956334651 ps
CPU time 3.23 seconds
Started Aug 13 05:36:09 PM PDT 24
Finished Aug 13 05:36:13 PM PDT 24
Peak memory 204844 kb
Host smart-7637d9a2-c66f-4d3c-b92c-eba1f851077a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381541692 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.381541692
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.402329486
Short name T74
Test name
Test status
Simulation time 817721357 ps
CPU time 1.71 seconds
Started Aug 13 05:35:56 PM PDT 24
Finished Aug 13 05:35:57 PM PDT 24
Peak memory 204892 kb
Host smart-9fda451c-b0a2-430d-b7cd-fe8ac9aeaee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402329486 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.402329486
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.688570786
Short name T306
Test name
Test status
Simulation time 145098387 ps
CPU time 1.06 seconds
Started Aug 13 05:36:03 PM PDT 24
Finished Aug 13 05:36:05 PM PDT 24
Peak memory 204908 kb
Host smart-5ea77694-bd63-412e-bcc6-677bf0ebed95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688570786 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.688570786
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.3733686674
Short name T300
Test name
Test status
Simulation time 156645413 ps
CPU time 1.08 seconds
Started Aug 13 05:36:08 PM PDT 24
Finished Aug 13 05:36:09 PM PDT 24
Peak memory 204900 kb
Host smart-1a910276-f4a5-4e68-8b88-718d75899af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733686674 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.3733686674
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.3368971736
Short name T298
Test name
Test status
Simulation time 467089378 ps
CPU time 1.4 seconds
Started Aug 13 05:35:58 PM PDT 24
Finished Aug 13 05:35:59 PM PDT 24
Peak memory 204868 kb
Host smart-6b066641-830c-408f-bb9d-5d50ff35ef6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368971736 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.3368971736
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.2769249128
Short name T47
Test name
Test status
Simulation time 440463341 ps
CPU time 1.19 seconds
Started Aug 13 05:35:56 PM PDT 24
Finished Aug 13 05:35:57 PM PDT 24
Peak memory 204884 kb
Host smart-e183f816-70bd-4c7e-a157-fb5ac7dff9ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769249128 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.2769249128
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_sba_debug_disabled.1629027835
Short name T225
Test name
Test status
Simulation time 998443685 ps
CPU time 2.25 seconds
Started Aug 13 05:35:58 PM PDT 24
Finished Aug 13 05:36:00 PM PDT 24
Peak memory 204924 kb
Host smart-a49e47fe-f5a9-4c6a-be5e-6e4c86548655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629027835 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.1629027835
Directory /workspace/1.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.78174409
Short name T303
Test name
Test status
Simulation time 1064924916 ps
CPU time 1.78 seconds
Started Aug 13 05:36:01 PM PDT 24
Finished Aug 13 05:36:03 PM PDT 24
Peak memory 205220 kb
Host smart-7b7463e5-a10a-4d19-a30a-c33e15382019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78174409 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.78174409
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.2646517052
Short name T70
Test name
Test status
Simulation time 1285400334 ps
CPU time 4.55 seconds
Started Aug 13 05:36:05 PM PDT 24
Finished Aug 13 05:36:09 PM PDT 24
Peak memory 229296 kb
Host smart-0590c2c2-d9c1-4f5a-b17c-dd02468b6dcd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646517052 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.2646517052
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.979196722
Short name T178
Test name
Test status
Simulation time 2305453787 ps
CPU time 2.13 seconds
Started Aug 13 05:36:16 PM PDT 24
Finished Aug 13 05:36:18 PM PDT 24
Peak memory 204956 kb
Host smart-57178217-8866-4e43-a08b-219da95b64f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979196722 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.979196722
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/1.rv_dm_sparse_lc_gate_fsm.1476573642
Short name T67
Test name
Test status
Simulation time 133254823 ps
CPU time 1.05 seconds
Started Aug 13 05:36:01 PM PDT 24
Finished Aug 13 05:36:03 PM PDT 24
Peak memory 213188 kb
Host smart-9299697e-92d7-4060-b0ce-f302f3f859e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476573642 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sparse_lc_gate_fsm.1476573642
Directory /workspace/1.rv_dm_sparse_lc_gate_fsm/latest

Test location /workspace/coverage/default/1.rv_dm_stress_all.1352543212
Short name T172
Test name
Test status
Simulation time 1821419608 ps
CPU time 5.41 seconds
Started Aug 13 05:36:09 PM PDT 24
Finished Aug 13 05:36:14 PM PDT 24
Peak memory 213312 kb
Host smart-e443a556-e753-4237-a73e-a47e659c438b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352543212 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.1352543212
Directory /workspace/1.rv_dm_stress_all/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.3027470224
Short name T34
Test name
Test status
Simulation time 55757833 ps
CPU time 0.72 seconds
Started Aug 13 05:36:14 PM PDT 24
Finished Aug 13 05:36:15 PM PDT 24
Peak memory 205032 kb
Host smart-3ed6ea5b-760b-4143-9656-03bd13bfab55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027470224 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.3027470224
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.1413588130
Short name T31
Test name
Test status
Simulation time 1778456512 ps
CPU time 3.09 seconds
Started Aug 13 05:36:08 PM PDT 24
Finished Aug 13 05:36:12 PM PDT 24
Peak memory 205316 kb
Host smart-6b331357-7fc6-4914-b352-7eab4e6a4aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413588130 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.1413588130
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.1630104590
Short name T258
Test name
Test status
Simulation time 4196888161 ps
CPU time 11.06 seconds
Started Aug 13 05:36:12 PM PDT 24
Finished Aug 13 05:36:24 PM PDT 24
Peak memory 213620 kb
Host smart-890e2d7f-342f-44a1-9ef9-c8c5d5449e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630104590 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.1630104590
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.2749824394
Short name T315
Test name
Test status
Simulation time 5795455805 ps
CPU time 5.08 seconds
Started Aug 13 05:36:06 PM PDT 24
Finished Aug 13 05:36:12 PM PDT 24
Peak memory 213640 kb
Host smart-0aaca521-a5e9-4a2d-bc4f-926040af6b80
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2749824394 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_
tl_access.2749824394
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.1476097181
Short name T264
Test name
Test status
Simulation time 3356116313 ps
CPU time 3.67 seconds
Started Aug 13 05:36:08 PM PDT 24
Finished Aug 13 05:36:12 PM PDT 24
Peak memory 205472 kb
Host smart-f5330e29-cd55-4534-9b46-3b649a30a119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476097181 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.1476097181
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_stress_all.1272897263
Short name T238
Test name
Test status
Simulation time 824825976 ps
CPU time 1.93 seconds
Started Aug 13 05:36:08 PM PDT 24
Finished Aug 13 05:36:10 PM PDT 24
Peak memory 205064 kb
Host smart-e0c82a39-924a-483f-8a00-b8bf5b5e2d35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272897263 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.1272897263
Directory /workspace/10.rv_dm_stress_all/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.423817757
Short name T227
Test name
Test status
Simulation time 73608281 ps
CPU time 0.97 seconds
Started Aug 13 05:36:05 PM PDT 24
Finished Aug 13 05:36:06 PM PDT 24
Peak memory 204980 kb
Host smart-66f9f7a0-048f-46fb-b6a2-e124f41e99eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423817757 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.423817757
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.2232031684
Short name T331
Test name
Test status
Simulation time 12555061796 ps
CPU time 17.71 seconds
Started Aug 13 05:36:10 PM PDT 24
Finished Aug 13 05:36:28 PM PDT 24
Peak memory 213600 kb
Host smart-5fb53bb1-4e9c-4f3b-be4a-2a4e1a41f0af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232031684 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.2232031684
Directory /workspace/11.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.1397436432
Short name T228
Test name
Test status
Simulation time 5601986463 ps
CPU time 18.36 seconds
Started Aug 13 05:36:06 PM PDT 24
Finished Aug 13 05:36:25 PM PDT 24
Peak memory 213600 kb
Host smart-b8e23a89-8153-424a-a674-07d2eaa6e2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397436432 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.1397436432
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.2350234224
Short name T243
Test name
Test status
Simulation time 2034947958 ps
CPU time 2.75 seconds
Started Aug 13 05:36:21 PM PDT 24
Finished Aug 13 05:36:24 PM PDT 24
Peak memory 204580 kb
Host smart-09cab80f-ee38-485a-810d-430d651dcdbc
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2350234224 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_
tl_access.2350234224
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.1785337287
Short name T281
Test name
Test status
Simulation time 29879120 ps
CPU time 0.77 seconds
Started Aug 13 05:36:15 PM PDT 24
Finished Aug 13 05:36:16 PM PDT 24
Peak memory 205080 kb
Host smart-8f8f98b7-5ceb-4271-80ca-c96595851041
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785337287 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.1785337287
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.2680909351
Short name T212
Test name
Test status
Simulation time 7079074359 ps
CPU time 22.92 seconds
Started Aug 13 05:36:15 PM PDT 24
Finished Aug 13 05:36:38 PM PDT 24
Peak memory 214300 kb
Host smart-ba54ad92-9caa-428f-a2f3-abd92618c733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680909351 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.2680909351
Directory /workspace/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.972113353
Short name T327
Test name
Test status
Simulation time 2886521008 ps
CPU time 8.3 seconds
Started Aug 13 05:36:34 PM PDT 24
Finished Aug 13 05:36:43 PM PDT 24
Peak memory 205492 kb
Host smart-695d21e7-a94b-42bf-9bce-1182a5a1e244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972113353 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.972113353
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.4178223408
Short name T76
Test name
Test status
Simulation time 7864538493 ps
CPU time 22.78 seconds
Started Aug 13 05:36:16 PM PDT 24
Finished Aug 13 05:36:39 PM PDT 24
Peak memory 213628 kb
Host smart-6148a75d-7cd1-4ab0-959b-851389b775a3
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4178223408 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_
tl_access.4178223408
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.2762564398
Short name T79
Test name
Test status
Simulation time 2556783516 ps
CPU time 4.6 seconds
Started Aug 13 05:36:13 PM PDT 24
Finished Aug 13 05:36:18 PM PDT 24
Peak memory 205464 kb
Host smart-5ecffcb8-a43e-431f-b80b-e0ecc8d75c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762564398 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.2762564398
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.2581798531
Short name T124
Test name
Test status
Simulation time 58009924 ps
CPU time 0.84 seconds
Started Aug 13 05:36:24 PM PDT 24
Finished Aug 13 05:36:25 PM PDT 24
Peak memory 204940 kb
Host smart-783579af-c280-429b-b6be-0e32972bf8b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581798531 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.2581798531
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.1368975511
Short name T249
Test name
Test status
Simulation time 19987180187 ps
CPU time 34.05 seconds
Started Aug 13 05:36:15 PM PDT 24
Finished Aug 13 05:36:49 PM PDT 24
Peak memory 213508 kb
Host smart-5d5569a0-92fd-4e22-9e2b-d9f6fb0010b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368975511 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.1368975511
Directory /workspace/13.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.3938876784
Short name T39
Test name
Test status
Simulation time 602428304 ps
CPU time 2.52 seconds
Started Aug 13 05:36:23 PM PDT 24
Finished Aug 13 05:36:26 PM PDT 24
Peak memory 205276 kb
Host smart-148f8b19-c662-4e9e-9de5-7e5ae9fd2b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938876784 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.3938876784
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.1223809774
Short name T218
Test name
Test status
Simulation time 6103743288 ps
CPU time 5.28 seconds
Started Aug 13 05:36:16 PM PDT 24
Finished Aug 13 05:36:22 PM PDT 24
Peak memory 205368 kb
Host smart-a575fab5-2716-4d0a-b187-6dbd6a23d187
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1223809774 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_
tl_access.1223809774
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.491444311
Short name T311
Test name
Test status
Simulation time 2741129811 ps
CPU time 8.8 seconds
Started Aug 13 05:36:26 PM PDT 24
Finished Aug 13 05:36:35 PM PDT 24
Peak memory 213496 kb
Host smart-db70636f-233a-48a4-91f6-4ace3d9ccb66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491444311 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.491444311
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.3687935140
Short name T328
Test name
Test status
Simulation time 153408247 ps
CPU time 0.75 seconds
Started Aug 13 05:36:29 PM PDT 24
Finished Aug 13 05:36:30 PM PDT 24
Peak memory 204972 kb
Host smart-fe8796a8-5845-45c1-a382-dc64c4e71eda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687935140 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.3687935140
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.3615696102
Short name T284
Test name
Test status
Simulation time 13181778072 ps
CPU time 3.61 seconds
Started Aug 13 05:36:13 PM PDT 24
Finished Aug 13 05:36:16 PM PDT 24
Peak memory 213504 kb
Host smart-06d53a1b-bc78-4bdb-a8a3-1e8a6aa68ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615696102 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.3615696102
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.628759974
Short name T316
Test name
Test status
Simulation time 2829754225 ps
CPU time 5.2 seconds
Started Aug 13 05:36:24 PM PDT 24
Finished Aug 13 05:36:29 PM PDT 24
Peak memory 205456 kb
Host smart-6c72e31f-87b2-4897-8a86-ed28b3b0499c
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=628759974 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_t
l_access.628759974
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.2893582699
Short name T231
Test name
Test status
Simulation time 6289976262 ps
CPU time 11.28 seconds
Started Aug 13 05:36:33 PM PDT 24
Finished Aug 13 05:36:44 PM PDT 24
Peak memory 205288 kb
Host smart-9846ff02-88c4-479b-88fe-d9ba8d698e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893582699 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.2893582699
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_stress_all.3161260532
Short name T295
Test name
Test status
Simulation time 9879432143 ps
CPU time 29.52 seconds
Started Aug 13 05:36:15 PM PDT 24
Finished Aug 13 05:36:44 PM PDT 24
Peak memory 205200 kb
Host smart-d9c3ab88-242e-407b-9dfc-93983543b3b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161260532 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.3161260532
Directory /workspace/14.rv_dm_stress_all/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.956078008
Short name T307
Test name
Test status
Simulation time 46461026 ps
CPU time 0.73 seconds
Started Aug 13 05:36:22 PM PDT 24
Finished Aug 13 05:36:23 PM PDT 24
Peak memory 205056 kb
Host smart-aad84b72-1f7f-48b7-8f43-34ee0d1a2261
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956078008 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.956078008
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.3267867865
Short name T308
Test name
Test status
Simulation time 7503482646 ps
CPU time 3.55 seconds
Started Aug 13 05:36:20 PM PDT 24
Finished Aug 13 05:36:24 PM PDT 24
Peak memory 213576 kb
Host smart-6cc00b10-359d-41e1-9f8f-cc2bd89c55de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267867865 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.3267867865
Directory /workspace/15.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.1336253909
Short name T90
Test name
Test status
Simulation time 4493233184 ps
CPU time 4.06 seconds
Started Aug 13 05:36:26 PM PDT 24
Finished Aug 13 05:36:30 PM PDT 24
Peak memory 213556 kb
Host smart-f1c414f3-00f5-45af-9471-cb21b212d73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336253909 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.1336253909
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.4216810359
Short name T279
Test name
Test status
Simulation time 732654204 ps
CPU time 1.89 seconds
Started Aug 13 05:36:17 PM PDT 24
Finished Aug 13 05:36:19 PM PDT 24
Peak memory 205260 kb
Host smart-c96af441-a217-4264-9759-a66970661c17
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4216810359 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_
tl_access.4216810359
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.1908294824
Short name T91
Test name
Test status
Simulation time 939146596 ps
CPU time 1.59 seconds
Started Aug 13 05:36:14 PM PDT 24
Finished Aug 13 05:36:16 PM PDT 24
Peak memory 205400 kb
Host smart-9c91f524-9f13-4a43-ab30-12b124ed7b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908294824 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.1908294824
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_stress_all.2194720711
Short name T27
Test name
Test status
Simulation time 2747929269 ps
CPU time 3.05 seconds
Started Aug 13 05:36:22 PM PDT 24
Finished Aug 13 05:36:26 PM PDT 24
Peak memory 213384 kb
Host smart-326307ab-65e9-429d-827d-51692dbd3112
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194720711 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.2194720711
Directory /workspace/15.rv_dm_stress_all/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.3186838073
Short name T77
Test name
Test status
Simulation time 40626659 ps
CPU time 0.72 seconds
Started Aug 13 05:36:25 PM PDT 24
Finished Aug 13 05:36:26 PM PDT 24
Peak memory 204880 kb
Host smart-8ba748af-5d18-4738-a9d6-8ca57a0b7aea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186838073 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.3186838073
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.1343166319
Short name T219
Test name
Test status
Simulation time 4395406767 ps
CPU time 3.88 seconds
Started Aug 13 05:36:30 PM PDT 24
Finished Aug 13 05:36:34 PM PDT 24
Peak memory 213672 kb
Host smart-ade4cac8-9b53-4949-8122-20128fbbeb9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343166319 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.1343166319
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.3685195725
Short name T196
Test name
Test status
Simulation time 1156214346 ps
CPU time 4 seconds
Started Aug 13 05:36:33 PM PDT 24
Finished Aug 13 05:36:37 PM PDT 24
Peak memory 205312 kb
Host smart-5eae5acf-d4d0-4472-8344-7c4f74780b93
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3685195725 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_
tl_access.3685195725
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.1593434392
Short name T305
Test name
Test status
Simulation time 1746807788 ps
CPU time 6.66 seconds
Started Aug 13 05:36:13 PM PDT 24
Finished Aug 13 05:36:20 PM PDT 24
Peak memory 205628 kb
Host smart-b8658b01-72e3-49c0-89b8-88c36bcad626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593434392 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.1593434392
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_stress_all.2727789073
Short name T10
Test name
Test status
Simulation time 1231453578 ps
CPU time 2.13 seconds
Started Aug 13 05:36:32 PM PDT 24
Finished Aug 13 05:36:34 PM PDT 24
Peak memory 205068 kb
Host smart-a1ead318-d056-40d2-adf5-3e52042d0404
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727789073 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.2727789073
Directory /workspace/16.rv_dm_stress_all/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.1542388843
Short name T304
Test name
Test status
Simulation time 140371805 ps
CPU time 0.77 seconds
Started Aug 13 05:36:20 PM PDT 24
Finished Aug 13 05:36:21 PM PDT 24
Peak memory 205280 kb
Host smart-e201f97c-bb26-4dac-a2b8-c74ff4cac5c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542388843 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.1542388843
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.4021804882
Short name T226
Test name
Test status
Simulation time 2196734216 ps
CPU time 3.8 seconds
Started Aug 13 05:36:25 PM PDT 24
Finished Aug 13 05:36:29 PM PDT 24
Peak memory 205612 kb
Host smart-1dcb2e17-5240-4bcf-859b-330a05649b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021804882 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.4021804882
Directory /workspace/17.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.3015489177
Short name T101
Test name
Test status
Simulation time 1197335543 ps
CPU time 3.65 seconds
Started Aug 13 05:36:22 PM PDT 24
Finished Aug 13 05:36:26 PM PDT 24
Peak memory 213560 kb
Host smart-c3c30ba6-22b4-401f-ab42-33d825f260cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015489177 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.3015489177
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.420709514
Short name T179
Test name
Test status
Simulation time 995650536 ps
CPU time 2.51 seconds
Started Aug 13 05:36:21 PM PDT 24
Finished Aug 13 05:36:24 PM PDT 24
Peak memory 205312 kb
Host smart-b9824b4b-ab1a-4f90-b706-cec3e8fd02f8
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=420709514 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_t
l_access.420709514
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.1856401515
Short name T297
Test name
Test status
Simulation time 8007284258 ps
CPU time 23.47 seconds
Started Aug 13 05:36:21 PM PDT 24
Finished Aug 13 05:36:45 PM PDT 24
Peak memory 205424 kb
Host smart-523f5bea-83f1-4bac-896f-3f1f0d383af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856401515 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.1856401515
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_stress_all.4252024277
Short name T71
Test name
Test status
Simulation time 2270250975 ps
CPU time 4.03 seconds
Started Aug 13 05:36:32 PM PDT 24
Finished Aug 13 05:36:36 PM PDT 24
Peak memory 205232 kb
Host smart-4220ea9e-f05a-490f-bf3d-8b3792969f21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252024277 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.4252024277
Directory /workspace/17.rv_dm_stress_all/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.2719822376
Short name T208
Test name
Test status
Simulation time 72402108 ps
CPU time 0.74 seconds
Started Aug 13 05:36:35 PM PDT 24
Finished Aug 13 05:36:36 PM PDT 24
Peak memory 205048 kb
Host smart-f03fca02-04e3-4617-ba6b-0cb63620b1bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719822376 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.2719822376
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.1817408210
Short name T28
Test name
Test status
Simulation time 2358144664 ps
CPU time 7.57 seconds
Started Aug 13 05:36:25 PM PDT 24
Finished Aug 13 05:36:33 PM PDT 24
Peak memory 213628 kb
Host smart-37044c8a-3f56-471d-bde1-59babe46e485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817408210 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.1817408210
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.1294904517
Short name T301
Test name
Test status
Simulation time 1228314629 ps
CPU time 1.78 seconds
Started Aug 13 05:36:27 PM PDT 24
Finished Aug 13 05:36:29 PM PDT 24
Peak memory 205404 kb
Host smart-7ad45bb9-c047-44a9-99ed-bf85001fbb8a
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1294904517 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_
tl_access.1294904517
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.3501882913
Short name T267
Test name
Test status
Simulation time 2473704299 ps
CPU time 2.2 seconds
Started Aug 13 05:36:31 PM PDT 24
Finished Aug 13 05:36:33 PM PDT 24
Peak memory 205368 kb
Host smart-149de3c4-e2e7-422d-9ad4-4229201e28cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501882913 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.3501882913
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_stress_all.1670548428
Short name T38
Test name
Test status
Simulation time 703263082 ps
CPU time 1.51 seconds
Started Aug 13 05:36:26 PM PDT 24
Finished Aug 13 05:36:28 PM PDT 24
Peak memory 204788 kb
Host smart-71db2973-7d19-4a42-8b4a-d1402c877b8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670548428 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.1670548428
Directory /workspace/18.rv_dm_stress_all/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.1187823797
Short name T299
Test name
Test status
Simulation time 45063437 ps
CPU time 0.76 seconds
Started Aug 13 05:36:20 PM PDT 24
Finished Aug 13 05:36:21 PM PDT 24
Peak memory 204980 kb
Host smart-bef55da6-0bd0-4fb5-9e49-741d1e65e46a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187823797 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.1187823797
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.2850614486
Short name T260
Test name
Test status
Simulation time 3656098813 ps
CPU time 9.28 seconds
Started Aug 13 05:36:42 PM PDT 24
Finished Aug 13 05:36:51 PM PDT 24
Peak memory 213664 kb
Host smart-a2cbb518-37f1-4ab7-95d4-f220b411f8ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850614486 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.2850614486
Directory /workspace/19.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.1934225340
Short name T198
Test name
Test status
Simulation time 3001727813 ps
CPU time 2.98 seconds
Started Aug 13 05:36:30 PM PDT 24
Finished Aug 13 05:36:33 PM PDT 24
Peak memory 213692 kb
Host smart-4b18b8ce-529c-4e1c-8ca6-f9cbef944f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934225340 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.1934225340
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.3239699779
Short name T319
Test name
Test status
Simulation time 2032262006 ps
CPU time 6.72 seconds
Started Aug 13 05:36:42 PM PDT 24
Finished Aug 13 05:36:49 PM PDT 24
Peak memory 213624 kb
Host smart-b48d892e-0784-4ef9-bc22-2e813c4621ae
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3239699779 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_
tl_access.3239699779
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.65958525
Short name T199
Test name
Test status
Simulation time 2975238438 ps
CPU time 4.97 seconds
Started Aug 13 05:36:27 PM PDT 24
Finished Aug 13 05:36:32 PM PDT 24
Peak memory 205416 kb
Host smart-4ab4fcdd-ba3c-4473-a40c-7e2e9da1e54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65958525 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.65958525
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_stress_all.3639396243
Short name T6
Test name
Test status
Simulation time 5320954088 ps
CPU time 14.28 seconds
Started Aug 13 05:36:22 PM PDT 24
Finished Aug 13 05:36:36 PM PDT 24
Peak memory 205100 kb
Host smart-2d2edcad-41b5-48c9-814a-7685e3683c2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639396243 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.3639396243
Directory /workspace/19.rv_dm_stress_all/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.1930553978
Short name T201
Test name
Test status
Simulation time 87258672 ps
CPU time 0.9 seconds
Started Aug 13 05:36:03 PM PDT 24
Finished Aug 13 05:36:04 PM PDT 24
Peak memory 204940 kb
Host smart-b24f049d-42f3-498f-990a-3f49ae2cbeea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930553978 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.1930553978
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.4193189014
Short name T272
Test name
Test status
Simulation time 3241354821 ps
CPU time 8.53 seconds
Started Aug 13 05:36:00 PM PDT 24
Finished Aug 13 05:36:09 PM PDT 24
Peak memory 213676 kb
Host smart-7b06f8bb-10b3-4940-a399-86df32581b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193189014 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.4193189014
Directory /workspace/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_buffered_enable.566405206
Short name T98
Test name
Test status
Simulation time 285893595 ps
CPU time 1.6 seconds
Started Aug 13 05:36:02 PM PDT 24
Finished Aug 13 05:36:03 PM PDT 24
Peak memory 225768 kb
Host smart-a55f9f33-248f-409d-8614-a73bb1af0510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566405206 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_buffered_enable.566405206
Directory /workspace/2.rv_dm_buffered_enable/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.1273974954
Short name T275
Test name
Test status
Simulation time 983600679 ps
CPU time 2.44 seconds
Started Aug 13 05:36:17 PM PDT 24
Finished Aug 13 05:36:19 PM PDT 24
Peak memory 205424 kb
Host smart-3ae053d1-6473-439d-8569-45d60372fdbc
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1273974954 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t
l_access.1273974954
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_halt_resume_whereto.4030682646
Short name T52
Test name
Test status
Simulation time 278284245 ps
CPU time 0.84 seconds
Started Aug 13 05:36:02 PM PDT 24
Finished Aug 13 05:36:03 PM PDT 24
Peak memory 204900 kb
Host smart-76ee6501-00a3-4904-9b9c-d3e4b02e5c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030682646 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_halt_resume_whereto.4030682646
Directory /workspace/2.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.3403557042
Short name T296
Test name
Test status
Simulation time 246768087 ps
CPU time 1.3 seconds
Started Aug 13 05:36:01 PM PDT 24
Finished Aug 13 05:36:02 PM PDT 24
Peak memory 204876 kb
Host smart-f8c48215-549e-4c54-93d2-1b1b2c58e5b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403557042 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.3403557042
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.3555306848
Short name T263
Test name
Test status
Simulation time 2549330161 ps
CPU time 2.75 seconds
Started Aug 13 05:36:09 PM PDT 24
Finished Aug 13 05:36:12 PM PDT 24
Peak memory 205404 kb
Host smart-2878e0f0-9b76-4bd5-b0a0-3f96228b13d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555306848 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.3555306848
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.3741965582
Short name T73
Test name
Test status
Simulation time 495101822 ps
CPU time 1.14 seconds
Started Aug 13 05:36:06 PM PDT 24
Finished Aug 13 05:36:07 PM PDT 24
Peak memory 229400 kb
Host smart-6d278908-77cc-471b-9903-4ecb2cbc8396
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741965582 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.3741965582
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/2.rv_dm_stress_all.2779988814
Short name T241
Test name
Test status
Simulation time 2248343496 ps
CPU time 2.08 seconds
Started Aug 13 05:36:16 PM PDT 24
Finished Aug 13 05:36:18 PM PDT 24
Peak memory 205228 kb
Host smart-63510039-cafe-4559-beab-c9825a4658a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779988814 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.2779988814
Directory /workspace/2.rv_dm_stress_all/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.4239785410
Short name T318
Test name
Test status
Simulation time 97567129 ps
CPU time 0.79 seconds
Started Aug 13 05:36:21 PM PDT 24
Finished Aug 13 05:36:22 PM PDT 24
Peak memory 205032 kb
Host smart-e4236fc1-bff9-4910-b5ad-49086be0ce1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239785410 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.4239785410
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/20.rv_dm_stress_all.2750404378
Short name T59
Test name
Test status
Simulation time 4196815346 ps
CPU time 1.75 seconds
Started Aug 13 05:36:30 PM PDT 24
Finished Aug 13 05:36:32 PM PDT 24
Peak memory 213360 kb
Host smart-6d22f03b-a913-4ad5-a11f-a043877af72d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750404378 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.2750404378
Directory /workspace/20.rv_dm_stress_all/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.1133189302
Short name T230
Test name
Test status
Simulation time 137812169 ps
CPU time 0.75 seconds
Started Aug 13 05:36:23 PM PDT 24
Finished Aug 13 05:36:24 PM PDT 24
Peak memory 205052 kb
Host smart-89fe50f8-ac80-4f6c-a33a-c4174e08a7ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133189302 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.1133189302
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_stress_all.2061149575
Short name T22
Test name
Test status
Simulation time 2769674897 ps
CPU time 5.85 seconds
Started Aug 13 05:36:37 PM PDT 24
Finished Aug 13 05:36:43 PM PDT 24
Peak memory 213364 kb
Host smart-7ac77ba1-2a5b-400d-9f04-78a1f4c1a748
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061149575 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.2061149575
Directory /workspace/21.rv_dm_stress_all/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.2004363178
Short name T223
Test name
Test status
Simulation time 86767965 ps
CPU time 0.77 seconds
Started Aug 13 05:36:39 PM PDT 24
Finished Aug 13 05:36:39 PM PDT 24
Peak memory 205036 kb
Host smart-fe7c930b-67db-488d-a8fe-dce461b408ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004363178 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.2004363178
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.2455091210
Short name T200
Test name
Test status
Simulation time 119154473 ps
CPU time 0.76 seconds
Started Aug 13 05:36:34 PM PDT 24
Finished Aug 13 05:36:35 PM PDT 24
Peak memory 205048 kb
Host smart-ff25398d-9ca8-4f77-93c9-e750cb7a77db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455091210 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.2455091210
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_stress_all.826310915
Short name T81
Test name
Test status
Simulation time 1136856258 ps
CPU time 2.62 seconds
Started Aug 13 05:36:25 PM PDT 24
Finished Aug 13 05:36:28 PM PDT 24
Peak memory 213120 kb
Host smart-bd712f31-adcd-41dc-a35d-74cd62ba12cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826310915 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.826310915
Directory /workspace/23.rv_dm_stress_all/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.593229249
Short name T288
Test name
Test status
Simulation time 48150141 ps
CPU time 0.69 seconds
Started Aug 13 05:36:47 PM PDT 24
Finished Aug 13 05:36:48 PM PDT 24
Peak memory 205040 kb
Host smart-5a2d0534-f995-4271-9181-b079b887b4a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593229249 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.593229249
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_stress_all.2859457399
Short name T58
Test name
Test status
Simulation time 2322585054 ps
CPU time 3.98 seconds
Started Aug 13 05:36:25 PM PDT 24
Finished Aug 13 05:36:29 PM PDT 24
Peak memory 213396 kb
Host smart-ea5235e5-f4aa-499d-b33a-7839b9230e21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859457399 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.2859457399
Directory /workspace/24.rv_dm_stress_all/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.2711930361
Short name T84
Test name
Test status
Simulation time 115668408 ps
CPU time 0.96 seconds
Started Aug 13 05:36:28 PM PDT 24
Finished Aug 13 05:36:29 PM PDT 24
Peak memory 205048 kb
Host smart-5753fc1e-b392-4aca-a0c7-2eb91a4b6c7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711930361 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.2711930361
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_stress_all.2292452628
Short name T170
Test name
Test status
Simulation time 3937787459 ps
CPU time 9.29 seconds
Started Aug 13 05:36:27 PM PDT 24
Finished Aug 13 05:36:37 PM PDT 24
Peak memory 205200 kb
Host smart-456ab270-1af1-4a24-9607-3dc9e39ae3a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292452628 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.2292452628
Directory /workspace/25.rv_dm_stress_all/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.1422501214
Short name T215
Test name
Test status
Simulation time 39410174 ps
CPU time 0.75 seconds
Started Aug 13 05:36:31 PM PDT 24
Finished Aug 13 05:36:32 PM PDT 24
Peak memory 205016 kb
Host smart-346d2d68-c491-4a38-9405-3560e1f9c360
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422501214 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.1422501214
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_stress_all.2688781567
Short name T251
Test name
Test status
Simulation time 4226784739 ps
CPU time 11.7 seconds
Started Aug 13 05:36:44 PM PDT 24
Finished Aug 13 05:36:56 PM PDT 24
Peak memory 213432 kb
Host smart-de8386d3-8efb-42f4-abf0-03497608f558
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688781567 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.2688781567
Directory /workspace/26.rv_dm_stress_all/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.759497089
Short name T78
Test name
Test status
Simulation time 34502716 ps
CPU time 0.67 seconds
Started Aug 13 05:36:46 PM PDT 24
Finished Aug 13 05:36:47 PM PDT 24
Peak memory 205056 kb
Host smart-a0ffa9c4-6e87-422b-866f-6dc6807ad860
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759497089 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.759497089
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_stress_all.3236407941
Short name T9
Test name
Test status
Simulation time 1884617578 ps
CPU time 3.65 seconds
Started Aug 13 05:36:30 PM PDT 24
Finished Aug 13 05:36:34 PM PDT 24
Peak memory 205072 kb
Host smart-a916f7af-2f18-4764-84d0-856ca291b359
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236407941 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.3236407941
Directory /workspace/27.rv_dm_stress_all/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.1947353791
Short name T83
Test name
Test status
Simulation time 46756125 ps
CPU time 0.72 seconds
Started Aug 13 05:36:28 PM PDT 24
Finished Aug 13 05:36:28 PM PDT 24
Peak memory 204996 kb
Host smart-6d9173ef-4f3e-492e-889c-0029a910fe27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947353791 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.1947353791
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_stress_all.2931150586
Short name T280
Test name
Test status
Simulation time 2796594220 ps
CPU time 6.6 seconds
Started Aug 13 05:36:32 PM PDT 24
Finished Aug 13 05:36:38 PM PDT 24
Peak memory 213364 kb
Host smart-5b625df8-9f70-439f-b334-f1eb6aaccb36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931150586 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.2931150586
Directory /workspace/28.rv_dm_stress_all/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.1416945217
Short name T195
Test name
Test status
Simulation time 39059662 ps
CPU time 0.71 seconds
Started Aug 13 05:36:39 PM PDT 24
Finished Aug 13 05:36:40 PM PDT 24
Peak memory 205028 kb
Host smart-7d4242da-4e76-4d78-b69c-bb5c13a426ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416945217 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.1416945217
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_stress_all.1588486761
Short name T285
Test name
Test status
Simulation time 3376888584 ps
CPU time 5.35 seconds
Started Aug 13 05:36:32 PM PDT 24
Finished Aug 13 05:36:37 PM PDT 24
Peak memory 205156 kb
Host smart-721408e8-ae5a-4191-9c68-c6988a20dbd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588486761 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.1588486761
Directory /workspace/29.rv_dm_stress_all/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.859685647
Short name T222
Test name
Test status
Simulation time 153448732 ps
CPU time 0.98 seconds
Started Aug 13 05:36:03 PM PDT 24
Finished Aug 13 05:36:04 PM PDT 24
Peak memory 204960 kb
Host smart-a3b93262-6fba-4230-92d7-38bb0f5617a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859685647 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.859685647
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.2896812868
Short name T313
Test name
Test status
Simulation time 23718507061 ps
CPU time 18.8 seconds
Started Aug 13 05:36:01 PM PDT 24
Finished Aug 13 05:36:20 PM PDT 24
Peak memory 213464 kb
Host smart-59524bc4-1b53-4c9e-9120-d7fec07cdbf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896812868 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.2896812868
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.314477676
Short name T289
Test name
Test status
Simulation time 8440865118 ps
CPU time 10.66 seconds
Started Aug 13 05:36:01 PM PDT 24
Finished Aug 13 05:36:11 PM PDT 24
Peak memory 214668 kb
Host smart-a39055af-d7a1-480c-9a96-fe1ea5ae335d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314477676 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.314477676
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_buffered_enable.247989172
Short name T314
Test name
Test status
Simulation time 95156168 ps
CPU time 1.07 seconds
Started Aug 13 05:36:00 PM PDT 24
Finished Aug 13 05:36:01 PM PDT 24
Peak memory 233984 kb
Host smart-e438f3a8-625d-486c-be04-e259d8456733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247989172 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_buffered_enable.247989172
Directory /workspace/3.rv_dm_buffered_enable/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.4081153252
Short name T320
Test name
Test status
Simulation time 5370719212 ps
CPU time 15.68 seconds
Started Aug 13 05:36:07 PM PDT 24
Finished Aug 13 05:36:23 PM PDT 24
Peak memory 213616 kb
Host smart-920717f3-1ce4-40ac-8c38-020340044fd2
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4081153252 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t
l_access.4081153252
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_halt_resume_whereto.429782065
Short name T250
Test name
Test status
Simulation time 180896255 ps
CPU time 0.85 seconds
Started Aug 13 05:36:12 PM PDT 24
Finished Aug 13 05:36:13 PM PDT 24
Peak memory 204896 kb
Host smart-ba09ac99-3db0-44f1-8db4-9e50297bc968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429782065 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_halt_resume_whereto.429782065
Directory /workspace/3.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.775334203
Short name T271
Test name
Test status
Simulation time 71424756 ps
CPU time 0.84 seconds
Started Aug 13 05:36:00 PM PDT 24
Finished Aug 13 05:36:01 PM PDT 24
Peak memory 204888 kb
Host smart-aa314480-d805-44ec-9eae-c8e69bc657e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775334203 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.775334203
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.873297734
Short name T276
Test name
Test status
Simulation time 2557544518 ps
CPU time 7.12 seconds
Started Aug 13 05:35:59 PM PDT 24
Finished Aug 13 05:36:06 PM PDT 24
Peak memory 205372 kb
Host smart-6db96759-f50f-4694-b01b-f5f4dc2e5bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873297734 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.873297734
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.2679128378
Short name T37
Test name
Test status
Simulation time 1204034232 ps
CPU time 1.46 seconds
Started Aug 13 05:36:03 PM PDT 24
Finished Aug 13 05:36:04 PM PDT 24
Peak memory 229540 kb
Host smart-bce12e54-910f-4ffb-ae66-0eda0cb85f30
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679128378 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.2679128378
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.3035810225
Short name T204
Test name
Test status
Simulation time 44118351 ps
CPU time 0.79 seconds
Started Aug 13 05:36:37 PM PDT 24
Finished Aug 13 05:36:38 PM PDT 24
Peak memory 204984 kb
Host smart-acd93ae2-692a-4385-81c1-79a9105794c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035810225 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.3035810225
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.87810808
Short name T261
Test name
Test status
Simulation time 70864318 ps
CPU time 0.74 seconds
Started Aug 13 05:36:50 PM PDT 24
Finished Aug 13 05:36:51 PM PDT 24
Peak memory 205056 kb
Host smart-1487b26b-8f29-4f73-94bd-47aea82b373e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87810808 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.87810808
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_stress_all.1762122742
Short name T51
Test name
Test status
Simulation time 1420531841 ps
CPU time 2.98 seconds
Started Aug 13 05:36:53 PM PDT 24
Finished Aug 13 05:36:56 PM PDT 24
Peak memory 205104 kb
Host smart-182420ff-8888-4ae3-801d-fcd0aa59a816
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762122742 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.1762122742
Directory /workspace/31.rv_dm_stress_all/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.2323067341
Short name T87
Test name
Test status
Simulation time 69569458 ps
CPU time 0.82 seconds
Started Aug 13 05:36:30 PM PDT 24
Finished Aug 13 05:36:31 PM PDT 24
Peak memory 205016 kb
Host smart-b5f06585-190d-4cd6-9bcc-d759dfbaec13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323067341 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.2323067341
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_stress_all.160252101
Short name T175
Test name
Test status
Simulation time 4119202020 ps
CPU time 6.17 seconds
Started Aug 13 05:36:28 PM PDT 24
Finished Aug 13 05:36:34 PM PDT 24
Peak memory 205264 kb
Host smart-a4c5dc6b-c751-452d-9dd0-bf715543e877
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160252101 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.160252101
Directory /workspace/32.rv_dm_stress_all/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.3940089315
Short name T33
Test name
Test status
Simulation time 56649872 ps
CPU time 0.76 seconds
Started Aug 13 05:36:27 PM PDT 24
Finished Aug 13 05:36:28 PM PDT 24
Peak memory 205080 kb
Host smart-3c1365c1-9a4c-4f83-88db-1386cc33bf25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940089315 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.3940089315
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_stress_all.583882055
Short name T266
Test name
Test status
Simulation time 5461539214 ps
CPU time 16.82 seconds
Started Aug 13 05:36:51 PM PDT 24
Finished Aug 13 05:37:08 PM PDT 24
Peak memory 213352 kb
Host smart-022cca86-77e8-4f7e-97ec-a4c8b30c5b9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583882055 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.583882055
Directory /workspace/33.rv_dm_stress_all/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.2150807841
Short name T220
Test name
Test status
Simulation time 43923965 ps
CPU time 0.8 seconds
Started Aug 13 05:36:31 PM PDT 24
Finished Aug 13 05:36:32 PM PDT 24
Peak memory 204900 kb
Host smart-0a3d608a-ecf2-4038-a6fb-b5053fc7cb2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150807841 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.2150807841
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_stress_all.1967513113
Short name T294
Test name
Test status
Simulation time 7165119310 ps
CPU time 6.74 seconds
Started Aug 13 05:36:27 PM PDT 24
Finished Aug 13 05:36:34 PM PDT 24
Peak memory 205256 kb
Host smart-e90e01cb-06cc-430f-99d2-431d433ab864
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967513113 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.1967513113
Directory /workspace/34.rv_dm_stress_all/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.4112967471
Short name T202
Test name
Test status
Simulation time 83489297 ps
CPU time 0.9 seconds
Started Aug 13 05:36:27 PM PDT 24
Finished Aug 13 05:36:28 PM PDT 24
Peak memory 205044 kb
Host smart-7c0733b2-8f8b-4973-9174-518d6d1c2183
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112967471 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.4112967471
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_stress_all.3360916601
Short name T29
Test name
Test status
Simulation time 3438580367 ps
CPU time 3.92 seconds
Started Aug 13 05:36:26 PM PDT 24
Finished Aug 13 05:36:30 PM PDT 24
Peak memory 213428 kb
Host smart-3c4372cf-c44c-4637-9b5f-017174812d6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360916601 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.3360916601
Directory /workspace/35.rv_dm_stress_all/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.3088505267
Short name T236
Test name
Test status
Simulation time 170389122 ps
CPU time 0.84 seconds
Started Aug 13 05:36:31 PM PDT 24
Finished Aug 13 05:36:32 PM PDT 24
Peak memory 205016 kb
Host smart-1dc3d653-98a0-49b0-8ef5-8c00e6c61079
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088505267 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.3088505267
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_stress_all.2478565956
Short name T16
Test name
Test status
Simulation time 4490418819 ps
CPU time 4.65 seconds
Started Aug 13 05:36:37 PM PDT 24
Finished Aug 13 05:36:42 PM PDT 24
Peak memory 205128 kb
Host smart-4cd12f6f-0c99-4095-9fef-a21df589bdb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478565956 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.2478565956
Directory /workspace/36.rv_dm_stress_all/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.2906056789
Short name T257
Test name
Test status
Simulation time 113395906 ps
CPU time 0.74 seconds
Started Aug 13 05:36:37 PM PDT 24
Finished Aug 13 05:36:37 PM PDT 24
Peak memory 204972 kb
Host smart-a9d10642-9b78-4200-8a46-307073884378
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906056789 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.2906056789
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_stress_all.4209654378
Short name T286
Test name
Test status
Simulation time 1193574128 ps
CPU time 2.26 seconds
Started Aug 13 05:37:04 PM PDT 24
Finished Aug 13 05:37:07 PM PDT 24
Peak memory 213376 kb
Host smart-367b5c9c-8b31-44c9-b727-550355d6b109
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209654378 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.4209654378
Directory /workspace/37.rv_dm_stress_all/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.3621884642
Short name T206
Test name
Test status
Simulation time 109367043 ps
CPU time 0.76 seconds
Started Aug 13 05:36:52 PM PDT 24
Finished Aug 13 05:36:53 PM PDT 24
Peak memory 205048 kb
Host smart-3c039207-7482-459a-bbb0-7d920ea35d4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621884642 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.3621884642
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_stress_all.3375029595
Short name T240
Test name
Test status
Simulation time 3595316610 ps
CPU time 3.34 seconds
Started Aug 13 05:36:28 PM PDT 24
Finished Aug 13 05:36:32 PM PDT 24
Peak memory 205272 kb
Host smart-1e9f5a6c-bf84-4a95-ba25-12f764daaff7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375029595 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.3375029595
Directory /workspace/39.rv_dm_stress_all/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.860925186
Short name T80
Test name
Test status
Simulation time 40154221 ps
CPU time 0.71 seconds
Started Aug 13 05:36:00 PM PDT 24
Finished Aug 13 05:36:01 PM PDT 24
Peak memory 204992 kb
Host smart-64ab6b43-d550-4079-82a7-f048119a32a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860925186 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.860925186
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.1875036620
Short name T248
Test name
Test status
Simulation time 14870706377 ps
CPU time 43.31 seconds
Started Aug 13 05:36:01 PM PDT 24
Finished Aug 13 05:36:44 PM PDT 24
Peak memory 215784 kb
Host smart-fc62c070-fcc8-417a-93bd-2c6153fd22cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875036620 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.1875036620
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.992067404
Short name T180
Test name
Test status
Simulation time 13842695297 ps
CPU time 38.13 seconds
Started Aug 13 05:35:59 PM PDT 24
Finished Aug 13 05:36:38 PM PDT 24
Peak memory 213716 kb
Host smart-733b2fb6-740f-4883-affb-a73364047b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992067404 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.992067404
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_buffered_enable.2471813211
Short name T256
Test name
Test status
Simulation time 689398668 ps
CPU time 1.26 seconds
Started Aug 13 05:35:59 PM PDT 24
Finished Aug 13 05:36:00 PM PDT 24
Peak memory 233992 kb
Host smart-a62c1650-0904-4fb6-8150-3c448a8ab709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471813211 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_buffered_enable.2471813211
Directory /workspace/4.rv_dm_buffered_enable/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.160671045
Short name T209
Test name
Test status
Simulation time 2409354529 ps
CPU time 1.97 seconds
Started Aug 13 05:36:00 PM PDT 24
Finished Aug 13 05:36:02 PM PDT 24
Peak memory 205396 kb
Host smart-0deb0670-b066-4b15-85bd-c1e13c00447a
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=160671045 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_tl
_access.160671045
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_halt_resume_whereto.3654635098
Short name T203
Test name
Test status
Simulation time 254000730 ps
CPU time 1.38 seconds
Started Aug 13 05:36:07 PM PDT 24
Finished Aug 13 05:36:09 PM PDT 24
Peak memory 204900 kb
Host smart-13c5bf79-553f-4ca5-bc1b-c1df0cd3a037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654635098 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_halt_resume_whereto.3654635098
Directory /workspace/4.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.3698297338
Short name T330
Test name
Test status
Simulation time 325491343 ps
CPU time 1 seconds
Started Aug 13 05:36:06 PM PDT 24
Finished Aug 13 05:36:07 PM PDT 24
Peak memory 204932 kb
Host smart-7a41f704-1ddc-4f5d-b29e-d6b667da8b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698297338 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.3698297338
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.3628701520
Short name T287
Test name
Test status
Simulation time 1433604721 ps
CPU time 3.23 seconds
Started Aug 13 05:36:07 PM PDT 24
Finished Aug 13 05:36:10 PM PDT 24
Peak memory 205424 kb
Host smart-45f7127d-d7e0-4366-adf6-f130c9ef8e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628701520 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.3628701520
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_stress_all.4124744964
Short name T85
Test name
Test status
Simulation time 5748007345 ps
CPU time 5.77 seconds
Started Aug 13 05:36:01 PM PDT 24
Finished Aug 13 05:36:07 PM PDT 24
Peak memory 213432 kb
Host smart-8a1e90b2-5fac-4fdf-8309-26f2d5e0acc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124744964 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.4124744964
Directory /workspace/4.rv_dm_stress_all/latest

Test location /workspace/coverage/default/4.rv_dm_stress_all_with_rand_reset.931296932
Short name T11
Test name
Test status
Simulation time 3917119605 ps
CPU time 50.7 seconds
Started Aug 13 05:36:02 PM PDT 24
Finished Aug 13 05:36:52 PM PDT 24
Peak memory 218092 kb
Host smart-17ea5c77-638c-4b9c-b401-5669b3945aef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931296932 -assert nopostp
roc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all_with_rand_reset.931296932
Directory /workspace/4.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.1475812529
Short name T86
Test name
Test status
Simulation time 53414960 ps
CPU time 0.81 seconds
Started Aug 13 05:36:36 PM PDT 24
Finished Aug 13 05:36:37 PM PDT 24
Peak memory 204988 kb
Host smart-a1bc1883-5068-4b19-906f-8aa09fc72153
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475812529 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.1475812529
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/40.rv_dm_stress_all.1594593901
Short name T326
Test name
Test status
Simulation time 2157996095 ps
CPU time 2.92 seconds
Started Aug 13 05:36:38 PM PDT 24
Finished Aug 13 05:36:41 PM PDT 24
Peak memory 205132 kb
Host smart-ff830bdc-bd5a-44ce-a82d-317940212ede
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594593901 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.1594593901
Directory /workspace/40.rv_dm_stress_all/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.3360885866
Short name T273
Test name
Test status
Simulation time 77836866 ps
CPU time 0.77 seconds
Started Aug 13 05:36:44 PM PDT 24
Finished Aug 13 05:36:44 PM PDT 24
Peak memory 205052 kb
Host smart-d72f78df-380a-417d-a1fe-96582eb46b48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360885866 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.3360885866
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.3487705483
Short name T278
Test name
Test status
Simulation time 177496492 ps
CPU time 0.8 seconds
Started Aug 13 05:36:43 PM PDT 24
Finished Aug 13 05:36:44 PM PDT 24
Peak memory 205048 kb
Host smart-c71ed8b4-f9de-4ebf-bd5f-0a7a90033fad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487705483 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.3487705483
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_stress_all.3020524158
Short name T302
Test name
Test status
Simulation time 5583391771 ps
CPU time 8.89 seconds
Started Aug 13 05:36:38 PM PDT 24
Finished Aug 13 05:36:47 PM PDT 24
Peak memory 205088 kb
Host smart-baf06d5b-e855-4a95-9950-0020ee92a356
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020524158 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.3020524158
Directory /workspace/42.rv_dm_stress_all/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.3208497581
Short name T237
Test name
Test status
Simulation time 44568916 ps
CPU time 0.7 seconds
Started Aug 13 05:36:43 PM PDT 24
Finished Aug 13 05:36:44 PM PDT 24
Peak memory 205048 kb
Host smart-18e396b8-019f-4407-b487-1a3eb2556b5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208497581 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.3208497581
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_stress_all.725625866
Short name T8
Test name
Test status
Simulation time 5534039917 ps
CPU time 16.83 seconds
Started Aug 13 05:36:37 PM PDT 24
Finished Aug 13 05:36:54 PM PDT 24
Peak memory 205128 kb
Host smart-bdb65453-6a1f-4b5a-bd1c-8ae708c7840e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725625866 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.725625866
Directory /workspace/43.rv_dm_stress_all/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.540445402
Short name T197
Test name
Test status
Simulation time 44937652 ps
CPU time 0.72 seconds
Started Aug 13 05:36:35 PM PDT 24
Finished Aug 13 05:36:36 PM PDT 24
Peak memory 205236 kb
Host smart-5a03997c-21bd-43d2-a271-9a1582790867
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540445402 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.540445402
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_stress_all.221060811
Short name T242
Test name
Test status
Simulation time 4168709460 ps
CPU time 3.68 seconds
Started Aug 13 05:36:44 PM PDT 24
Finished Aug 13 05:36:48 PM PDT 24
Peak memory 205228 kb
Host smart-c1fc9f42-9505-49a8-8260-be0c5968d395
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221060811 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.221060811
Directory /workspace/44.rv_dm_stress_all/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.325769651
Short name T139
Test name
Test status
Simulation time 35261382 ps
CPU time 0.74 seconds
Started Aug 13 05:36:36 PM PDT 24
Finished Aug 13 05:36:37 PM PDT 24
Peak memory 204940 kb
Host smart-bed84ada-f63e-4b5e-a91a-e0febae062b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325769651 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.325769651
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_stress_all.450751763
Short name T181
Test name
Test status
Simulation time 1928426435 ps
CPU time 5.6 seconds
Started Aug 13 05:36:37 PM PDT 24
Finished Aug 13 05:36:43 PM PDT 24
Peak memory 205156 kb
Host smart-58244094-4496-4651-ab97-a75cb3375cef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450751763 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.450751763
Directory /workspace/45.rv_dm_stress_all/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.3550423709
Short name T205
Test name
Test status
Simulation time 86499125 ps
CPU time 0.91 seconds
Started Aug 13 05:36:37 PM PDT 24
Finished Aug 13 05:36:38 PM PDT 24
Peak memory 205080 kb
Host smart-9cb8da56-03ab-44e4-a76a-6e4410be61b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550423709 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.3550423709
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_stress_all.3529255493
Short name T26
Test name
Test status
Simulation time 6236986119 ps
CPU time 17.15 seconds
Started Aug 13 05:36:36 PM PDT 24
Finished Aug 13 05:36:54 PM PDT 24
Peak memory 205160 kb
Host smart-235d8a02-a817-421f-a78b-df82e5c0c904
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529255493 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.3529255493
Directory /workspace/46.rv_dm_stress_all/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.610907876
Short name T274
Test name
Test status
Simulation time 169450678 ps
CPU time 0.86 seconds
Started Aug 13 05:36:45 PM PDT 24
Finished Aug 13 05:36:46 PM PDT 24
Peak memory 205020 kb
Host smart-be2bdbad-ca34-4ef7-8134-099dfb8fd26b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610907876 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.610907876
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_stress_all.1928175568
Short name T324
Test name
Test status
Simulation time 3231373382 ps
CPU time 9.71 seconds
Started Aug 13 05:36:39 PM PDT 24
Finished Aug 13 05:36:49 PM PDT 24
Peak memory 205232 kb
Host smart-d09bed26-a6e3-419f-89dd-fce05c6f673a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928175568 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.1928175568
Directory /workspace/47.rv_dm_stress_all/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.2683436373
Short name T253
Test name
Test status
Simulation time 99527071 ps
CPU time 0.78 seconds
Started Aug 13 05:36:35 PM PDT 24
Finished Aug 13 05:36:35 PM PDT 24
Peak memory 205044 kb
Host smart-ba4816ca-57f9-4ca1-85d9-294a8d6606f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683436373 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.2683436373
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_stress_all.3884621338
Short name T15
Test name
Test status
Simulation time 7343811906 ps
CPU time 10.29 seconds
Started Aug 13 05:36:52 PM PDT 24
Finished Aug 13 05:37:02 PM PDT 24
Peak memory 205148 kb
Host smart-f1bde117-838c-41fe-9057-1edba0072f87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884621338 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.3884621338
Directory /workspace/48.rv_dm_stress_all/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.3144227812
Short name T229
Test name
Test status
Simulation time 92168575 ps
CPU time 0.68 seconds
Started Aug 13 05:36:54 PM PDT 24
Finished Aug 13 05:36:55 PM PDT 24
Peak memory 205064 kb
Host smart-a94f884f-8aa8-4e2b-ac49-b9329fdd1401
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144227812 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.3144227812
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_stress_all.2298996233
Short name T310
Test name
Test status
Simulation time 3800572094 ps
CPU time 3.8 seconds
Started Aug 13 05:36:38 PM PDT 24
Finished Aug 13 05:36:42 PM PDT 24
Peak memory 213284 kb
Host smart-eb3f6b4e-b507-45cc-9cb6-36f1ec7c174e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298996233 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.2298996233
Directory /workspace/49.rv_dm_stress_all/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.1421544071
Short name T233
Test name
Test status
Simulation time 93892949 ps
CPU time 0.77 seconds
Started Aug 13 05:36:07 PM PDT 24
Finished Aug 13 05:36:08 PM PDT 24
Peak memory 205020 kb
Host smart-c8770557-bb16-4e8d-95d5-f5a070c0a37c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421544071 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.1421544071
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.3274897064
Short name T268
Test name
Test status
Simulation time 3992925096 ps
CPU time 8 seconds
Started Aug 13 05:36:00 PM PDT 24
Finished Aug 13 05:36:08 PM PDT 24
Peak memory 213612 kb
Host smart-3e4b1961-362a-470a-9af9-5b74d67d8c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274897064 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.3274897064
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.426029544
Short name T252
Test name
Test status
Simulation time 1291888553 ps
CPU time 2.25 seconds
Started Aug 13 05:36:03 PM PDT 24
Finished Aug 13 05:36:05 PM PDT 24
Peak memory 205368 kb
Host smart-cfee74aa-3a30-43ab-a9f9-ad03e3a7b02a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426029544 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.426029544
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_buffered_enable.613172339
Short name T75
Test name
Test status
Simulation time 342385938 ps
CPU time 1.61 seconds
Started Aug 13 05:36:00 PM PDT 24
Finished Aug 13 05:36:02 PM PDT 24
Peak memory 234056 kb
Host smart-db2c38a1-f327-4a6a-9cfa-0335b1f79768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613172339 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_buffered_enable.613172339
Directory /workspace/5.rv_dm_buffered_enable/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.2506543849
Short name T122
Test name
Test status
Simulation time 2111597238 ps
CPU time 2.69 seconds
Started Aug 13 05:36:01 PM PDT 24
Finished Aug 13 05:36:04 PM PDT 24
Peak memory 205344 kb
Host smart-6328ed4b-c745-4043-8198-649e4366d6c5
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2506543849 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t
l_access.2506543849
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_halt_resume_whereto.395539134
Short name T283
Test name
Test status
Simulation time 989678390 ps
CPU time 1.99 seconds
Started Aug 13 05:36:07 PM PDT 24
Finished Aug 13 05:36:10 PM PDT 24
Peak memory 204908 kb
Host smart-339914ff-466b-441f-ae6b-1f2dca56672a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395539134 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_halt_resume_whereto.395539134
Directory /workspace/5.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.1658376628
Short name T185
Test name
Test status
Simulation time 6190872393 ps
CPU time 3.39 seconds
Started Aug 13 05:35:59 PM PDT 24
Finished Aug 13 05:36:03 PM PDT 24
Peak memory 205384 kb
Host smart-0e9fd9ec-60b8-434c-972b-c4a43da1049a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658376628 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.1658376628
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_stress_all.1561047278
Short name T173
Test name
Test status
Simulation time 2100992200 ps
CPU time 2.31 seconds
Started Aug 13 05:36:02 PM PDT 24
Finished Aug 13 05:36:05 PM PDT 24
Peak memory 205136 kb
Host smart-da92b922-1599-4f82-94cc-f20166fde0d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561047278 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.1561047278
Directory /workspace/5.rv_dm_stress_all/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.3219810510
Short name T88
Test name
Test status
Simulation time 141424278 ps
CPU time 0.7 seconds
Started Aug 13 05:36:09 PM PDT 24
Finished Aug 13 05:36:10 PM PDT 24
Peak memory 205008 kb
Host smart-f4ffe6d2-25a5-4dc7-af88-652293599ae2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219810510 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.3219810510
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.3789967518
Short name T123
Test name
Test status
Simulation time 951510773 ps
CPU time 1.65 seconds
Started Aug 13 05:36:09 PM PDT 24
Finished Aug 13 05:36:11 PM PDT 24
Peak memory 205404 kb
Host smart-bd62a814-d9d5-4b92-a478-0c0e51a1b008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789967518 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.3789967518
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_buffered_enable.1666096392
Short name T68
Test name
Test status
Simulation time 223224065 ps
CPU time 0.94 seconds
Started Aug 13 05:36:06 PM PDT 24
Finished Aug 13 05:36:07 PM PDT 24
Peak memory 234752 kb
Host smart-d97630ae-a2dd-4fc7-8f53-97a13a6957fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666096392 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_buffered_enable.1666096392
Directory /workspace/6.rv_dm_buffered_enable/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.612195593
Short name T14
Test name
Test status
Simulation time 3866582360 ps
CPU time 11.57 seconds
Started Aug 13 05:36:01 PM PDT 24
Finished Aug 13 05:36:13 PM PDT 24
Peak memory 213668 kb
Host smart-f4b985d6-6e01-4ea5-85c3-04aa00699eca
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=612195593 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_tl
_access.612195593
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_halt_resume_whereto.2933752249
Short name T254
Test name
Test status
Simulation time 1053791740 ps
CPU time 3.69 seconds
Started Aug 13 05:36:00 PM PDT 24
Finished Aug 13 05:36:04 PM PDT 24
Peak memory 204900 kb
Host smart-60724d48-b945-4b34-823c-bf032a25592a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933752249 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_halt_resume_whereto.2933752249
Directory /workspace/6.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.3936002331
Short name T244
Test name
Test status
Simulation time 1849955000 ps
CPU time 6.34 seconds
Started Aug 13 05:36:06 PM PDT 24
Finished Aug 13 05:36:13 PM PDT 24
Peak memory 205328 kb
Host smart-f5239602-abf5-4504-9c91-8682e48bab23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936002331 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.3936002331
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_stress_all.2669755364
Short name T20
Test name
Test status
Simulation time 2230904692 ps
CPU time 2.39 seconds
Started Aug 13 05:36:22 PM PDT 24
Finished Aug 13 05:36:25 PM PDT 24
Peak memory 213316 kb
Host smart-5add55e5-3202-4721-a595-84c9a3788cc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669755364 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.2669755364
Directory /workspace/6.rv_dm_stress_all/latest

Test location /workspace/coverage/default/6.rv_dm_stress_all_with_rand_reset.4157058913
Short name T24
Test name
Test status
Simulation time 4884806021 ps
CPU time 40.57 seconds
Started Aug 13 05:36:09 PM PDT 24
Finished Aug 13 05:36:50 PM PDT 24
Peak memory 221760 kb
Host smart-5c0580db-7015-47c8-8389-b9f55f1de125
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157058913 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all_with_rand_reset.4157058913
Directory /workspace/6.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.834257153
Short name T235
Test name
Test status
Simulation time 41875457 ps
CPU time 0.84 seconds
Started Aug 13 05:36:09 PM PDT 24
Finished Aug 13 05:36:10 PM PDT 24
Peak memory 205012 kb
Host smart-cc414d91-4bc1-4fb4-b7ec-1de57e030794
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834257153 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.834257153
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.2385660009
Short name T30
Test name
Test status
Simulation time 11494615698 ps
CPU time 9.39 seconds
Started Aug 13 05:36:14 PM PDT 24
Finished Aug 13 05:36:24 PM PDT 24
Peak memory 213612 kb
Host smart-b6d43837-6fa8-44b6-9429-ed04e8badf67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385660009 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.2385660009
Directory /workspace/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.3130758748
Short name T247
Test name
Test status
Simulation time 7617944468 ps
CPU time 9.54 seconds
Started Aug 13 05:36:07 PM PDT 24
Finished Aug 13 05:36:17 PM PDT 24
Peak memory 213640 kb
Host smart-50612f78-5c46-4d2e-af02-dcbded684621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130758748 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.3130758748
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_buffered_enable.1885106984
Short name T93
Test name
Test status
Simulation time 319211452 ps
CPU time 1.07 seconds
Started Aug 13 05:36:05 PM PDT 24
Finished Aug 13 05:36:06 PM PDT 24
Peak memory 225688 kb
Host smart-3bdde06d-c625-4823-b7a4-244ef044001e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885106984 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_buffered_enable.1885106984
Directory /workspace/7.rv_dm_buffered_enable/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.3828524475
Short name T323
Test name
Test status
Simulation time 2925313862 ps
CPU time 3.4 seconds
Started Aug 13 05:36:10 PM PDT 24
Finished Aug 13 05:36:13 PM PDT 24
Peak memory 205560 kb
Host smart-1f55265d-946d-4ee8-87de-202e4b1b2487
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3828524475 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t
l_access.3828524475
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_halt_resume_whereto.4030139725
Short name T54
Test name
Test status
Simulation time 1155404166 ps
CPU time 3.78 seconds
Started Aug 13 05:36:12 PM PDT 24
Finished Aug 13 05:36:16 PM PDT 24
Peak memory 204900 kb
Host smart-8faff5ed-6703-4b7c-862e-59baaa1df8fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030139725 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_halt_resume_whereto.4030139725
Directory /workspace/7.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.3637018948
Short name T211
Test name
Test status
Simulation time 4175603002 ps
CPU time 11.63 seconds
Started Aug 13 05:36:20 PM PDT 24
Finished Aug 13 05:36:32 PM PDT 24
Peak memory 205296 kb
Host smart-d5c718b3-f5b8-488b-97ed-ec531eccfe86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637018948 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.3637018948
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_stress_all.1876178750
Short name T49
Test name
Test status
Simulation time 3192310772 ps
CPU time 2.52 seconds
Started Aug 13 05:36:09 PM PDT 24
Finished Aug 13 05:36:11 PM PDT 24
Peak memory 213388 kb
Host smart-09c98363-35f3-43ad-9f27-4b376500e239
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876178750 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.1876178750
Directory /workspace/7.rv_dm_stress_all/latest

Test location /workspace/coverage/default/7.rv_dm_stress_all_with_rand_reset.2002563813
Short name T64
Test name
Test status
Simulation time 13630589083 ps
CPU time 49.54 seconds
Started Aug 13 05:36:10 PM PDT 24
Finished Aug 13 05:36:59 PM PDT 24
Peak memory 213892 kb
Host smart-974661b1-c596-4e16-9d72-a4a2a64627cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002563813 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all_with_rand_reset.2002563813
Directory /workspace/7.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.3182468641
Short name T216
Test name
Test status
Simulation time 48905444 ps
CPU time 0.83 seconds
Started Aug 13 05:36:08 PM PDT 24
Finished Aug 13 05:36:09 PM PDT 24
Peak memory 205064 kb
Host smart-128755db-b1a5-42fb-9852-7366b6b0d9b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182468641 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.3182468641
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.2848262042
Short name T168
Test name
Test status
Simulation time 5340583981 ps
CPU time 10.3 seconds
Started Aug 13 05:36:07 PM PDT 24
Finished Aug 13 05:36:18 PM PDT 24
Peak memory 205720 kb
Host smart-4397446f-9622-496b-a084-92703233127e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848262042 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.2848262042
Directory /workspace/8.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.4083100131
Short name T255
Test name
Test status
Simulation time 4874506296 ps
CPU time 6.55 seconds
Started Aug 13 05:36:07 PM PDT 24
Finished Aug 13 05:36:14 PM PDT 24
Peak memory 205504 kb
Host smart-b75c47ea-a6d1-4b7e-b241-ba427ede2236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083100131 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.4083100131
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.2263385900
Short name T232
Test name
Test status
Simulation time 12266993959 ps
CPU time 32.85 seconds
Started Aug 13 05:36:06 PM PDT 24
Finished Aug 13 05:36:40 PM PDT 24
Peak memory 205472 kb
Host smart-8a407e69-6bb2-44e8-b3ce-afadbdeeb063
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2263385900 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_t
l_access.2263385900
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.2871879617
Short name T293
Test name
Test status
Simulation time 14566337016 ps
CPU time 17.7 seconds
Started Aug 13 05:36:09 PM PDT 24
Finished Aug 13 05:36:27 PM PDT 24
Peak memory 213592 kb
Host smart-64b9996b-d2c3-4f02-94ef-4ea8ed0a5b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871879617 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.2871879617
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_stress_all.674443269
Short name T183
Test name
Test status
Simulation time 2346622695 ps
CPU time 2.8 seconds
Started Aug 13 05:36:07 PM PDT 24
Finished Aug 13 05:36:10 PM PDT 24
Peak memory 205244 kb
Host smart-78f7fb02-385b-440f-9939-558ed4b421b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674443269 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.674443269
Directory /workspace/8.rv_dm_stress_all/latest

Test location /workspace/coverage/default/8.rv_dm_stress_all_with_rand_reset.1237303597
Short name T62
Test name
Test status
Simulation time 4714387335 ps
CPU time 33.06 seconds
Started Aug 13 05:36:13 PM PDT 24
Finished Aug 13 05:36:46 PM PDT 24
Peak memory 221596 kb
Host smart-b36d3115-4e94-430a-90d7-e7fae6a21549
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237303597 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all_with_rand_reset.1237303597
Directory /workspace/8.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.2934905315
Short name T207
Test name
Test status
Simulation time 189909742 ps
CPU time 0.74 seconds
Started Aug 13 05:36:12 PM PDT 24
Finished Aug 13 05:36:13 PM PDT 24
Peak memory 205040 kb
Host smart-79af2569-b06b-4b69-8ec6-655b426cec0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934905315 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.2934905315
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.2503300819
Short name T89
Test name
Test status
Simulation time 21979241354 ps
CPU time 17.49 seconds
Started Aug 13 05:36:08 PM PDT 24
Finished Aug 13 05:36:26 PM PDT 24
Peak memory 213636 kb
Host smart-cd63840d-899b-41d6-935e-2d8df6cc8481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503300819 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.2503300819
Directory /workspace/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.1335686056
Short name T92
Test name
Test status
Simulation time 679398292 ps
CPU time 1.75 seconds
Started Aug 13 05:36:07 PM PDT 24
Finished Aug 13 05:36:09 PM PDT 24
Peak memory 205064 kb
Host smart-36d5d91b-b4f5-4b6d-94b6-a319573edcca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335686056 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.1335686056
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_buffered_enable.3132304269
Short name T46
Test name
Test status
Simulation time 376412285 ps
CPU time 1.07 seconds
Started Aug 13 05:36:14 PM PDT 24
Finished Aug 13 05:36:15 PM PDT 24
Peak memory 226064 kb
Host smart-54bfd9e1-2315-4c23-91fd-f298caee7dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132304269 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_buffered_enable.3132304269
Directory /workspace/9.rv_dm_buffered_enable/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.3423956020
Short name T217
Test name
Test status
Simulation time 4623510640 ps
CPU time 2.81 seconds
Started Aug 13 05:36:13 PM PDT 24
Finished Aug 13 05:36:16 PM PDT 24
Peak memory 205412 kb
Host smart-44a5b361-b07c-4da4-ac66-a043e30b6264
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3423956020 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t
l_access.3423956020
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.2038698025
Short name T309
Test name
Test status
Simulation time 8958507051 ps
CPU time 25.67 seconds
Started Aug 13 05:36:06 PM PDT 24
Finished Aug 13 05:36:32 PM PDT 24
Peak memory 213652 kb
Host smart-3da97d17-c183-44b0-af35-d8e7834ee9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038698025 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.2038698025
Directory /workspace/9.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_stress_all.3512314225
Short name T174
Test name
Test status
Simulation time 5555303226 ps
CPU time 14.18 seconds
Started Aug 13 05:36:14 PM PDT 24
Finished Aug 13 05:36:28 PM PDT 24
Peak memory 213348 kb
Host smart-cc41ed8e-af52-470c-a7fc-b30c168c32cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512314225 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.3512314225
Directory /workspace/9.rv_dm_stress_all/latest
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