Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	291132	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

634973

1

T4

5

T8

1

T5

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	542387	1			T4	4		T8	1		T5	3
values[0x0]	165539	1			T4	4		T8	1		T5	2
values[0x1]	218179	1			T4	5		T5	5		T7	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	197142	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

728963

1

T4

7

T8

1

T5

6

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3806	1			T17	51		T43	16		T19	35
valid_sources[0x01]	3679	1			T17	71		T43	7		T19	54
valid_sources[0x02]	3431	1			T18	1		T17	64		T43	11
valid_sources[0x03]	3655	1			T17	79		T43	17		T19	54
valid_sources[0x04]	3837	1			T17	73		T43	14		T19	43
valid_sources[0x05]	3671	1			T17	59		T43	16		T19	59
valid_sources[0x06]	3833	1			T17	54		T43	12		T19	35
valid_sources[0x07]	3892	1			T17	59		T43	12		T19	39
valid_sources[0x08]	3302	1			T6	1		T39	2		T17	58
valid_sources[0x09]	4049	1			T17	74		T43	16		T19	41
valid_sources[0x0a]	3529	1			T17	74		T43	11		T19	43
valid_sources[0x0b]	3784	1			T17	64		T43	9		T44	3
valid_sources[0x0c]	3652	1			T17	73		T43	19		T19	52
valid_sources[0x0d]	3535	1			T17	70		T43	9		T44	1
valid_sources[0x0e]	3595	1			T17	58		T43	9		T19	47
valid_sources[0x0f]	3757	1			T17	63		T43	16		T19	35
valid_sources[0x10]	3343	1			T17	58		T43	12		T19	43
valid_sources[0x11]	3809	1			T17	71		T43	15		T19	29
valid_sources[0x12]	3491	1			T17	57		T43	21		T19	36
valid_sources[0x13]	3787	1			T17	55		T43	9		T19	37
valid_sources[0x14]	3514	1			T28	4		T17	68		T43	7
valid_sources[0x15]	3772	1			T17	65		T43	14		T19	42
valid_sources[0x16]	3716	1			T17	59		T43	13		T19	60
valid_sources[0x17]	3541	1			T17	73		T43	7		T19	36
valid_sources[0x18]	3334	1			T4	13		T17	89		T43	8
valid_sources[0x19]	3619	1			T17	75		T43	6		T19	49
valid_sources[0x1a]	3751	1			T39	2		T17	71		T43	4
valid_sources[0x1b]	3340	1			T17	58		T43	9		T19	53
valid_sources[0x1c]	3885	1			T17	73		T43	8		T19	34
valid_sources[0x1d]	3922	1			T17	68		T43	9		T19	53
valid_sources[0x1e]	3431	1			T17	53		T43	9		T19	28
valid_sources[0x1f]	3307	1			T17	74		T43	10		T19	50
valid_sources[0x20]	3441	1			T17	49		T43	10		T19	28
valid_sources[0x21]	3289	1			T17	60		T43	11		T19	40
valid_sources[0x22]	3439	1			T17	63		T43	6		T19	44
valid_sources[0x23]	3250	1			T17	47		T43	10		T19	52
valid_sources[0x24]	3803	1			T17	85		T43	9		T19	53
valid_sources[0x25]	3615	1			T17	89		T43	13		T19	39
valid_sources[0x26]	3402	1			T17	77		T43	11		T19	65
valid_sources[0x27]	3515	1			T17	68		T43	2		T19	45
valid_sources[0x28]	3534	1			T17	66		T43	6		T19	40
valid_sources[0x29]	3546	1			T17	59		T43	5		T19	56
valid_sources[0x2a]	3272	1			T17	52		T43	13		T19	51
valid_sources[0x2b]	3987	1			T17	43		T43	13		T19	38
valid_sources[0x2c]	3542	1			T17	54		T43	11		T19	38
valid_sources[0x2d]	3771	1			T17	61		T43	14		T19	45
valid_sources[0x2e]	3622	1			T6	1		T17	72		T43	13
valid_sources[0x2f]	3479	1			T17	73		T43	7		T19	49
valid_sources[0x30]	3542	1			T17	78		T43	10		T19	43
valid_sources[0x31]	3650	1			T17	67		T43	13		T19	49
valid_sources[0x32]	3863	1			T17	71		T43	14		T19	46
valid_sources[0x33]	3487	1			T17	61		T43	13		T19	39
valid_sources[0x34]	3700	1			T17	90		T43	7		T19	53
valid_sources[0x35]	3543	1			T17	69		T43	19		T19	37
valid_sources[0x36]	3988	1			T17	90		T43	10		T19	42
valid_sources[0x37]	3505	1			T17	56		T43	13		T19	53
valid_sources[0x38]	3311	1			T17	76		T43	11		T19	46
valid_sources[0x39]	3700	1			T17	67		T43	8		T19	33
valid_sources[0x3a]	3660	1			T17	64		T43	8		T19	40
valid_sources[0x3b]	3987	1			T17	60		T43	8		T19	44
valid_sources[0x3c]	3489	1			T17	58		T43	11		T19	53
valid_sources[0x3d]	3796	1			T17	85		T43	8		T19	30
valid_sources[0x3e]	3590	1			T17	68		T43	7		T19	42
valid_sources[0x3f]	3522	1			T17	59		T43	9		T19	46
valid_sources[0x40]	4075	1			T17	79		T43	9		T19	28
valid_sources[0x41]	3390	1			T17	70		T43	14		T19	38
valid_sources[0x42]	3654	1			T17	76		T43	12		T19	55
valid_sources[0x43]	4020	1			T6	3		T17	75		T43	12
valid_sources[0x44]	3344	1			T17	70		T43	15		T19	44
valid_sources[0x45]	3660	1			T17	91		T43	10		T19	35
valid_sources[0x46]	3489	1			T17	49		T43	11		T19	22
valid_sources[0x47]	3522	1			T17	71		T43	5		T19	54
valid_sources[0x48]	3760	1			T6	1		T28	1		T17	57
valid_sources[0x49]	3789	1			T17	62		T43	10		T19	43
valid_sources[0x4a]	3749	1			T17	80		T43	12		T19	42
valid_sources[0x4b]	3581	1			T17	65		T43	12		T19	39
valid_sources[0x4c]	3444	1			T21	5		T17	70		T43	11
valid_sources[0x4d]	3939	1			T17	77		T43	10		T19	51
valid_sources[0x4e]	3674	1			T17	53		T43	12		T19	42
valid_sources[0x4f]	3543	1			T17	64		T43	4		T19	41
valid_sources[0x50]	5587	1			T17	54		T106	4		T43	14
valid_sources[0x51]	3617	1			T17	62		T43	8		T19	38
valid_sources[0x52]	3549	1			T17	79		T43	7		T19	48
valid_sources[0x53]	3476	1			T17	61		T43	12		T19	41
valid_sources[0x54]	3517	1			T17	65		T43	16		T161	1
valid_sources[0x55]	3558	1			T17	56		T43	11		T19	44
valid_sources[0x56]	3398	1			T17	70		T43	9		T19	43
valid_sources[0x57]	3447	1			T17	68		T43	10		T19	40
valid_sources[0x58]	4153	1			T17	76		T43	11		T161	2
valid_sources[0x59]	3814	1			T17	60		T43	10		T19	48
valid_sources[0x5a]	3447	1			T17	71		T43	9		T19	57
valid_sources[0x5b]	4008	1			T17	50		T43	9		T19	51
valid_sources[0x5c]	3672	1			T17	68		T43	8		T19	32
valid_sources[0x5d]	3333	1			T17	92		T43	8		T19	57
valid_sources[0x5e]	3522	1			T17	56		T43	12		T19	53
valid_sources[0x5f]	3532	1			T6	1		T28	1		T17	71
valid_sources[0x60]	4046	1			T17	70		T43	14		T19	43
valid_sources[0x61]	3321	1			T18	1		T17	83		T43	11
valid_sources[0x62]	3791	1			T17	66		T43	7		T19	41
valid_sources[0x63]	3805	1			T17	65		T43	7		T19	37
valid_sources[0x64]	3685	1			T17	66		T43	12		T19	38
valid_sources[0x65]	4488	1			T17	70		T43	3		T19	36
valid_sources[0x66]	3322	1			T17	56		T43	7		T19	19
valid_sources[0x67]	3448	1			T17	63		T43	13		T19	47
valid_sources[0x68]	3430	1			T17	74		T43	10		T19	43
valid_sources[0x69]	4052	1			T6	1		T17	69		T43	7
valid_sources[0x6a]	3713	1			T17	58		T43	10		T19	29
valid_sources[0x6b]	3813	1			T17	60		T43	13		T19	25
valid_sources[0x6c]	3477	1			T17	70		T43	9		T19	51
valid_sources[0x6d]	3802	1			T17	81		T43	14		T19	42
valid_sources[0x6e]	3518	1			T17	65		T43	12		T19	40
valid_sources[0x6f]	3812	1			T17	74		T43	11		T19	40
valid_sources[0x70]	4044	1			T17	70		T43	13		T19	45
valid_sources[0x71]	3307	1			T17	60		T43	15		T19	55
valid_sources[0x72]	3785	1			T17	67		T43	18		T19	45
valid_sources[0x73]	3664	1			T6	1		T17	66		T43	14
valid_sources[0x74]	3700	1			T17	77		T43	13		T19	31
valid_sources[0x75]	3390	1			T39	1		T17	80		T43	6
valid_sources[0x76]	3349	1			T17	66		T43	15		T19	42
valid_sources[0x77]	3617	1			T17	62		T43	7		T19	31
valid_sources[0x78]	3313	1			T17	71		T43	12		T19	29
valid_sources[0x79]	3543	1			T17	65		T43	11		T19	46
valid_sources[0x7a]	3246	1			T17	53		T43	11		T19	41
valid_sources[0x7b]	3620	1			T17	57		T43	6		T19	65
valid_sources[0x7c]	3830	1			T17	49		T43	15		T19	31
valid_sources[0x7d]	3887	1			T17	62		T43	13		T19	31
valid_sources[0x7e]	3820	1			T17	57		T43	7		T19	38
valid_sources[0x7f]	3766	1			T39	1		T17	69		T43	13
valid_sources[0x80]	3388	1			T17	53		T43	9		T19	46

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

319416

1

T4

1

T5

1

T6

3

values[0x0]

all_enables

biggest_size

158373

1

T4

2

T8

1

T5

2

values[0x1]

all_enables

biggest_size

157184

1

T4

2

T6

1

T21

3

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7725	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

106339

1

T1

7

T2

1

T3

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	31422	1			T17	2592		T43	391		T19	1845
values[0x0]	40471	1			T1	3		T2	1		T3	3
values[0x1]	42171	1			T1	4		T3	3		T29	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4975	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

109089

1

T1

7

T2

1

T3

6

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	536	1			T17	45		T43	6		T19	34
valid_sources[0x01]	377	1			T17	44		T43	11		T162	6
valid_sources[0x02]	594	1			T17	35		T43	2		T19	34
valid_sources[0x03]	415	1			T203	1		T204	2		T17	40
valid_sources[0x04]	422	1			T155	1		T17	33		T43	9
valid_sources[0x05]	428	1			T17	37		T43	10		T19	21
valid_sources[0x06]	450	1			T205	2		T17	43		T43	10
valid_sources[0x07]	375	1			T17	43		T43	7		T19	20
valid_sources[0x08]	452	1			T17	36		T43	6		T19	43
valid_sources[0x09]	386	1			T17	30		T43	9		T19	12
valid_sources[0x0a]	385	1			T39	1		T206	2		T17	33
valid_sources[0x0b]	400	1			T66	2		T17	30		T43	10
valid_sources[0x0c]	518	1			T6	1		T39	1		T17	35
valid_sources[0x0d]	403	1			T207	1		T17	39		T43	6
valid_sources[0x0e]	354	1			T17	39		T43	4		T19	26
valid_sources[0x0f]	402	1			T36	1		T17	40		T43	3
valid_sources[0x10]	432	1			T68	1		T17	42		T43	8
valid_sources[0x11]	399	1			T27	1		T206	2		T17	38
valid_sources[0x12]	355	1			T208	1		T17	49		T43	3
valid_sources[0x13]	476	1			T17	46		T43	5		T19	34
valid_sources[0x14]	418	1			T25	2		T17	34		T43	13
valid_sources[0x15]	387	1			T32	1		T27	7		T17	18
valid_sources[0x16]	330	1			T17	37		T43	6		T19	14
valid_sources[0x17]	388	1			T28	2		T66	1		T17	33
valid_sources[0x18]	541	1			T29	1		T17	47		T43	5
valid_sources[0x19]	458	1			T17	38		T43	9		T19	25
valid_sources[0x1a]	408	1			T17	35		T43	10		T19	28
valid_sources[0x1b]	588	1			T32	1		T17	43		T43	9
valid_sources[0x1c]	499	1			T206	1		T17	32		T43	5
valid_sources[0x1d]	377	1			T25	1		T17	41		T43	7
valid_sources[0x1e]	470	1			T1	3		T17	32		T43	6
valid_sources[0x1f]	424	1			T40	1		T209	1		T17	40
valid_sources[0x20]	393	1			T3	1		T32	1		T17	37
valid_sources[0x21]	379	1			T17	32		T43	9		T19	14
valid_sources[0x22]	489	1			T17	46		T43	3		T19	20
valid_sources[0x23]	475	1			T17	27		T43	4		T19	29
valid_sources[0x24]	429	1			T17	37		T43	6		T19	25
valid_sources[0x25]	430	1			T210	1		T17	40		T43	1
valid_sources[0x26]	380	1			T204	1		T17	40		T43	10
valid_sources[0x27]	533	1			T32	1		T39	1		T17	40
valid_sources[0x28]	426	1			T61	1		T25	1		T17	39
valid_sources[0x29]	628	1			T153	1		T17	46		T43	8
valid_sources[0x2a]	452	1			T17	45		T43	5		T19	36
valid_sources[0x2b]	515	1			T1	3		T68	1		T17	44
valid_sources[0x2c]	448	1			T208	1		T17	36		T43	8
valid_sources[0x2d]	423	1			T204	1		T17	40		T43	2
valid_sources[0x2e]	442	1			T155	1		T17	43		T43	9
valid_sources[0x2f]	445	1			T17	37		T43	5		T160	1
valid_sources[0x30]	440	1			T17	37		T43	4		T161	1
valid_sources[0x31]	349	1			T17	22		T43	7		T19	27
valid_sources[0x32]	536	1			T17	29		T43	5		T19	22
valid_sources[0x33]	384	1			T17	28		T43	6		T110	1
valid_sources[0x34]	509	1			T17	38		T43	9		T19	29
valid_sources[0x35]	506	1			T155	1		T17	33		T43	8
valid_sources[0x36]	428	1			T154	1		T17	39		T43	9
valid_sources[0x37]	535	1			T66	1		T17	54		T43	4
valid_sources[0x38]	518	1			T21	1		T17	46		T43	8
valid_sources[0x39]	381	1			T17	39		T43	5		T19	30
valid_sources[0x3a]	593	1			T5	1		T17	40		T43	1
valid_sources[0x3b]	445	1			T28	2		T66	1		T206	1
valid_sources[0x3c]	514	1			T28	1		T17	41		T43	5
valid_sources[0x3d]	435	1			T204	1		T17	40		T43	6
valid_sources[0x3e]	402	1			T153	1		T17	33		T43	7
valid_sources[0x3f]	370	1			T32	1		T17	48		T43	2
valid_sources[0x40]	418	1			T21	1		T17	43		T43	8
valid_sources[0x41]	449	1			T153	2		T17	43		T43	4
valid_sources[0x42]	638	1			T28	1		T17	46		T43	7
valid_sources[0x43]	465	1			T153	1		T204	1		T17	36
valid_sources[0x44]	361	1			T27	2		T17	27		T108	4
valid_sources[0x45]	416	1			T17	26		T43	7		T19	23
valid_sources[0x46]	446	1			T17	45		T43	7		T19	32
valid_sources[0x47]	412	1			T17	44		T43	9		T19	19
valid_sources[0x48]	494	1			T205	2		T17	34		T43	5
valid_sources[0x49]	507	1			T66	1		T17	40		T43	16
valid_sources[0x4a]	394	1			T153	1		T206	1		T17	33
valid_sources[0x4b]	384	1			T68	1		T17	47		T43	4
valid_sources[0x4c]	424	1			T204	1		T17	44		T43	4
valid_sources[0x4d]	364	1			T17	45		T43	3		T19	34
valid_sources[0x4e]	356	1			T17	40		T43	14		T19	19
valid_sources[0x4f]	448	1			T17	35		T43	10		T19	20
valid_sources[0x50]	1262	1			T5	1		T32	1		T152	3
valid_sources[0x51]	376	1			T17	38		T43	2		T19	13
valid_sources[0x52]	501	1			T208	1		T17	37		T43	8
valid_sources[0x53]	422	1			T26	1		T17	47		T43	6
valid_sources[0x54]	388	1			T155	1		T39	1		T17	44
valid_sources[0x55]	342	1			T17	34		T43	3		T19	16
valid_sources[0x56]	483	1			T17	34		T43	4		T19	33
valid_sources[0x57]	431	1			T39	1		T17	37		T43	4
valid_sources[0x58]	449	1			T17	36		T43	7		T19	22
valid_sources[0x59]	391	1			T17	31		T43	2		T112	1
valid_sources[0x5a]	353	1			T17	36		T43	1		T19	41
valid_sources[0x5b]	515	1			T17	44		T43	4		T19	39
valid_sources[0x5c]	411	1			T17	56		T43	12		T19	28
valid_sources[0x5d]	355	1			T32	1		T64	1		T17	40
valid_sources[0x5e]	480	1			T54	1		T17	44		T43	8
valid_sources[0x5f]	471	1			T30	1		T17	59		T43	5
valid_sources[0x60]	396	1			T155	3		T39	2		T17	35
valid_sources[0x61]	408	1			T65	1		T17	36		T43	5
valid_sources[0x62]	479	1			T64	2		T17	30		T43	11
valid_sources[0x63]	555	1			T17	43		T43	3		T19	35
valid_sources[0x64]	450	1			T36	1		T17	34		T43	10
valid_sources[0x65]	428	1			T64	2		T17	46		T43	7
valid_sources[0x66]	404	1			T17	56		T43	7		T19	26
valid_sources[0x67]	436	1			T17	43		T43	3		T19	15
valid_sources[0x68]	309	1			T64	1		T17	43		T43	10
valid_sources[0x69]	493	1			T17	41		T43	3		T19	56
valid_sources[0x6a]	465	1			T29	1		T17	38		T43	4
valid_sources[0x6b]	479	1			T17	37		T43	8		T19	27
valid_sources[0x6c]	440	1			T17	33		T43	4		T19	46
valid_sources[0x6d]	496	1			T64	1		T17	46		T43	10
valid_sources[0x6e]	462	1			T17	36		T43	4		T19	33
valid_sources[0x6f]	368	1			T21	1		T39	1		T17	41
valid_sources[0x70]	410	1			T25	1		T17	38		T43	9
valid_sources[0x71]	429	1			T64	1		T204	4		T17	44
valid_sources[0x72]	358	1			T17	41		T43	3		T19	25
valid_sources[0x73]	447	1			T17	39		T106	1		T43	4
valid_sources[0x74]	446	1			T17	45		T43	8		T19	49
valid_sources[0x75]	434	1			T6	1		T32	1		T66	1
valid_sources[0x76]	402	1			T17	32		T43	4		T19	17
valid_sources[0x77]	421	1			T31	8		T17	29		T43	7
valid_sources[0x78]	371	1			T17	24		T43	8		T19	51
valid_sources[0x79]	395	1			T32	1		T66	1		T206	1
valid_sources[0x7a]	682	1			T39	1		T17	44		T43	7
valid_sources[0x7b]	369	1			T5	1		T6	1		T64	1
valid_sources[0x7c]	616	1			T64	1		T66	4		T17	59
valid_sources[0x7d]	421	1			T17	41		T43	3		T19	29
valid_sources[0x7e]	418	1			T17	25		T43	9		T19	30
valid_sources[0x7f]	394	1			T17	29		T43	4		T19	21
valid_sources[0x80]	396	1			T211	1		T17	32		T43	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27871

1

T17

2419

T43

366

T19

1750

values[0x0]

all_enables

biggest_size

39430

1

T1

3

T2

1

T3

3

values[0x1]

all_enables

biggest_size

39038

1

T1

4

T3

3

T30

1