Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
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Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block] 100.00 1 100 1 64 64




Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 0 16 100.00 100 1 1 0


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
partial 706721 1 T4 8 T8 1 T5 7
full_word 649004 1 T4 5 T8 1 T5 3



Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 1355445 1 T4 13 T8 2 T5 10
auto[TlIntgErrCmd] 101 1 T163 3 T158 7 T164 7
auto[TlIntgErrData] 91 1 T163 3 T158 6 T164 7
auto[TlIntgErrBoth] 88 1 T163 4 T158 7 T164 6



Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 560398 1 T4 4 T8 1 T5 3
auto[1] 795327 1 T4 9 T8 1 T5 7



Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 239290 1 T4 3 T8 1 T5 2
auto[TlIntgErrNone] partial auto[1] 467187 1 T4 5 T5 5 T7 2
auto[TlIntgErrNone] full_word auto[0] 320974 1 T4 1 T5 1 T6 3
auto[TlIntgErrNone] full_word auto[1] 327994 1 T4 4 T8 1 T5 2
auto[TlIntgErrCmd] partial auto[0] 38 1 T163 1 T158 2 T164 1
auto[TlIntgErrCmd] partial auto[1] 55 1 T163 2 T158 5 T164 4
auto[TlIntgErrCmd] full_word auto[0] 3 1 T200 1 T201 2 - -
auto[TlIntgErrCmd] full_word auto[1] 5 1 T164 2 T198 1 T194 1
auto[TlIntgErrData] partial auto[0] 38 1 T163 2 T158 1 T164 4
auto[TlIntgErrData] partial auto[1] 36 1 T163 1 T158 4 T164 2
auto[TlIntgErrData] full_word auto[0] 9 1 T158 1 T198 1 T194 1
auto[TlIntgErrData] full_word auto[1] 8 1 T164 1 T197 1 T200 2
auto[TlIntgErrBoth] partial auto[0] 42 1 T163 1 T158 2 T164 4
auto[TlIntgErrBoth] partial auto[1] 35 1 T163 2 T158 4 T164 2
auto[TlIntgErrBoth] full_word auto[0] 4 1 T158 1 T200 1 T196 1
auto[TlIntgErrBoth] full_word auto[1] 7 1 T163 1 T202 1 T198 1

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