Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.66	100.00	85.71	97.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	108597141	133343	0	0
late_debug_enable_rd_A	108597141	10868	0	0
late_debug_enable_regwen_rd_A	108597141	9639	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	108597141	133343	0	0
T9	0	6174	0	0
T13	0	5953	0	0
T17	430557	14319	0	0
T19	0	8233	0	0
T22	0	6465	0	0
T43	100787	1387	0	0
T45	0	10046	0	0
T51	27389	0	0	0
T53	0	9599	0	0
T75	0	4110	0	0
T88	0	8075	0	0
T106	71509	0	0	0
T107	10165	0	0	0
T108	4069	0	0	0
T109	22076	0	0	0
T110	39057	0	0	0
T111	165741	0	0	0
T112	45095	0	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	108597141	10868	0	0
T19	0	2926	0	0
T43	100787	624	0	0
T44	10261	0	0	0
T51	27389	0	0	0
T53	0	3001	0	0
T75	0	765	0	0
T85	0	23	0	0
T89	0	28	0	0
T110	39057	0	0	0
T111	165741	0	0	0
T112	45095	0	0	0
T114	0	4	0	0
T156	0	122	0	0
T157	0	631	0	0
T158	0	72	0	0
T159	35888	0	0	0
T160	11963	0	0	0
T161	41740	0	0	0
T162	7218	0	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	108597141	9639	0	0
T19	0	2641	0	0
T43	100787	506	0	0
T44	10261	0	0	0
T51	27389	0	0	0
T53	0	2653	0	0
T75	0	701	0	0
T85	0	53	0	0
T89	0	8	0	0
T110	39057	0	0	0
T111	165741	0	0	0
T112	45095	0	0	0
T114	0	34	0	0
T156	0	135	0	0
T157	0	534	0	0
T158	0	81	0	0
T159	35888	0	0	0
T160	11963	0	0	0
T161	41740	0	0	0
T162	7218	0	0	0