Line Coverage for Module :
prim_generic_clock_mux2
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Module :
prim_generic_clock_mux2
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Module :
prim_generic_clock_mux2
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
6886498 |
6885010 |
0 |
0 |
selKnown1 |
50369910 |
50368422 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
6886498 |
6885010 |
0 |
0 |
T1 |
61462 |
61458 |
0 |
0 |
T2 |
16504 |
16500 |
0 |
0 |
T3 |
20844 |
20840 |
0 |
0 |
T4 |
13494 |
13490 |
0 |
0 |
T5 |
8384 |
8380 |
0 |
0 |
T6 |
0 |
5 |
0 |
0 |
T8 |
1462 |
1458 |
0 |
0 |
T18 |
0 |
8 |
0 |
0 |
T24 |
23106 |
23102 |
0 |
0 |
T25 |
0 |
10 |
0 |
0 |
T27 |
0 |
18 |
0 |
0 |
T29 |
292 |
288 |
0 |
0 |
T30 |
26812 |
26808 |
0 |
0 |
T31 |
306 |
302 |
0 |
0 |
T36 |
0 |
4 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
50369910 |
50368422 |
0 |
0 |
T1 |
723119 |
723115 |
0 |
0 |
T2 |
121968 |
121964 |
0 |
0 |
T3 |
467251 |
467247 |
0 |
0 |
T4 |
478761 |
478757 |
0 |
0 |
T5 |
70979 |
70975 |
0 |
0 |
T6 |
0 |
2 |
0 |
0 |
T8 |
11364 |
11360 |
0 |
0 |
T18 |
0 |
8 |
0 |
0 |
T24 |
48294 |
48290 |
0 |
0 |
T25 |
0 |
6 |
0 |
0 |
T27 |
0 |
18 |
0 |
0 |
T29 |
6332 |
6328 |
0 |
0 |
T30 |
156915 |
156911 |
0 |
0 |
T31 |
1845 |
1841 |
0 |
0 |
T36 |
0 |
4 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
2196140 |
2195878 |
0 |
0 |
selKnown1 |
45679662 |
45679400 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2196140 |
2195878 |
0 |
0 |
T1 |
30724 |
30723 |
0 |
0 |
T2 |
8251 |
8250 |
0 |
0 |
T3 |
10416 |
10415 |
0 |
0 |
T4 |
6742 |
6741 |
0 |
0 |
T5 |
4188 |
4187 |
0 |
0 |
T8 |
730 |
729 |
0 |
0 |
T24 |
11549 |
11548 |
0 |
0 |
T29 |
145 |
144 |
0 |
0 |
T30 |
13405 |
13404 |
0 |
0 |
T31 |
152 |
151 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
45679662 |
45679400 |
0 |
0 |
T1 |
692381 |
692380 |
0 |
0 |
T2 |
113715 |
113714 |
0 |
0 |
T3 |
456823 |
456822 |
0 |
0 |
T4 |
472011 |
472010 |
0 |
0 |
T5 |
66783 |
66782 |
0 |
0 |
T8 |
10632 |
10631 |
0 |
0 |
T24 |
36737 |
36736 |
0 |
0 |
T29 |
6185 |
6184 |
0 |
0 |
T30 |
143508 |
143507 |
0 |
0 |
T31 |
1691 |
1690 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
858 |
596 |
0 |
0 |
T1 |
7 |
6 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
5 |
4 |
0 |
0 |
T5 |
4 |
3 |
0 |
0 |
T6 |
0 |
2 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T18 |
0 |
4 |
0 |
0 |
T24 |
4 |
3 |
0 |
0 |
T25 |
0 |
5 |
0 |
0 |
T27 |
0 |
9 |
0 |
0 |
T29 |
1 |
0 |
0 |
0 |
T30 |
1 |
0 |
0 |
0 |
T31 |
1 |
0 |
0 |
0 |
T36 |
0 |
2 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
802 |
540 |
0 |
0 |
T1 |
7 |
6 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
4 |
3 |
0 |
0 |
T5 |
4 |
3 |
0 |
0 |
T6 |
0 |
1 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T18 |
0 |
4 |
0 |
0 |
T24 |
4 |
3 |
0 |
0 |
T25 |
0 |
3 |
0 |
0 |
T27 |
0 |
9 |
0 |
0 |
T29 |
1 |
0 |
0 |
0 |
T30 |
1 |
0 |
0 |
0 |
T31 |
1 |
0 |
0 |
0 |
T36 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
4687735 |
4687253 |
0 |
0 |
selKnown1 |
4687735 |
4687253 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
4687735 |
4687253 |
0 |
0 |
T1 |
30724 |
30723 |
0 |
0 |
T2 |
8251 |
8250 |
0 |
0 |
T3 |
10416 |
10415 |
0 |
0 |
T4 |
6742 |
6741 |
0 |
0 |
T5 |
4188 |
4187 |
0 |
0 |
T8 |
730 |
729 |
0 |
0 |
T24 |
11549 |
11548 |
0 |
0 |
T29 |
145 |
144 |
0 |
0 |
T30 |
13405 |
13404 |
0 |
0 |
T31 |
152 |
151 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
4687735 |
4687253 |
0 |
0 |
T1 |
30724 |
30723 |
0 |
0 |
T2 |
8251 |
8250 |
0 |
0 |
T3 |
10416 |
10415 |
0 |
0 |
T4 |
6742 |
6741 |
0 |
0 |
T5 |
4188 |
4187 |
0 |
0 |
T8 |
730 |
729 |
0 |
0 |
T24 |
11549 |
11548 |
0 |
0 |
T29 |
145 |
144 |
0 |
0 |
T30 |
13405 |
13404 |
0 |
0 |
T31 |
152 |
151 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
1765 |
1283 |
0 |
0 |
selKnown1 |
1711 |
1229 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1765 |
1283 |
0 |
0 |
T1 |
7 |
6 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
5 |
4 |
0 |
0 |
T5 |
4 |
3 |
0 |
0 |
T6 |
0 |
3 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T18 |
0 |
4 |
0 |
0 |
T24 |
4 |
3 |
0 |
0 |
T25 |
0 |
5 |
0 |
0 |
T27 |
0 |
9 |
0 |
0 |
T29 |
1 |
0 |
0 |
0 |
T30 |
1 |
0 |
0 |
0 |
T31 |
1 |
0 |
0 |
0 |
T36 |
0 |
2 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1711 |
1229 |
0 |
0 |
T1 |
7 |
6 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
4 |
3 |
0 |
0 |
T5 |
4 |
3 |
0 |
0 |
T6 |
0 |
1 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T18 |
0 |
4 |
0 |
0 |
T24 |
4 |
3 |
0 |
0 |
T25 |
0 |
3 |
0 |
0 |
T27 |
0 |
9 |
0 |
0 |
T29 |
1 |
0 |
0 |
0 |
T30 |
1 |
0 |
0 |
0 |
T31 |
1 |
0 |
0 |
0 |
T36 |
0 |
2 |
0 |
0 |