SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_lc_sync_lc_hw_debug_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prim_lc_sync_lc_dft_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_en_sync_copies | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_pm_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.66 | 100.00 | 85.71 | 97.60 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.66 | 100.00 | 85.71 | 97.60 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.66 | 100.00 | 85.71 | 97.60 | 100.00 | 100.00 | dut |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.66 | 100.00 | 85.71 | 97.60 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
70.34 | 86.27 | 76.47 | 57.14 | 81.82 | 50.00 | u_tlul_lc_gate_sba |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
90.00 | 100.00 | 100.00 | 100.00 | 100.00 | 50.00 | u_tlul_lc_gate_rom |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1572 | 1572 | 0 | 0 |
OutputsKnown_A | 273967005 | 273581367 | 0 | 0 |
gen_flops.OutputDelay_A | 137038986 | 136838949 | 0 | 2358 |
gen_no_flops.OutputDelay_A | 136928019 | 136735200 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1572 | 1572 | 0 | 0 |
T1 | 6 | 6 | 0 | 0 |
T2 | 6 | 6 | 0 | 0 |
T3 | 6 | 6 | 0 | 0 |
T4 | 6 | 6 | 0 | 0 |
T5 | 6 | 6 | 0 | 0 |
T8 | 6 | 6 | 0 | 0 |
T24 | 6 | 6 | 0 | 0 |
T29 | 6 | 6 | 0 | 0 |
T30 | 6 | 6 | 0 | 0 |
T31 | 6 | 6 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 273967005 | 273581367 | 0 | 0 |
T1 | 4154286 | 4151154 | 0 | 0 |
T2 | 682290 | 681810 | 0 | 0 |
T3 | 2740938 | 2738598 | 0 | 0 |
T4 | 2832066 | 2830440 | 0 | 0 |
T5 | 400698 | 399180 | 0 | 0 |
T8 | 63792 | 63480 | 0 | 0 |
T24 | 220422 | 218748 | 0 | 0 |
T29 | 37110 | 36768 | 0 | 0 |
T30 | 861048 | 860532 | 0 | 0 |
T31 | 10146 | 9690 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 137038986 | 136838949 | 0 | 2358 |
T1 | 2077143 | 2075514 | 0 | 9 |
T2 | 341145 | 340896 | 0 | 9 |
T3 | 1370469 | 1369245 | 0 | 9 |
T4 | 1416033 | 1415184 | 0 | 9 |
T5 | 200349 | 199554 | 0 | 9 |
T8 | 31896 | 31731 | 0 | 9 |
T24 | 110211 | 109338 | 0 | 9 |
T29 | 18555 | 18375 | 0 | 9 |
T30 | 430524 | 430257 | 0 | 9 |
T31 | 5073 | 4836 | 0 | 9 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 136928019 | 136735200 | 0 | 0 |
T1 | 2077143 | 2075577 | 0 | 0 |
T2 | 341145 | 340905 | 0 | 0 |
T3 | 1370469 | 1369299 | 0 | 0 |
T4 | 1416033 | 1415220 | 0 | 0 |
T5 | 200349 | 199590 | 0 | 0 |
T8 | 31896 | 31740 | 0 | 0 |
T24 | 110211 | 109374 | 0 | 0 |
T29 | 18555 | 18384 | 0 | 0 |
T30 | 430524 | 430266 | 0 | 0 |
T31 | 5073 | 4845 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 262 | 262 | 0 | 0 |
OutputsKnown_A | 45679662 | 45615389 | 0 | 0 |
gen_flops.OutputDelay_A | 45679662 | 45612983 | 0 | 786 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 262 | 262 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
T31 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 45679662 | 45615389 | 0 | 0 |
T1 | 692381 | 691859 | 0 | 0 |
T2 | 113715 | 113635 | 0 | 0 |
T3 | 456823 | 456433 | 0 | 0 |
T4 | 472011 | 471740 | 0 | 0 |
T5 | 66783 | 66530 | 0 | 0 |
T8 | 10632 | 10580 | 0 | 0 |
T24 | 36737 | 36458 | 0 | 0 |
T29 | 6185 | 6128 | 0 | 0 |
T30 | 143508 | 143422 | 0 | 0 |
T31 | 1691 | 1615 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 45679662 | 45612983 | 0 | 786 |
T1 | 692381 | 691838 | 0 | 3 |
T2 | 113715 | 113632 | 0 | 3 |
T3 | 456823 | 456415 | 0 | 3 |
T4 | 472011 | 471728 | 0 | 3 |
T5 | 66783 | 66518 | 0 | 3 |
T8 | 10632 | 10577 | 0 | 3 |
T24 | 36737 | 36446 | 0 | 3 |
T29 | 6185 | 6125 | 0 | 3 |
T30 | 143508 | 143419 | 0 | 3 |
T31 | 1691 | 1612 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 262 | 262 | 0 | 0 |
OutputsKnown_A | 45679662 | 45615389 | 0 | 0 |
gen_flops.OutputDelay_A | 45679662 | 45612983 | 0 | 786 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 262 | 262 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
T31 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 45679662 | 45615389 | 0 | 0 |
T1 | 692381 | 691859 | 0 | 0 |
T2 | 113715 | 113635 | 0 | 0 |
T3 | 456823 | 456433 | 0 | 0 |
T4 | 472011 | 471740 | 0 | 0 |
T5 | 66783 | 66530 | 0 | 0 |
T8 | 10632 | 10580 | 0 | 0 |
T24 | 36737 | 36458 | 0 | 0 |
T29 | 6185 | 6128 | 0 | 0 |
T30 | 143508 | 143422 | 0 | 0 |
T31 | 1691 | 1615 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 45679662 | 45612983 | 0 | 786 |
T1 | 692381 | 691838 | 0 | 3 |
T2 | 113715 | 113632 | 0 | 3 |
T3 | 456823 | 456415 | 0 | 3 |
T4 | 472011 | 471728 | 0 | 3 |
T5 | 66783 | 66518 | 0 | 3 |
T8 | 10632 | 10577 | 0 | 3 |
T24 | 36737 | 36446 | 0 | 3 |
T29 | 6185 | 6125 | 0 | 3 |
T30 | 143508 | 143419 | 0 | 3 |
T31 | 1691 | 1612 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 262 | 262 | 0 | 0 |
OutputsKnown_A | 45568695 | 45504422 | 0 | 0 |
gen_no_flops.OutputDelay_A | 45568695 | 45504422 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 262 | 262 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
T31 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 45568695 | 45504422 | 0 | 0 |
T1 | 692381 | 691859 | 0 | 0 |
T2 | 113715 | 113635 | 0 | 0 |
T3 | 456823 | 456433 | 0 | 0 |
T4 | 472011 | 471740 | 0 | 0 |
T5 | 66783 | 66530 | 0 | 0 |
T8 | 10632 | 10580 | 0 | 0 |
T24 | 36737 | 36458 | 0 | 0 |
T29 | 6185 | 6128 | 0 | 0 |
T30 | 143508 | 143422 | 0 | 0 |
T31 | 1691 | 1615 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 45568695 | 45504422 | 0 | 0 |
T1 | 692381 | 691859 | 0 | 0 |
T2 | 113715 | 113635 | 0 | 0 |
T3 | 456823 | 456433 | 0 | 0 |
T4 | 472011 | 471740 | 0 | 0 |
T5 | 66783 | 66530 | 0 | 0 |
T8 | 10632 | 10580 | 0 | 0 |
T24 | 36737 | 36458 | 0 | 0 |
T29 | 6185 | 6128 | 0 | 0 |
T30 | 143508 | 143422 | 0 | 0 |
T31 | 1691 | 1615 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 262 | 262 | 0 | 0 |
OutputsKnown_A | 45679662 | 45615389 | 0 | 0 |
gen_flops.OutputDelay_A | 45679662 | 45612983 | 0 | 786 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 262 | 262 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
T31 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 45679662 | 45615389 | 0 | 0 |
T1 | 692381 | 691859 | 0 | 0 |
T2 | 113715 | 113635 | 0 | 0 |
T3 | 456823 | 456433 | 0 | 0 |
T4 | 472011 | 471740 | 0 | 0 |
T5 | 66783 | 66530 | 0 | 0 |
T8 | 10632 | 10580 | 0 | 0 |
T24 | 36737 | 36458 | 0 | 0 |
T29 | 6185 | 6128 | 0 | 0 |
T30 | 143508 | 143422 | 0 | 0 |
T31 | 1691 | 1615 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 45679662 | 45612983 | 0 | 786 |
T1 | 692381 | 691838 | 0 | 3 |
T2 | 113715 | 113632 | 0 | 3 |
T3 | 456823 | 456415 | 0 | 3 |
T4 | 472011 | 471728 | 0 | 3 |
T5 | 66783 | 66518 | 0 | 3 |
T8 | 10632 | 10577 | 0 | 3 |
T24 | 36737 | 36446 | 0 | 3 |
T29 | 6185 | 6125 | 0 | 3 |
T30 | 143508 | 143419 | 0 | 3 |
T31 | 1691 | 1612 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 262 | 262 | 0 | 0 |
OutputsKnown_A | 45679662 | 45615389 | 0 | 0 |
gen_no_flops.OutputDelay_A | 45679662 | 45615389 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 262 | 262 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
T31 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 45679662 | 45615389 | 0 | 0 |
T1 | 692381 | 691859 | 0 | 0 |
T2 | 113715 | 113635 | 0 | 0 |
T3 | 456823 | 456433 | 0 | 0 |
T4 | 472011 | 471740 | 0 | 0 |
T5 | 66783 | 66530 | 0 | 0 |
T8 | 10632 | 10580 | 0 | 0 |
T24 | 36737 | 36458 | 0 | 0 |
T29 | 6185 | 6128 | 0 | 0 |
T30 | 143508 | 143422 | 0 | 0 |
T31 | 1691 | 1615 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 45679662 | 45615389 | 0 | 0 |
T1 | 692381 | 691859 | 0 | 0 |
T2 | 113715 | 113635 | 0 | 0 |
T3 | 456823 | 456433 | 0 | 0 |
T4 | 472011 | 471740 | 0 | 0 |
T5 | 66783 | 66530 | 0 | 0 |
T8 | 10632 | 10580 | 0 | 0 |
T24 | 36737 | 36458 | 0 | 0 |
T29 | 6185 | 6128 | 0 | 0 |
T30 | 143508 | 143422 | 0 | 0 |
T31 | 1691 | 1615 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 262 | 262 | 0 | 0 |
OutputsKnown_A | 45679662 | 45615389 | 0 | 0 |
gen_no_flops.OutputDelay_A | 45679662 | 45615389 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 262 | 262 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
T31 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 45679662 | 45615389 | 0 | 0 |
T1 | 692381 | 691859 | 0 | 0 |
T2 | 113715 | 113635 | 0 | 0 |
T3 | 456823 | 456433 | 0 | 0 |
T4 | 472011 | 471740 | 0 | 0 |
T5 | 66783 | 66530 | 0 | 0 |
T8 | 10632 | 10580 | 0 | 0 |
T24 | 36737 | 36458 | 0 | 0 |
T29 | 6185 | 6128 | 0 | 0 |
T30 | 143508 | 143422 | 0 | 0 |
T31 | 1691 | 1615 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 45679662 | 45615389 | 0 | 0 |
T1 | 692381 | 691859 | 0 | 0 |
T2 | 113715 | 113635 | 0 | 0 |
T3 | 456823 | 456433 | 0 | 0 |
T4 | 472011 | 471740 | 0 | 0 |
T5 | 66783 | 66530 | 0 | 0 |
T8 | 10632 | 10580 | 0 | 0 |
T24 | 36737 | 36458 | 0 | 0 |
T29 | 6185 | 6128 | 0 | 0 |
T30 | 143508 | 143422 | 0 | 0 |
T31 | 1691 | 1615 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |