Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	285177	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

624023

1

T2

4

T4

2

T7

80

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	526830	1			T2	3		T7	80		T14	2
values[0x0]	163143	1			T2	2		T4	2		T6	3
values[0x1]	219227	1			T2	4		T6	3		T5	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	190252	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

718948

1

T2

5

T4

2

T7

80

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3418	1			T15	46		T10	17		T45	2
valid_sources[0x01]	3792	1			T7	1		T15	39		T10	28
valid_sources[0x02]	4326	1			T15	42		T10	35		T45	1
valid_sources[0x03]	3344	1			T7	1		T15	45		T63	1
valid_sources[0x04]	2986	1			T7	2		T15	40		T10	76
valid_sources[0x05]	3602	1			T7	1		T15	41		T10	38
valid_sources[0x06]	3886	1			T15	48		T10	153		T22	63
valid_sources[0x07]	3181	1			T7	2		T20	1		T15	34
valid_sources[0x08]	3023	1			T15	39		T10	20		T45	28
valid_sources[0x09]	3651	1			T7	1		T28	5		T20	1
valid_sources[0x0a]	3053	1			T15	25		T10	22		T45	4
valid_sources[0x0b]	2883	1			T7	1		T15	33		T10	44
valid_sources[0x0c]	3352	1			T15	48		T10	28		T45	16
valid_sources[0x0d]	3895	1			T30	5		T15	32		T10	65
valid_sources[0x0e]	3703	1			T15	37		T10	31		T45	14
valid_sources[0x0f]	3442	1			T15	35		T10	25		T45	4
valid_sources[0x10]	3733	1			T15	39		T10	3		T45	22
valid_sources[0x11]	3553	1			T15	46		T10	16		T45	19
valid_sources[0x12]	4308	1			T15	40		T10	33		T22	67
valid_sources[0x13]	3095	1			T15	34		T10	142		T45	31
valid_sources[0x14]	3523	1			T15	35		T10	43		T45	10
valid_sources[0x15]	4105	1			T15	46		T10	26		T45	19
valid_sources[0x16]	3318	1			T15	47		T10	69		T45	21
valid_sources[0x17]	3552	1			T15	41		T10	24		T45	11
valid_sources[0x18]	3883	1			T15	37		T10	19		T45	27
valid_sources[0x19]	3141	1			T15	44		T10	16		T45	5
valid_sources[0x1a]	3157	1			T32	1		T15	42		T10	35
valid_sources[0x1b]	4082	1			T15	33		T10	50		T45	2
valid_sources[0x1c]	3319	1			T15	42		T10	12		T45	2
valid_sources[0x1d]	3238	1			T7	1		T15	34		T10	22
valid_sources[0x1e]	3020	1			T7	1		T15	38		T10	63
valid_sources[0x1f]	3055	1			T15	40		T10	17		T45	7
valid_sources[0x20]	4453	1			T15	51		T10	80		T45	8
valid_sources[0x21]	4244	1			T7	3		T15	42		T10	39
valid_sources[0x22]	3814	1			T15	39		T10	25		T45	18
valid_sources[0x23]	2987	1			T7	1		T15	27		T10	9
valid_sources[0x24]	3236	1			T15	48		T10	9		T45	14
valid_sources[0x25]	3252	1			T15	31		T63	1		T10	38
valid_sources[0x26]	3573	1			T15	42		T10	28		T45	5
valid_sources[0x27]	3463	1			T7	1		T15	41		T10	24
valid_sources[0x28]	3394	1			T15	27		T10	168		T45	22
valid_sources[0x29]	3382	1			T15	45		T10	131		T58	1
valid_sources[0x2a]	3824	1			T15	31		T10	178		T45	27
valid_sources[0x2b]	3219	1			T7	1		T15	32		T10	44
valid_sources[0x2c]	3322	1			T15	46		T10	42		T45	15
valid_sources[0x2d]	3474	1			T7	1		T15	45		T10	15
valid_sources[0x2e]	3847	1			T15	50		T10	85		T45	30
valid_sources[0x2f]	4186	1			T15	30		T10	68		T45	7
valid_sources[0x30]	3435	1			T14	1		T15	40		T10	20
valid_sources[0x31]	3479	1			T7	1		T15	48		T10	15
valid_sources[0x32]	3413	1			T7	3		T15	40		T10	28
valid_sources[0x33]	4293	1			T15	43		T10	23		T45	1
valid_sources[0x34]	3658	1			T41	1		T15	33		T10	43
valid_sources[0x35]	3493	1			T15	43		T10	24		T45	6
valid_sources[0x36]	3074	1			T15	35		T10	19		T45	7
valid_sources[0x37]	3433	1			T15	39		T10	11		T45	20
valid_sources[0x38]	3211	1			T15	28		T10	15		T45	27
valid_sources[0x39]	3572	1			T15	46		T10	36		T22	45
valid_sources[0x3a]	3874	1			T15	52		T10	225		T45	11
valid_sources[0x3b]	3463	1			T7	2		T15	40		T10	15
valid_sources[0x3c]	4211	1			T15	30		T10	38		T45	21
valid_sources[0x3d]	4350	1			T7	1		T15	41		T10	23
valid_sources[0x3e]	3661	1			T42	1		T15	44		T10	26
valid_sources[0x3f]	3508	1			T15	36		T10	45		T45	11
valid_sources[0x40]	3216	1			T15	44		T10	7		T45	9
valid_sources[0x41]	3265	1			T7	1		T15	38		T10	86
valid_sources[0x42]	3247	1			T15	40		T10	55		T45	11
valid_sources[0x43]	3347	1			T15	24		T10	65		T45	4
valid_sources[0x44]	3859	1			T41	1		T15	30		T10	25
valid_sources[0x45]	3403	1			T15	47		T10	45		T22	47
valid_sources[0x46]	3176	1			T15	52		T10	43		T22	60
valid_sources[0x47]	3433	1			T7	1		T15	50		T10	15
valid_sources[0x48]	3657	1			T7	3		T15	28		T10	19
valid_sources[0x49]	3652	1			T15	39		T10	11		T22	45
valid_sources[0x4a]	3592	1			T15	32		T10	52		T45	46
valid_sources[0x4b]	3472	1			T15	40		T10	64		T45	22
valid_sources[0x4c]	3530	1			T15	37		T10	14		T45	22
valid_sources[0x4d]	4174	1			T14	1		T28	1		T15	35
valid_sources[0x4e]	2917	1			T7	1		T15	53		T10	21
valid_sources[0x4f]	3446	1			T7	1		T15	33		T10	28
valid_sources[0x50]	3707	1			T7	2		T15	43		T10	41
valid_sources[0x51]	3622	1			T15	51		T10	56		T45	9
valid_sources[0x52]	3285	1			T7	1		T15	39		T10	33
valid_sources[0x53]	3604	1			T28	1		T15	32		T10	6
valid_sources[0x54]	3724	1			T15	43		T10	24		T45	21
valid_sources[0x55]	3732	1			T15	23		T10	4		T45	10
valid_sources[0x56]	3139	1			T15	40		T10	32		T45	3
valid_sources[0x57]	3537	1			T15	42		T10	35		T45	11
valid_sources[0x58]	3169	1			T42	4		T15	27		T10	29
valid_sources[0x59]	2855	1			T15	34		T10	25		T45	19
valid_sources[0x5a]	3290	1			T15	30		T10	9		T45	19
valid_sources[0x5b]	3468	1			T20	5		T15	33		T10	22
valid_sources[0x5c]	3665	1			T15	30		T10	16		T45	27
valid_sources[0x5d]	3538	1			T15	41		T10	5		T45	38
valid_sources[0x5e]	3382	1			T15	47		T10	157		T45	7
valid_sources[0x5f]	3487	1			T15	41		T10	10		T45	2
valid_sources[0x60]	3673	1			T15	42		T10	36		T45	4
valid_sources[0x61]	3654	1			T15	36		T10	31		T45	42
valid_sources[0x62]	3917	1			T15	36		T10	11		T45	1
valid_sources[0x63]	3605	1			T7	1		T15	43		T10	23
valid_sources[0x64]	3839	1			T15	40		T10	7		T45	2
valid_sources[0x65]	2927	1			T2	1		T15	30		T63	1
valid_sources[0x66]	4440	1			T2	1		T7	2		T15	40
valid_sources[0x67]	3999	1			T15	40		T10	32		T45	13
valid_sources[0x68]	3097	1			T15	39		T10	21		T45	3
valid_sources[0x69]	3210	1			T15	36		T10	20		T45	4
valid_sources[0x6a]	3509	1			T15	28		T10	17		T45	11
valid_sources[0x6b]	4613	1			T15	36		T10	58		T45	9
valid_sources[0x6c]	3436	1			T15	35		T10	2		T45	17
valid_sources[0x6d]	3470	1			T15	46		T10	37		T22	56
valid_sources[0x6e]	2903	1			T7	1		T15	42		T10	31
valid_sources[0x6f]	3572	1			T28	2		T15	30		T10	28
valid_sources[0x70]	3566	1			T7	1		T15	38		T10	17
valid_sources[0x71]	4049	1			T15	28		T10	160		T45	2
valid_sources[0x72]	3591	1			T15	36		T10	62		T22	57
valid_sources[0x73]	3232	1			T15	46		T63	1		T10	16
valid_sources[0x74]	3821	1			T15	30		T10	80		T45	5
valid_sources[0x75]	3048	1			T15	48		T10	72		T45	7
valid_sources[0x76]	3762	1			T41	1		T15	38		T10	17
valid_sources[0x77]	3196	1			T15	37		T10	47		T45	2
valid_sources[0x78]	3186	1			T15	47		T10	7		T22	55
valid_sources[0x79]	3846	1			T15	43		T10	37		T45	20
valid_sources[0x7a]	3204	1			T7	1		T15	42		T10	12
valid_sources[0x7b]	3620	1			T7	1		T15	33		T10	74
valid_sources[0x7c]	3596	1			T15	32		T10	7		T45	16
valid_sources[0x7d]	3363	1			T15	44		T10	6		T45	3
valid_sources[0x7e]	3644	1			T15	27		T10	66		T45	23
valid_sources[0x7f]	3137	1			T15	32		T10	83		T45	15
valid_sources[0x80]	3706	1			T7	1		T15	35		T10	37

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

313921

1

T2

1

T7

80

T14

1

values[0x0]

all_enables

biggest_size

155741

1

T2

2

T4

2

T6

1

values[0x1]

all_enables

biggest_size

154361

1

T2

1

T6

1

T30

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8476	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

112447

1

T1

5

T2

7

T3

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	33688	1			T15	1573		T10	1068		T45	322
values[0x0]	42488	1			T1	3		T2	4		T3	5
values[0x1]	44747	1			T1	2		T2	3		T3	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5626	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

115297

1

T1

5

T2

7

T3

4

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	742	1			T27	1		T15	19		T10	19
valid_sources[0x01]	569	1			T5	1		T15	33		T10	18
valid_sources[0x02]	496	1			T15	28		T10	22		T22	30
valid_sources[0x03]	660	1			T27	1		T15	30		T10	9
valid_sources[0x04]	362	1			T15	20		T10	20		T22	42
valid_sources[0x05]	380	1			T15	29		T10	16		T22	48
valid_sources[0x06]	412	1			T15	14		T10	25		T45	2
valid_sources[0x07]	578	1			T15	16		T10	12		T22	37
valid_sources[0x08]	473	1			T15	35		T10	30		T31	1
valid_sources[0x09]	458	1			T38	1		T15	29		T10	13
valid_sources[0x0a]	379	1			T4	1		T15	31		T10	16
valid_sources[0x0b]	444	1			T15	21		T10	22		T45	50
valid_sources[0x0c]	962	1			T15	17		T10	13		T45	142
valid_sources[0x0d]	400	1			T15	20		T10	12		T22	33
valid_sources[0x0e]	617	1			T15	21		T10	25		T22	37
valid_sources[0x0f]	384	1			T29	1		T15	23		T10	16
valid_sources[0x10]	383	1			T30	1		T15	35		T10	21
valid_sources[0x11]	785	1			T30	1		T15	26		T10	20
valid_sources[0x12]	372	1			T15	27		T10	7		T22	28
valid_sources[0x13]	512	1			T15	25		T34	1		T10	20
valid_sources[0x14]	425	1			T15	25		T10	19		T22	33
valid_sources[0x15]	407	1			T15	24		T10	19		T22	50
valid_sources[0x16]	432	1			T15	19		T10	17		T22	40
valid_sources[0x17]	455	1			T15	15		T10	22		T45	70
valid_sources[0x18]	404	1			T15	16		T10	18		T183	1
valid_sources[0x19]	424	1			T15	25		T10	15		T45	1
valid_sources[0x1a]	428	1			T15	24		T10	9		T22	44
valid_sources[0x1b]	547	1			T15	27		T10	16		T22	32
valid_sources[0x1c]	381	1			T15	24		T10	18		T22	33
valid_sources[0x1d]	333	1			T15	15		T10	9		T22	40
valid_sources[0x1e]	495	1			T3	1		T15	24		T10	19
valid_sources[0x1f]	695	1			T15	27		T10	13		T22	37
valid_sources[0x20]	450	1			T2	1		T15	28		T10	19
valid_sources[0x21]	379	1			T15	24		T33	1		T10	12
valid_sources[0x22]	396	1			T15	27		T10	12		T45	20
valid_sources[0x23]	364	1			T15	18		T10	17		T22	49
valid_sources[0x24]	372	1			T15	19		T10	21		T22	46
valid_sources[0x25]	593	1			T15	21		T10	20		T65	1
valid_sources[0x26]	406	1			T15	17		T10	9		T45	18
valid_sources[0x27]	630	1			T5	1		T15	29		T10	14
valid_sources[0x28]	399	1			T15	32		T10	12		T184	1
valid_sources[0x29]	787	1			T13	1		T15	28		T10	14
valid_sources[0x2a]	389	1			T15	25		T10	14		T145	1
valid_sources[0x2b]	409	1			T15	22		T10	22		T185	1
valid_sources[0x2c]	395	1			T4	1		T15	30		T10	17
valid_sources[0x2d]	430	1			T15	30		T10	16		T22	43
valid_sources[0x2e]	356	1			T15	26		T10	26		T22	37
valid_sources[0x2f]	371	1			T15	31		T10	15		T31	1
valid_sources[0x30]	392	1			T15	14		T10	18		T22	28
valid_sources[0x31]	390	1			T15	16		T10	14		T45	3
valid_sources[0x32]	491	1			T15	28		T10	14		T22	39
valid_sources[0x33]	393	1			T15	15		T33	1		T10	12
valid_sources[0x34]	610	1			T15	25		T10	19		T45	70
valid_sources[0x35]	451	1			T41	1		T15	21		T10	10
valid_sources[0x36]	656	1			T15	42		T10	12		T22	43
valid_sources[0x37]	454	1			T15	31		T10	14		T22	37
valid_sources[0x38]	403	1			T15	26		T10	19		T31	1
valid_sources[0x39]	567	1			T15	34		T10	12		T145	1
valid_sources[0x3a]	386	1			T15	22		T10	8		T22	38
valid_sources[0x3b]	341	1			T7	1		T15	18		T10	18
valid_sources[0x3c]	510	1			T15	15		T10	19		T22	40
valid_sources[0x3d]	468	1			T4	1		T15	24		T10	21
valid_sources[0x3e]	388	1			T15	26		T10	24		T184	1
valid_sources[0x3f]	420	1			T27	1		T15	27		T10	12
valid_sources[0x40]	427	1			T32	1		T15	18		T10	25
valid_sources[0x41]	646	1			T15	20		T10	26		T22	43
valid_sources[0x42]	515	1			T15	20		T25	9		T10	13
valid_sources[0x43]	455	1			T15	21		T10	25		T22	42
valid_sources[0x44]	410	1			T15	28		T10	16		T22	48
valid_sources[0x45]	694	1			T15	25		T10	14		T22	39
valid_sources[0x46]	470	1			T15	22		T33	1		T10	9
valid_sources[0x47]	455	1			T30	2		T15	24		T10	16
valid_sources[0x48]	384	1			T15	28		T10	15		T22	37
valid_sources[0x49]	377	1			T15	34		T10	15		T22	34
valid_sources[0x4a]	455	1			T15	32		T10	14		T22	38
valid_sources[0x4b]	546	1			T26	1		T15	28		T10	17
valid_sources[0x4c]	396	1			T15	21		T10	17		T22	25
valid_sources[0x4d]	449	1			T15	22		T10	19		T186	1
valid_sources[0x4e]	453	1			T30	1		T27	1		T15	23
valid_sources[0x4f]	608	1			T3	1		T15	16		T10	27
valid_sources[0x50]	601	1			T15	20		T10	16		T22	31
valid_sources[0x51]	360	1			T15	20		T10	21		T45	1
valid_sources[0x52]	757	1			T2	2		T15	13		T10	19
valid_sources[0x53]	467	1			T27	1		T15	32		T10	28
valid_sources[0x54]	585	1			T6	1		T15	27		T10	15
valid_sources[0x55]	401	1			T15	20		T10	16		T22	40
valid_sources[0x56]	713	1			T5	1		T27	2		T15	30
valid_sources[0x57]	414	1			T15	45		T10	13		T22	49
valid_sources[0x58]	546	1			T15	34		T34	2		T10	11
valid_sources[0x59]	364	1			T15	24		T10	17		T22	24
valid_sources[0x5a]	552	1			T15	24		T10	19		T22	35
valid_sources[0x5b]	483	1			T3	1		T6	1		T15	19
valid_sources[0x5c]	416	1			T15	21		T10	12		T22	39
valid_sources[0x5d]	394	1			T15	20		T10	10		T186	1
valid_sources[0x5e]	733	1			T15	32		T10	9		T66	1
valid_sources[0x5f]	926	1			T15	21		T10	19		T22	45
valid_sources[0x60]	470	1			T15	17		T10	16		T22	39
valid_sources[0x61]	467	1			T15	16		T10	24		T145	1
valid_sources[0x62]	435	1			T15	7		T10	16		T45	4
valid_sources[0x63]	454	1			T15	15		T10	23		T22	35
valid_sources[0x64]	395	1			T15	18		T10	23		T45	3
valid_sources[0x65]	368	1			T15	24		T33	1		T10	10
valid_sources[0x66]	419	1			T15	36		T10	16		T22	47
valid_sources[0x67]	448	1			T15	18		T10	18		T22	44
valid_sources[0x68]	390	1			T15	17		T10	16		T22	34
valid_sources[0x69]	391	1			T5	1		T15	16		T10	8
valid_sources[0x6a]	375	1			T15	24		T10	16		T22	30
valid_sources[0x6b]	481	1			T15	37		T10	12		T187	1
valid_sources[0x6c]	592	1			T15	33		T10	10		T65	1
valid_sources[0x6d]	395	1			T15	23		T10	11		T22	41
valid_sources[0x6e]	387	1			T15	37		T10	11		T45	6
valid_sources[0x6f]	420	1			T15	26		T10	20		T22	35
valid_sources[0x70]	599	1			T2	1		T15	36		T10	16
valid_sources[0x71]	475	1			T15	34		T10	16		T31	1
valid_sources[0x72]	502	1			T28	1		T15	19		T10	23
valid_sources[0x73]	453	1			T15	29		T10	18		T22	31
valid_sources[0x74]	373	1			T15	18		T10	14		T22	32
valid_sources[0x75]	401	1			T28	1		T15	24		T10	9
valid_sources[0x76]	436	1			T15	22		T10	10		T22	34
valid_sources[0x77]	424	1			T15	19		T10	31		T187	2
valid_sources[0x78]	664	1			T15	16		T10	24		T22	40
valid_sources[0x79]	454	1			T15	17		T10	16		T22	38
valid_sources[0x7a]	358	1			T27	1		T15	24		T10	12
valid_sources[0x7b]	379	1			T15	14		T33	1		T10	20
valid_sources[0x7c]	399	1			T14	1		T15	26		T10	8
valid_sources[0x7d]	460	1			T15	34		T10	8		T45	2
valid_sources[0x7e]	485	1			T15	22		T10	24		T22	43
valid_sources[0x7f]	370	1			T15	20		T10	21		T22	32
valid_sources[0x80]	650	1			T15	24		T10	10		T22	42

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29573

1

T15

1457

T10

983

T45

300

values[0x0]

all_enables

biggest_size

41383

1

T1

3

T2

4

T3

2

values[0x1]

all_enables

biggest_size

41491

1

T1

2

T2

3

T4

3