Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

733381

1

T2

5

T6

4

T5

2

full_word

639948

1

T2

4

T4

2

T7

80

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	1373009	1			T2	9		T4	2		T7	80
auto[TlIntgErrCmd]	100	1			T147	1		T148	6		T142	7
auto[TlIntgErrData]	112	1			T147	2		T148	8		T142	4
auto[TlIntgErrBoth]	108	1			T147	7		T148	6		T142	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

546540

1

T2

3

T7

80

T30

2

auto[1]

826789

1

T2

6

T4

2

T6

6

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	230625	1			T2	2		T30	1		T28	2
auto[TlIntgErrNone]	partial	auto[1]	502467	1			T2	3		T6	4		T5	2
auto[TlIntgErrNone]	full_word	auto[0]	315780	1			T2	1		T7	80		T30	1
auto[TlIntgErrNone]	full_word	auto[1]	324137	1			T2	3		T4	2		T6	2
auto[TlIntgErrCmd]	partial	auto[0]	39	1			T148	2		T142	4		T172	3
auto[TlIntgErrCmd]	partial	auto[1]	50	1			T148	4		T142	3		T172	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T177	1		T178	1		T179	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T147	1		T172	2		T180	1
auto[TlIntgErrData]	partial	auto[0]	46	1			T148	5		T142	2		T172	2
auto[TlIntgErrData]	partial	auto[1]	55	1			T147	2		T148	3		T142	2
auto[TlIntgErrData]	full_word	auto[0]	5	1			T176	1		T173	1		T177	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T172	2		T173	1		T178	1
auto[TlIntgErrBoth]	partial	auto[0]	39	1			T147	2		T148	3		T142	5
auto[TlIntgErrBoth]	partial	auto[1]	60	1			T147	4		T148	2		T142	4
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T148	1		T173	1		T178	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T147	1		T181	1		T182	1