Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.66	100.00	85.71	97.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	114528963	140259	0	0
late_debug_enable_rd_A	114528963	10537	0	0
late_debug_enable_regwen_rd_A	114528963	9834	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114528963	140259	0	0
T10	386297	5965	0	0
T15	290145	9351	0	0
T21	0	13519	0	0
T22	0	11785	0	0
T25	37311	0	0	0
T33	3618	0	0	0
T34	1588	0	0	0
T35	46639	0	0	0
T45	0	1702	0	0
T54	0	2378	0	0
T63	187486	0	0	0
T64	3443	0	0	0
T65	104809	0	0	0
T89	0	11488	0	0
T92	0	2418	0	0
T93	0	321	0	0
T97	0	13295	0	0
T102	70548	0	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114528963	10537	0	0
T8	225857	0	0	0
T10	386297	2105	0	0
T22	0	3968	0	0
T36	73146	0	0	0
T45	0	379	0	0
T58	50758	0	0	0
T65	104809	0	0	0
T66	245712	0	0	0
T67	20806	0	0	0
T68	70794	0	0	0
T92	0	423	0	0
T93	0	234	0	0
T95	0	10	0	0
T141	0	146	0	0
T142	0	27	0	0
T143	0	174	0	0
T144	0	51	0	0
T145	127523	0	0	0
T146	2398	0	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114528963	9834	0	0
T8	225857	0	0	0
T10	386297	1692	0	0
T22	0	3444	0	0
T36	73146	0	0	0
T45	0	308	0	0
T58	50758	0	0	0
T65	104809	0	0	0
T66	245712	0	0	0
T67	20806	0	0	0
T68	70794	0	0	0
T92	0	491	0	0
T93	0	207	0	0
T95	0	17	0	0
T103	0	2	0	0
T141	0	81	0	0
T142	0	38	0	0
T143	0	173	0	0
T145	127523	0	0	0
T146	2398	0	0	0