Line Coverage for Module :
prim_generic_clock_mux2
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Module :
prim_generic_clock_mux2
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T85 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T85 |
1 | 1 | Covered | T85 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T85 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Module :
prim_generic_clock_mux2
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
8016664 |
8015172 |
0 |
0 |
selKnown1 |
51106978 |
51105486 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8016664 |
8015172 |
0 |
0 |
T1 |
25988 |
25984 |
0 |
0 |
T2 |
10467 |
10463 |
0 |
0 |
T3 |
238 |
234 |
0 |
0 |
T4 |
23104 |
23100 |
0 |
0 |
T5 |
0 |
12 |
0 |
0 |
T6 |
21772 |
21768 |
0 |
0 |
T7 |
274 |
270 |
0 |
0 |
T13 |
30016 |
30012 |
0 |
0 |
T14 |
1084 |
1080 |
0 |
0 |
T20 |
0 |
8 |
0 |
0 |
T26 |
31584 |
31580 |
0 |
0 |
T27 |
0 |
22 |
0 |
0 |
T28 |
0 |
14 |
0 |
0 |
T29 |
644 |
640 |
0 |
0 |
T30 |
0 |
13 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
51106978 |
51105486 |
0 |
0 |
T1 |
564403 |
564399 |
0 |
0 |
T2 |
75109 |
75105 |
0 |
0 |
T3 |
9895 |
9891 |
0 |
0 |
T4 |
184795 |
184791 |
0 |
0 |
T5 |
0 |
4 |
0 |
0 |
T6 |
196614 |
196610 |
0 |
0 |
T7 |
8332 |
8328 |
0 |
0 |
T13 |
201513 |
201509 |
0 |
0 |
T14 |
6303 |
6299 |
0 |
0 |
T20 |
0 |
8 |
0 |
0 |
T26 |
665843 |
665839 |
0 |
0 |
T27 |
0 |
22 |
0 |
0 |
T28 |
0 |
14 |
0 |
0 |
T29 |
6255 |
6251 |
0 |
0 |
T30 |
0 |
12 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T85 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T85 |
1 | 1 | Covered | T85 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T85 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
2652350 |
2652087 |
0 |
0 |
selKnown1 |
45742798 |
45742535 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2652350 |
2652087 |
0 |
0 |
T1 |
12989 |
12988 |
0 |
0 |
T2 |
5227 |
5226 |
0 |
0 |
T3 |
118 |
117 |
0 |
0 |
T4 |
11545 |
11544 |
0 |
0 |
T6 |
10883 |
10882 |
0 |
0 |
T7 |
136 |
135 |
0 |
0 |
T13 |
15007 |
15006 |
0 |
0 |
T14 |
541 |
540 |
0 |
0 |
T26 |
15790 |
15789 |
0 |
0 |
T29 |
321 |
320 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
45742798 |
45742535 |
0 |
0 |
T1 |
551404 |
551403 |
0 |
0 |
T2 |
69872 |
69871 |
0 |
0 |
T3 |
9775 |
9774 |
0 |
0 |
T4 |
173240 |
173239 |
0 |
0 |
T6 |
185725 |
185724 |
0 |
0 |
T7 |
8194 |
8193 |
0 |
0 |
T13 |
186504 |
186503 |
0 |
0 |
T14 |
5760 |
5759 |
0 |
0 |
T26 |
650049 |
650048 |
0 |
0 |
T29 |
5932 |
5931 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T85 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T85 |
1 | 1 | Covered | T85 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T85 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
862 |
599 |
0 |
0 |
T1 |
5 |
4 |
0 |
0 |
T2 |
6 |
5 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
7 |
6 |
0 |
0 |
T5 |
0 |
5 |
0 |
0 |
T6 |
3 |
2 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
1 |
0 |
0 |
0 |
T20 |
0 |
4 |
0 |
0 |
T26 |
2 |
1 |
0 |
0 |
T27 |
0 |
11 |
0 |
0 |
T28 |
0 |
7 |
0 |
0 |
T29 |
1 |
0 |
0 |
0 |
T30 |
0 |
6 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
802 |
539 |
0 |
0 |
T1 |
5 |
4 |
0 |
0 |
T2 |
5 |
4 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
5 |
4 |
0 |
0 |
T5 |
0 |
2 |
0 |
0 |
T6 |
3 |
2 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
1 |
0 |
0 |
0 |
T20 |
0 |
4 |
0 |
0 |
T26 |
2 |
1 |
0 |
0 |
T27 |
0 |
11 |
0 |
0 |
T28 |
0 |
7 |
0 |
0 |
T29 |
1 |
0 |
0 |
0 |
T30 |
0 |
6 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T85 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T85 |
1 | 1 | Covered | T85 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T85 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
5361596 |
5361113 |
0 |
0 |
selKnown1 |
5361596 |
5361113 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
5361596 |
5361113 |
0 |
0 |
T1 |
12989 |
12988 |
0 |
0 |
T2 |
5227 |
5226 |
0 |
0 |
T3 |
118 |
117 |
0 |
0 |
T4 |
11545 |
11544 |
0 |
0 |
T6 |
10883 |
10882 |
0 |
0 |
T7 |
136 |
135 |
0 |
0 |
T13 |
15007 |
15006 |
0 |
0 |
T14 |
541 |
540 |
0 |
0 |
T26 |
15790 |
15789 |
0 |
0 |
T29 |
321 |
320 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
5361596 |
5361113 |
0 |
0 |
T1 |
12989 |
12988 |
0 |
0 |
T2 |
5227 |
5226 |
0 |
0 |
T3 |
118 |
117 |
0 |
0 |
T4 |
11545 |
11544 |
0 |
0 |
T6 |
10883 |
10882 |
0 |
0 |
T7 |
136 |
135 |
0 |
0 |
T13 |
15007 |
15006 |
0 |
0 |
T14 |
541 |
540 |
0 |
0 |
T26 |
15790 |
15789 |
0 |
0 |
T29 |
321 |
320 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T85 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T85 |
1 | 1 | Covered | T85 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T85 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
1856 |
1373 |
0 |
0 |
selKnown1 |
1782 |
1299 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1856 |
1373 |
0 |
0 |
T1 |
5 |
4 |
0 |
0 |
T2 |
7 |
6 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
7 |
6 |
0 |
0 |
T5 |
0 |
7 |
0 |
0 |
T6 |
3 |
2 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
1 |
0 |
0 |
0 |
T20 |
0 |
4 |
0 |
0 |
T26 |
2 |
1 |
0 |
0 |
T27 |
0 |
11 |
0 |
0 |
T28 |
0 |
7 |
0 |
0 |
T29 |
1 |
0 |
0 |
0 |
T30 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1782 |
1299 |
0 |
0 |
T1 |
5 |
4 |
0 |
0 |
T2 |
5 |
4 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
5 |
4 |
0 |
0 |
T5 |
0 |
2 |
0 |
0 |
T6 |
3 |
2 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
1 |
0 |
0 |
0 |
T20 |
0 |
4 |
0 |
0 |
T26 |
2 |
1 |
0 |
0 |
T27 |
0 |
11 |
0 |
0 |
T28 |
0 |
7 |
0 |
0 |
T29 |
1 |
0 |
0 |
0 |
T30 |
0 |
6 |
0 |
0 |