Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : rv_dm_regs_reg_top
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm_regs_reg_top.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg_regs 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg_regs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.32 98.69 99.35 93.55 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.66 100.00 85.71 97.60 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_alert_test 100.00 100.00
u_chk 97.78 100.00 93.33 100.00
u_late_debug_enable 100.00 100.00 100.00 100.00
u_late_debug_enable_regwen 100.00 100.00 100.00 100.00
u_prim_reg_we_check 100.00 100.00 100.00
u_reg_if 98.97 97.14 98.75 100.00 100.00
u_rsp_intg_gen 100.00 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : rv_dm_regs_reg_top
Line No.TotalCoveredPercent
TOTAL3535100.00
ALWAYS6744100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN11711100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN13611100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN18411100.00
ALWAYS21544100.00
CONT_ASSIGN22111100.00
ALWAYS22511100.00
CONT_ASSIGN23211100.00
CONT_ASSIGN23411100.00
CONT_ASSIGN23511100.00
CONT_ASSIGN23711100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24011100.00
ALWAYS24444100.00
ALWAYS25255100.00
CONT_ASSIGN27700
CONT_ASSIGN28511100.00
CONT_ASSIGN28611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm_regs_reg_top.sv' or '../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm_regs_reg_top.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
67 1 1
68 1 1
69 1 1
70 1 1
MISSING_ELSE
76 1 1
88 1 1
89 1 1
117 1 1
118 1 1
136 1 1
150 1 1
184 1 1
215 1 1
216 1 1
217 1 1
218 1 1
221 1 1
225 1 1
232 1 1
234 1 1
235 1 1
237 1 1
238 1 1
240 1 1
244 1 1
245 1 1
246 1 1
247 1 1
252 1 1
253 1 1
255 1 1
259 1 1
263 1 1
277 unreachable
285 1 1
286 1 1


Cond Coverage for Module : rv_dm_regs_reg_top
TotalCoveredPercent
Conditions5656100.00
Logical5656100.00
Non-Logical00
Event00

 LINE       57
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT15,T10,T45
11CoveredT1,T2,T3

 LINE       69
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT35,T36,T37
10CoveredT147,T148,T142

 LINE       76
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT35,T36,T37
010CoveredT147,T148,T142
100CoveredT35,T36,T37

 LINE       118
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT147,T148,T142
010CoveredT15,T10,T45
100CoveredT15,T10,T45

 LINE       184
 EXPRESSION (late_debug_enable_we & late_debug_enable_regwen_qs)
             ----------1---------   -------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT103,T104,T105
11CoveredT1,T2,T4

 LINE       216
 EXPRESSION (reg_addr == rv_dm_reg_pkg::RV_DM_ALERT_TEST_OFFSET)
            --------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T6

 LINE       217
 EXPRESSION (reg_addr == rv_dm_reg_pkg::RV_DM_LATE_DEBUG_ENABLE_REGWEN_OFFSET)
            ---------------------------------1--------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T6

 LINE       218
 EXPRESSION (reg_addr == rv_dm_reg_pkg::RV_DM_LATE_DEBUG_ENABLE_OFFSET)
            -----------------------------1-----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       221
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       221
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT15,T10,T45

 LINE       225
 EXPRESSION (reg_we & ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1111 & (~reg_be)))))))
             ---1--   ----------------------------------------------------------------2---------------------------------------------------------------
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT15,T10,T45

 LINE       225
 SUB-EXPRESSION ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1111 & (~reg_be))))))
                 -------------------1-------------------   -------------------2-------------------   ---------------------3--------------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT2,T3,T6
010CoveredT2,T6,T26
100CoveredT2,T3,T6

 LINE       225
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       225
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT2,T3,T26
11CoveredT2,T6,T26

 LINE       225
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT2,T3,T6

 LINE       232
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T4
101CoveredT2,T3,T6
110CoveredT15,T10,T45
111CoveredT3,T33,T34

 LINE       235
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT2,T3,T6
110CoveredT15,T10,T45
111CoveredT147,T103,T104

 LINE       238
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT3,T33,T34
101CoveredT1,T2,T3
110CoveredT15,T10,T45
111CoveredT1,T2,T4

Branch Coverage for Module : rv_dm_regs_reg_top
Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 221 2 2 100.00
IF 67 3 3 100.00
CASE 253 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm_regs_reg_top.sv' or '../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm_regs_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 221 ((reg_re || reg_we)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 67 if ((!rst_ni)) -2-: 69 if ((intg_err || reg_we_err))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T35,T36,T37
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 253 case (1'b1)

Branches:
-1-StatusTests
addr_hit[0] Covered T1,T2,T3
addr_hit[1] Covered T1,T2,T3
addr_hit[2] Covered T1,T2,T3
default Covered T1,T2,T3


Assert Coverage for Module : rv_dm_regs_reg_top
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
en2addrHit 114528963 13644 0 0
reAfterRv 114528963 13644 0 0
rePulse 114528963 7166 0 0
wePulse 114528963 6478 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 114528963 13644 0 0
T1 551404 5 0 0
T2 69872 7 0 0
T3 9775 10 0 0
T4 173240 8 0 0
T6 185725 7 0 0
T7 8194 1 0 0
T13 186504 1 0 0
T14 5760 1 0 0
T26 650049 2 0 0
T29 5932 1 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 114528963 13644 0 0
T1 551404 5 0 0
T2 69872 7 0 0
T3 9775 10 0 0
T4 173240 8 0 0
T6 185725 7 0 0
T7 8194 1 0 0
T13 186504 1 0 0
T14 5760 1 0 0
T26 650049 2 0 0
T29 5932 1 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 114528963 7166 0 0
T10 386297 105 0 0
T15 290145 121 0 0
T21 0 182 0 0
T22 0 155 0 0
T25 37311 0 0 0
T33 3618 0 0 0
T34 1588 0 0 0
T35 46639 0 0 0
T45 0 28 0 0
T54 0 52 0 0
T63 187486 0 0 0
T64 3443 0 0 0
T65 104809 0 0 0
T89 0 143 0 0
T92 0 49 0 0
T93 0 15 0 0
T97 0 164 0 0
T102 70548 0 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 114528963 6478 0 0
T1 551404 5 0 0
T2 69872 7 0 0
T3 9775 10 0 0
T4 173240 8 0 0
T6 185725 7 0 0
T7 8194 1 0 0
T13 186504 1 0 0
T14 5760 1 0 0
T26 650049 2 0 0
T29 5932 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%