SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_lc_sync_lc_hw_debug_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prim_lc_sync_lc_dft_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_en_sync_copies | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_pm_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.66 | 100.00 | 85.71 | 97.60 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.66 | 100.00 | 85.71 | 97.60 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.66 | 100.00 | 85.71 | 97.60 | 100.00 | 100.00 | dut |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.66 | 100.00 | 85.71 | 97.60 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
78.91 | 86.27 | 76.47 | 100.00 | 81.82 | 50.00 | u_tlul_lc_gate_sba |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
90.00 | 100.00 | 100.00 | 100.00 | 100.00 | 50.00 | u_tlul_lc_gate_rom |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1578 | 1578 | 0 | 0 |
OutputsKnown_A | 274333756 | 273968794 | 0 | 0 |
gen_flops.OutputDelay_A | 137228394 | 137038695 | 0 | 2367 |
gen_no_flops.OutputDelay_A | 137105362 | 136922881 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1578 | 1578 | 0 | 0 |
T1 | 6 | 6 | 0 | 0 |
T2 | 6 | 6 | 0 | 0 |
T3 | 6 | 6 | 0 | 0 |
T4 | 6 | 6 | 0 | 0 |
T6 | 6 | 6 | 0 | 0 |
T7 | 6 | 6 | 0 | 0 |
T13 | 6 | 6 | 0 | 0 |
T14 | 6 | 6 | 0 | 0 |
T26 | 6 | 6 | 0 | 0 |
T29 | 6 | 6 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 274333756 | 273968794 | 0 | 0 |
T1 | 3308424 | 3306600 | 0 | 0 |
T2 | 419232 | 417138 | 0 | 0 |
T3 | 58650 | 58230 | 0 | 0 |
T4 | 1039440 | 1037352 | 0 | 0 |
T6 | 1114350 | 1113078 | 0 | 0 |
T7 | 49164 | 48732 | 0 | 0 |
T13 | 1119024 | 1118604 | 0 | 0 |
T14 | 30511 | 30085 | 0 | 0 |
T26 | 3900294 | 3899358 | 0 | 0 |
T29 | 35592 | 35154 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 137228394 | 137038695 | 0 | 2367 |
T1 | 1654212 | 1653255 | 0 | 9 |
T2 | 209616 | 208524 | 0 | 9 |
T3 | 29325 | 29106 | 0 | 9 |
T4 | 519720 | 518631 | 0 | 9 |
T6 | 557175 | 556512 | 0 | 9 |
T7 | 24582 | 24357 | 0 | 9 |
T13 | 559512 | 559293 | 0 | 9 |
T14 | 17280 | 17058 | 0 | 9 |
T26 | 1950147 | 1949661 | 0 | 9 |
T29 | 17796 | 17568 | 0 | 9 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 137105362 | 136922881 | 0 | 0 |
T1 | 1654212 | 1653300 | 0 | 0 |
T2 | 209616 | 208569 | 0 | 0 |
T3 | 29325 | 29115 | 0 | 0 |
T4 | 519720 | 518676 | 0 | 0 |
T6 | 557175 | 556539 | 0 | 0 |
T7 | 24582 | 24366 | 0 | 0 |
T13 | 559512 | 559302 | 0 | 0 |
T14 | 13231 | 13018 | 0 | 0 |
T26 | 1950147 | 1949679 | 0 | 0 |
T29 | 17796 | 17577 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 263 | 263 | 0 | 0 |
OutputsKnown_A | 45742798 | 45681971 | 0 | 0 |
gen_flops.OutputDelay_A | 45742798 | 45679565 | 0 | 789 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 263 | 263 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T26 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 45742798 | 45681971 | 0 | 0 |
T1 | 551404 | 551100 | 0 | 0 |
T2 | 69872 | 69523 | 0 | 0 |
T3 | 9775 | 9705 | 0 | 0 |
T4 | 173240 | 172892 | 0 | 0 |
T6 | 185725 | 185513 | 0 | 0 |
T7 | 8194 | 8122 | 0 | 0 |
T13 | 186504 | 186434 | 0 | 0 |
T14 | 5760 | 5689 | 0 | 0 |
T26 | 650049 | 649893 | 0 | 0 |
T29 | 5932 | 5859 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 45742798 | 45679565 | 0 | 789 |
T1 | 551404 | 551085 | 0 | 3 |
T2 | 69872 | 69508 | 0 | 3 |
T3 | 9775 | 9702 | 0 | 3 |
T4 | 173240 | 172877 | 0 | 3 |
T6 | 185725 | 185504 | 0 | 3 |
T7 | 8194 | 8119 | 0 | 3 |
T13 | 186504 | 186431 | 0 | 3 |
T14 | 5760 | 5686 | 0 | 3 |
T26 | 650049 | 649887 | 0 | 3 |
T29 | 5932 | 5856 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 263 | 263 | 0 | 0 |
OutputsKnown_A | 45742798 | 45681971 | 0 | 0 |
gen_flops.OutputDelay_A | 45742798 | 45679565 | 0 | 789 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 263 | 263 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T26 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 45742798 | 45681971 | 0 | 0 |
T1 | 551404 | 551100 | 0 | 0 |
T2 | 69872 | 69523 | 0 | 0 |
T3 | 9775 | 9705 | 0 | 0 |
T4 | 173240 | 172892 | 0 | 0 |
T6 | 185725 | 185513 | 0 | 0 |
T7 | 8194 | 8122 | 0 | 0 |
T13 | 186504 | 186434 | 0 | 0 |
T14 | 5760 | 5689 | 0 | 0 |
T26 | 650049 | 649893 | 0 | 0 |
T29 | 5932 | 5859 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 45742798 | 45679565 | 0 | 789 |
T1 | 551404 | 551085 | 0 | 3 |
T2 | 69872 | 69508 | 0 | 3 |
T3 | 9775 | 9702 | 0 | 3 |
T4 | 173240 | 172877 | 0 | 3 |
T6 | 185725 | 185504 | 0 | 3 |
T7 | 8194 | 8119 | 0 | 3 |
T13 | 186504 | 186431 | 0 | 3 |
T14 | 5760 | 5686 | 0 | 3 |
T26 | 650049 | 649887 | 0 | 3 |
T29 | 5932 | 5856 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 263 | 263 | 0 | 0 |
OutputsKnown_A | 45619766 | 45558939 | 0 | 0 |
gen_no_flops.OutputDelay_A | 45619766 | 45558939 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 263 | 263 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T26 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 45619766 | 45558939 | 0 | 0 |
T1 | 551404 | 551100 | 0 | 0 |
T2 | 69872 | 69523 | 0 | 0 |
T3 | 9775 | 9705 | 0 | 0 |
T4 | 173240 | 172892 | 0 | 0 |
T6 | 185725 | 185513 | 0 | 0 |
T7 | 8194 | 8122 | 0 | 0 |
T13 | 186504 | 186434 | 0 | 0 |
T14 | 1711 | 1640 | 0 | 0 |
T26 | 650049 | 649893 | 0 | 0 |
T29 | 5932 | 5859 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 45619766 | 45558939 | 0 | 0 |
T1 | 551404 | 551100 | 0 | 0 |
T2 | 69872 | 69523 | 0 | 0 |
T3 | 9775 | 9705 | 0 | 0 |
T4 | 173240 | 172892 | 0 | 0 |
T6 | 185725 | 185513 | 0 | 0 |
T7 | 8194 | 8122 | 0 | 0 |
T13 | 186504 | 186434 | 0 | 0 |
T14 | 1711 | 1640 | 0 | 0 |
T26 | 650049 | 649893 | 0 | 0 |
T29 | 5932 | 5859 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 263 | 263 | 0 | 0 |
OutputsKnown_A | 45742798 | 45681971 | 0 | 0 |
gen_flops.OutputDelay_A | 45742798 | 45679565 | 0 | 789 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 263 | 263 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T26 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 45742798 | 45681971 | 0 | 0 |
T1 | 551404 | 551100 | 0 | 0 |
T2 | 69872 | 69523 | 0 | 0 |
T3 | 9775 | 9705 | 0 | 0 |
T4 | 173240 | 172892 | 0 | 0 |
T6 | 185725 | 185513 | 0 | 0 |
T7 | 8194 | 8122 | 0 | 0 |
T13 | 186504 | 186434 | 0 | 0 |
T14 | 5760 | 5689 | 0 | 0 |
T26 | 650049 | 649893 | 0 | 0 |
T29 | 5932 | 5859 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 45742798 | 45679565 | 0 | 789 |
T1 | 551404 | 551085 | 0 | 3 |
T2 | 69872 | 69508 | 0 | 3 |
T3 | 9775 | 9702 | 0 | 3 |
T4 | 173240 | 172877 | 0 | 3 |
T6 | 185725 | 185504 | 0 | 3 |
T7 | 8194 | 8119 | 0 | 3 |
T13 | 186504 | 186431 | 0 | 3 |
T14 | 5760 | 5686 | 0 | 3 |
T26 | 650049 | 649887 | 0 | 3 |
T29 | 5932 | 5856 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 263 | 263 | 0 | 0 |
OutputsKnown_A | 45742798 | 45681971 | 0 | 0 |
gen_no_flops.OutputDelay_A | 45742798 | 45681971 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 263 | 263 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T26 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 45742798 | 45681971 | 0 | 0 |
T1 | 551404 | 551100 | 0 | 0 |
T2 | 69872 | 69523 | 0 | 0 |
T3 | 9775 | 9705 | 0 | 0 |
T4 | 173240 | 172892 | 0 | 0 |
T6 | 185725 | 185513 | 0 | 0 |
T7 | 8194 | 8122 | 0 | 0 |
T13 | 186504 | 186434 | 0 | 0 |
T14 | 5760 | 5689 | 0 | 0 |
T26 | 650049 | 649893 | 0 | 0 |
T29 | 5932 | 5859 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 45742798 | 45681971 | 0 | 0 |
T1 | 551404 | 551100 | 0 | 0 |
T2 | 69872 | 69523 | 0 | 0 |
T3 | 9775 | 9705 | 0 | 0 |
T4 | 173240 | 172892 | 0 | 0 |
T6 | 185725 | 185513 | 0 | 0 |
T7 | 8194 | 8122 | 0 | 0 |
T13 | 186504 | 186434 | 0 | 0 |
T14 | 5760 | 5689 | 0 | 0 |
T26 | 650049 | 649893 | 0 | 0 |
T29 | 5932 | 5859 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 263 | 263 | 0 | 0 |
OutputsKnown_A | 45742798 | 45681971 | 0 | 0 |
gen_no_flops.OutputDelay_A | 45742798 | 45681971 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 263 | 263 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T26 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 45742798 | 45681971 | 0 | 0 |
T1 | 551404 | 551100 | 0 | 0 |
T2 | 69872 | 69523 | 0 | 0 |
T3 | 9775 | 9705 | 0 | 0 |
T4 | 173240 | 172892 | 0 | 0 |
T6 | 185725 | 185513 | 0 | 0 |
T7 | 8194 | 8122 | 0 | 0 |
T13 | 186504 | 186434 | 0 | 0 |
T14 | 5760 | 5689 | 0 | 0 |
T26 | 650049 | 649893 | 0 | 0 |
T29 | 5932 | 5859 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 45742798 | 45681971 | 0 | 0 |
T1 | 551404 | 551100 | 0 | 0 |
T2 | 69872 | 69523 | 0 | 0 |
T3 | 9775 | 9705 | 0 | 0 |
T4 | 173240 | 172892 | 0 | 0 |
T6 | 185725 | 185513 | 0 | 0 |
T7 | 8194 | 8122 | 0 | 0 |
T13 | 186504 | 186434 | 0 | 0 |
T14 | 5760 | 5689 | 0 | 0 |
T26 | 650049 | 649893 | 0 | 0 |
T29 | 5932 | 5859 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |