Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

659992

1

T4

4

T7

3

T5

2

full_word

602821

1

T1

2

T4

7

T7

4

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	1262523	1			T1	2		T4	11		T7	7
auto[TlIntgErrCmd]	77	1			T169	5		T170	3		T160	3
auto[TlIntgErrData]	108	1			T169	2		T170	10		T160	3
auto[TlIntgErrBoth]	105	1			T169	3		T170	7		T160	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

523059

1

T1

1

T4

2

T7

2

auto[1]

739754

1

T1

1

T4

9

T7

5

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	218005	1			T7	2		T8	3		T6	2
auto[TlIntgErrNone]	partial	auto[1]	441726	1			T4	4		T7	1		T5	2
auto[TlIntgErrNone]	full_word	auto[0]	304914	1			T1	1		T4	2		T8	2
auto[TlIntgErrNone]	full_word	auto[1]	297878	1			T1	1		T4	5		T7	4
auto[TlIntgErrCmd]	partial	auto[0]	34	1			T169	2		T170	2		T160	2
auto[TlIntgErrCmd]	partial	auto[1]	35	1			T169	3		T170	1		T160	1
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T189	1		T193	2		T197	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T196	1		T198	1		T199	1
auto[TlIntgErrData]	partial	auto[0]	54	1			T169	2		T170	6		T189	1
auto[TlIntgErrData]	partial	auto[1]	47	1			T170	4		T160	3		T190	3
auto[TlIntgErrData]	full_word	auto[0]	5	1			T193	2		T200	1		T201	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T195	1		T199	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T170	3		T189	1		T192	2
auto[TlIntgErrBoth]	partial	auto[1]	53	1			T169	3		T170	4		T160	4
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T189	1		T202	1		T199	2
auto[TlIntgErrBoth]	full_word	auto[1]	10	1			T189	1		T191	2		T200	1