Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.61	100.00	90.48	97.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	108837498	126613	0	0
late_debug_enable_rd_A	108837498	12306	0	0
late_debug_enable_regwen_rd_A	108837498	10181	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	108837498	126613	0	0
T9	245636	8537	0	0
T12	832811	0	0	0
T14	0	2089	0	0
T17	0	5773	0	0
T23	0	7243	0	0
T25	0	7039	0	0
T26	64848	0	0	0
T48	67583	0	0	0
T50	0	5588	0	0
T51	16318	0	0	0
T55	4841	0	0	0
T57	0	4432	0	0
T58	0	2715	0	0
T62	4036	0	0	0
T99	0	6925	0	0
T102	0	2409	0	0
T110	134391	0	0	0
T113	5627	0	0	0
T114	107142	0	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	108837498	12306	0	0
T17	303972	0	0	0
T57	0	1453	0	0
T95	0	1064	0	0
T99	0	1271	0	0
T102	134056	1063	0	0
T104	0	5	0	0
T117	0	38	0	0
T157	0	283	0	0
T158	0	98	0	0
T159	0	120	0	0
T160	0	47	0	0
T161	2081	0	0	0
T162	37004	0	0	0
T163	45952	0	0	0
T164	364514	0	0	0
T165	88338	0	0	0
T166	51977	0	0	0
T167	3445	0	0	0
T168	90173	0	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	108837498	10181	0	0
T17	303972	0	0	0
T57	0	1321	0	0
T95	0	1012	0	0
T99	0	861	0	0
T102	134056	917	0	0
T104	0	13	0	0
T117	0	18	0	0
T157	0	242	0	0
T158	0	49	0	0
T159	0	79	0	0
T160	0	64	0	0
T161	2081	0	0	0
T162	37004	0	0	0
T163	45952	0	0	0
T164	364514	0	0	0
T165	88338	0	0	0
T166	51977	0	0	0
T167	3445	0	0	0
T168	90173	0	0	0