Unified Coverage Report :: Module :: rv_dm_enable_checker

Module : rv_dm_enable_checker

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.enable_checker	100.00	100.00					100.00

---

Module Instance : tb.dut.enable_checker

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.61	100.00	90.48	97.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rv_dm_enable_checker

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	36	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv' or '../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	1	1
36	1	1

---

Assert Coverage for Module : rv_dm_enable_checker

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DebugRequestNeedsDebug_A	53242836	53183494	0	0
MemTLResponseWithoutDebugIsError_A	53161446	53102104	0	0
NdmResetAckNeedsDebug_A	53243737	53184395	0	0
SbaTLRequestNeedsDebug_A	53161446	53102104	0	0

DebugRequestNeedsDebug_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53242836	53183494	0	0
T1	16311	16243	0	0
T2	137568	137510	0	0
T3	61359	61297	0	0
T4	108402	108116	0	0
T7	90005	89739	0	0
T15	77313	77249	0	0
T33	3910	3845	0	0
T34	2847	2782	0	0
T35	2358	2291	0	0
T36	81687	81636	0	0

MemTLResponseWithoutDebugIsError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53161446	53102104	0	0
T1	16311	16243	0	0
T2	137568	137510	0	0
T3	61359	61297	0	0
T4	108402	108116	0	0
T7	90005	89739	0	0
T15	77313	77249	0	0
T33	3910	3845	0	0
T34	2847	2782	0	0
T35	2358	2291	0	0
T36	81687	81636	0	0

NdmResetAckNeedsDebug_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53243737	53184395	0	0
T1	16311	16243	0	0
T2	137568	137510	0	0
T3	61359	61297	0	0
T4	108402	108116	0	0
T7	90005	89739	0	0
T15	77313	77249	0	0
T33	3910	3845	0	0
T34	2847	2782	0	0
T35	2358	2291	0	0
T36	81687	81636	0	0

SbaTLRequestNeedsDebug_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53161446	53102104	0	0
T1	16311	16243	0	0
T2	137568	137510	0	0
T3	61359	61297	0	0
T4	108402	108116	0	0
T7	90005	89739	0	0
T15	77313	77249	0	0
T33	3910	3845	0	0
T34	2847	2782	0	0
T35	2358	2291	0	0
T36	81687	81636	0	0