Line Coverage for Module :
prim_generic_clock_mux2
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Module :
prim_generic_clock_mux2
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T91 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T91 |
1 | 1 | Covered | T91 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T91 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Module :
prim_generic_clock_mux2
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
7374903 |
7373411 |
0 |
0 |
selKnown1 |
58309323 |
58307831 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7374903 |
7373411 |
0 |
0 |
T1 |
1556 |
1554 |
0 |
0 |
T2 |
19382 |
19380 |
0 |
0 |
T3 |
20042 |
20040 |
0 |
0 |
T4 |
12316 |
12312 |
0 |
0 |
T5 |
2 |
0 |
0 |
0 |
T7 |
7160 |
7156 |
0 |
0 |
T8 |
0 |
9 |
0 |
0 |
T15 |
33824 |
33820 |
0 |
0 |
T21 |
0 |
9 |
0 |
0 |
T28 |
2 |
0 |
0 |
0 |
T29 |
0 |
14 |
0 |
0 |
T30 |
0 |
12 |
0 |
0 |
T33 |
322 |
320 |
0 |
0 |
T34 |
238 |
234 |
0 |
0 |
T35 |
292 |
288 |
0 |
0 |
T36 |
23818 |
23814 |
0 |
0 |
T37 |
0 |
2 |
0 |
0 |
T46 |
0 |
7 |
0 |
0 |
T59 |
0 |
9 |
0 |
0 |
T65 |
0 |
6 |
0 |
0 |
T69 |
2 |
0 |
0 |
0 |
T111 |
2 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
58309323 |
58307831 |
0 |
0 |
T1 |
17089 |
17087 |
0 |
0 |
T2 |
147259 |
147257 |
0 |
0 |
T3 |
71380 |
71378 |
0 |
0 |
T4 |
114563 |
114559 |
0 |
0 |
T5 |
2 |
0 |
0 |
0 |
T7 |
93589 |
93585 |
0 |
0 |
T8 |
0 |
8 |
0 |
0 |
T15 |
94226 |
94222 |
0 |
0 |
T21 |
0 |
6 |
0 |
0 |
T28 |
2 |
0 |
0 |
0 |
T29 |
0 |
14 |
0 |
0 |
T30 |
0 |
8 |
0 |
0 |
T33 |
4071 |
4069 |
0 |
0 |
T34 |
2967 |
2963 |
0 |
0 |
T35 |
2505 |
2501 |
0 |
0 |
T36 |
93597 |
93593 |
0 |
0 |
T37 |
0 |
2 |
0 |
0 |
T46 |
0 |
6 |
0 |
0 |
T59 |
0 |
8 |
0 |
0 |
T65 |
0 |
6 |
0 |
0 |
T69 |
2 |
0 |
0 |
0 |
T111 |
2 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T91 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T91 |
1 | 1 | Covered | T91 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T91 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
2309239 |
2308976 |
0 |
0 |
selKnown1 |
53243737 |
53243474 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2309239 |
2308976 |
0 |
0 |
T1 |
778 |
777 |
0 |
0 |
T2 |
9691 |
9690 |
0 |
0 |
T3 |
10021 |
10020 |
0 |
0 |
T4 |
6153 |
6152 |
0 |
0 |
T7 |
3576 |
3575 |
0 |
0 |
T15 |
16911 |
16910 |
0 |
0 |
T33 |
161 |
160 |
0 |
0 |
T34 |
118 |
117 |
0 |
0 |
T35 |
145 |
144 |
0 |
0 |
T36 |
11908 |
11907 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
53243737 |
53243474 |
0 |
0 |
T1 |
16311 |
16310 |
0 |
0 |
T2 |
137568 |
137567 |
0 |
0 |
T3 |
61359 |
61358 |
0 |
0 |
T4 |
108402 |
108401 |
0 |
0 |
T7 |
90005 |
90004 |
0 |
0 |
T15 |
77313 |
77312 |
0 |
0 |
T33 |
3910 |
3909 |
0 |
0 |
T34 |
2847 |
2846 |
0 |
0 |
T35 |
2358 |
2357 |
0 |
0 |
T36 |
81687 |
81686 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T91 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T91 |
1 | 1 | Covered | T91 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T91 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
754 |
491 |
0 |
0 |
T4 |
4 |
3 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T7 |
4 |
3 |
0 |
0 |
T8 |
0 |
4 |
0 |
0 |
T15 |
1 |
0 |
0 |
0 |
T21 |
0 |
4 |
0 |
0 |
T28 |
1 |
0 |
0 |
0 |
T29 |
0 |
7 |
0 |
0 |
T30 |
0 |
6 |
0 |
0 |
T34 |
1 |
0 |
0 |
0 |
T35 |
1 |
0 |
0 |
0 |
T36 |
1 |
0 |
0 |
0 |
T37 |
0 |
1 |
0 |
0 |
T46 |
0 |
3 |
0 |
0 |
T59 |
0 |
4 |
0 |
0 |
T65 |
0 |
3 |
0 |
0 |
T69 |
1 |
0 |
0 |
0 |
T111 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
721 |
458 |
0 |
0 |
T4 |
4 |
3 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T7 |
4 |
3 |
0 |
0 |
T8 |
0 |
4 |
0 |
0 |
T15 |
1 |
0 |
0 |
0 |
T21 |
0 |
3 |
0 |
0 |
T28 |
1 |
0 |
0 |
0 |
T29 |
0 |
7 |
0 |
0 |
T30 |
0 |
4 |
0 |
0 |
T34 |
1 |
0 |
0 |
0 |
T35 |
1 |
0 |
0 |
0 |
T36 |
1 |
0 |
0 |
0 |
T37 |
0 |
1 |
0 |
0 |
T46 |
0 |
3 |
0 |
0 |
T59 |
0 |
4 |
0 |
0 |
T65 |
0 |
3 |
0 |
0 |
T69 |
1 |
0 |
0 |
0 |
T111 |
1 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T91 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T91 |
1 | 1 | Covered | T91 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T91 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
5063214 |
5062731 |
0 |
0 |
selKnown1 |
5063213 |
5062730 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
5063214 |
5062731 |
0 |
0 |
T1 |
778 |
777 |
0 |
0 |
T2 |
9691 |
9690 |
0 |
0 |
T3 |
10021 |
10020 |
0 |
0 |
T4 |
6153 |
6152 |
0 |
0 |
T7 |
3576 |
3575 |
0 |
0 |
T15 |
16911 |
16910 |
0 |
0 |
T33 |
161 |
160 |
0 |
0 |
T34 |
118 |
117 |
0 |
0 |
T35 |
145 |
144 |
0 |
0 |
T36 |
11908 |
11907 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
5063213 |
5062730 |
0 |
0 |
T1 |
778 |
777 |
0 |
0 |
T2 |
9691 |
9690 |
0 |
0 |
T3 |
10021 |
10020 |
0 |
0 |
T4 |
6153 |
6152 |
0 |
0 |
T7 |
3576 |
3575 |
0 |
0 |
T15 |
16911 |
16910 |
0 |
0 |
T33 |
161 |
160 |
0 |
0 |
T34 |
118 |
117 |
0 |
0 |
T35 |
145 |
144 |
0 |
0 |
T36 |
11908 |
11907 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T91 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T91 |
1 | 1 | Covered | T91 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T91 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
1696 |
1213 |
0 |
0 |
selKnown1 |
1652 |
1169 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1696 |
1213 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T7 |
4 |
3 |
0 |
0 |
T8 |
0 |
5 |
0 |
0 |
T15 |
1 |
0 |
0 |
0 |
T21 |
0 |
5 |
0 |
0 |
T28 |
1 |
0 |
0 |
0 |
T29 |
0 |
7 |
0 |
0 |
T30 |
0 |
6 |
0 |
0 |
T34 |
1 |
0 |
0 |
0 |
T35 |
1 |
0 |
0 |
0 |
T36 |
1 |
0 |
0 |
0 |
T37 |
0 |
1 |
0 |
0 |
T46 |
0 |
4 |
0 |
0 |
T59 |
0 |
5 |
0 |
0 |
T65 |
0 |
3 |
0 |
0 |
T69 |
1 |
0 |
0 |
0 |
T111 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1652 |
1169 |
0 |
0 |
T4 |
4 |
3 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T7 |
4 |
3 |
0 |
0 |
T8 |
0 |
4 |
0 |
0 |
T15 |
1 |
0 |
0 |
0 |
T21 |
0 |
3 |
0 |
0 |
T28 |
1 |
0 |
0 |
0 |
T29 |
0 |
7 |
0 |
0 |
T30 |
0 |
4 |
0 |
0 |
T34 |
1 |
0 |
0 |
0 |
T35 |
1 |
0 |
0 |
0 |
T36 |
1 |
0 |
0 |
0 |
T37 |
0 |
1 |
0 |
0 |
T46 |
0 |
3 |
0 |
0 |
T59 |
0 |
4 |
0 |
0 |
T65 |
0 |
3 |
0 |
0 |
T69 |
1 |
0 |
0 |
0 |
T111 |
1 |
0 |
0 |
0 |