SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_lc_sync_lc_hw_debug_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prim_lc_sync_lc_dft_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_en_sync_copies | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_pm_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
97.61 | 100.00 | 90.48 | 97.60 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
97.61 | 100.00 | 90.48 | 97.60 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
97.61 | 100.00 | 90.48 | 97.60 | 100.00 | 100.00 | dut |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
97.61 | 100.00 | 90.48 | 97.60 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
78.91 | 86.27 | 76.47 | 100.00 | 81.82 | 50.00 | u_tlul_lc_gate_sba |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
90.00 | 100.00 | 100.00 | 100.00 | 100.00 | 50.00 | u_tlul_lc_gate_rom |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1578 | 1578 | 0 | 0 |
OutputsKnown_A | 319380131 | 319024079 | 0 | 0 |
gen_flops.OutputDelay_A | 159731211 | 159546696 | 0 | 2367 |
gen_no_flops.OutputDelay_A | 159648920 | 159470894 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1578 | 1578 | 0 | 0 |
T1 | 6 | 6 | 0 | 0 |
T2 | 6 | 6 | 0 | 0 |
T3 | 6 | 6 | 0 | 0 |
T4 | 6 | 6 | 0 | 0 |
T7 | 6 | 6 | 0 | 0 |
T15 | 6 | 6 | 0 | 0 |
T33 | 6 | 6 | 0 | 0 |
T34 | 6 | 6 | 0 | 0 |
T35 | 6 | 6 | 0 | 0 |
T36 | 6 | 6 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 319380131 | 319024079 | 0 | 0 |
T1 | 97866 | 97458 | 0 | 0 |
T2 | 825408 | 825060 | 0 | 0 |
T3 | 368154 | 367782 | 0 | 0 |
T4 | 650412 | 648696 | 0 | 0 |
T7 | 540030 | 538434 | 0 | 0 |
T15 | 463878 | 463494 | 0 | 0 |
T33 | 23460 | 23070 | 0 | 0 |
T34 | 17082 | 16692 | 0 | 0 |
T35 | 14148 | 13746 | 0 | 0 |
T36 | 490122 | 489816 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 159731211 | 159546696 | 0 | 2367 |
T1 | 48933 | 48720 | 0 | 9 |
T2 | 412704 | 412521 | 0 | 9 |
T3 | 184077 | 183882 | 0 | 9 |
T4 | 325206 | 324312 | 0 | 9 |
T7 | 270015 | 269181 | 0 | 9 |
T15 | 231939 | 231738 | 0 | 9 |
T33 | 11730 | 11526 | 0 | 9 |
T34 | 8541 | 8337 | 0 | 9 |
T35 | 7074 | 6864 | 0 | 9 |
T36 | 245061 | 244899 | 0 | 9 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 159648920 | 159470894 | 0 | 0 |
T1 | 48933 | 48729 | 0 | 0 |
T2 | 412704 | 412530 | 0 | 0 |
T3 | 184077 | 183891 | 0 | 0 |
T4 | 325206 | 324348 | 0 | 0 |
T7 | 270015 | 269217 | 0 | 0 |
T15 | 231939 | 231747 | 0 | 0 |
T33 | 11730 | 11535 | 0 | 0 |
T34 | 8541 | 8346 | 0 | 0 |
T35 | 7074 | 6873 | 0 | 0 |
T36 | 245061 | 244908 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 263 | 263 | 0 | 0 |
OutputsKnown_A | 53243737 | 53184395 | 0 | 0 |
gen_flops.OutputDelay_A | 53243737 | 53182232 | 0 | 789 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 263 | 263 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
T34 | 1 | 1 | 0 | 0 |
T35 | 1 | 1 | 0 | 0 |
T36 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 53243737 | 53184395 | 0 | 0 |
T1 | 16311 | 16243 | 0 | 0 |
T2 | 137568 | 137510 | 0 | 0 |
T3 | 61359 | 61297 | 0 | 0 |
T4 | 108402 | 108116 | 0 | 0 |
T7 | 90005 | 89739 | 0 | 0 |
T15 | 77313 | 77249 | 0 | 0 |
T33 | 3910 | 3845 | 0 | 0 |
T34 | 2847 | 2782 | 0 | 0 |
T35 | 2358 | 2291 | 0 | 0 |
T36 | 81687 | 81636 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 53243737 | 53182232 | 0 | 789 |
T1 | 16311 | 16240 | 0 | 3 |
T2 | 137568 | 137507 | 0 | 3 |
T3 | 61359 | 61294 | 0 | 3 |
T4 | 108402 | 108104 | 0 | 3 |
T7 | 90005 | 89727 | 0 | 3 |
T15 | 77313 | 77246 | 0 | 3 |
T33 | 3910 | 3842 | 0 | 3 |
T34 | 2847 | 2779 | 0 | 3 |
T35 | 2358 | 2288 | 0 | 3 |
T36 | 81687 | 81633 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 263 | 263 | 0 | 0 |
OutputsKnown_A | 53243737 | 53184395 | 0 | 0 |
gen_flops.OutputDelay_A | 53243737 | 53182232 | 0 | 789 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 263 | 263 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
T34 | 1 | 1 | 0 | 0 |
T35 | 1 | 1 | 0 | 0 |
T36 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 53243737 | 53184395 | 0 | 0 |
T1 | 16311 | 16243 | 0 | 0 |
T2 | 137568 | 137510 | 0 | 0 |
T3 | 61359 | 61297 | 0 | 0 |
T4 | 108402 | 108116 | 0 | 0 |
T7 | 90005 | 89739 | 0 | 0 |
T15 | 77313 | 77249 | 0 | 0 |
T33 | 3910 | 3845 | 0 | 0 |
T34 | 2847 | 2782 | 0 | 0 |
T35 | 2358 | 2291 | 0 | 0 |
T36 | 81687 | 81636 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 53243737 | 53182232 | 0 | 789 |
T1 | 16311 | 16240 | 0 | 3 |
T2 | 137568 | 137507 | 0 | 3 |
T3 | 61359 | 61294 | 0 | 3 |
T4 | 108402 | 108104 | 0 | 3 |
T7 | 90005 | 89727 | 0 | 3 |
T15 | 77313 | 77246 | 0 | 3 |
T33 | 3910 | 3842 | 0 | 3 |
T34 | 2847 | 2779 | 0 | 3 |
T35 | 2358 | 2288 | 0 | 3 |
T36 | 81687 | 81633 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 263 | 263 | 0 | 0 |
OutputsKnown_A | 53161446 | 53102104 | 0 | 0 |
gen_no_flops.OutputDelay_A | 53161446 | 53102104 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 263 | 263 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
T34 | 1 | 1 | 0 | 0 |
T35 | 1 | 1 | 0 | 0 |
T36 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 53161446 | 53102104 | 0 | 0 |
T1 | 16311 | 16243 | 0 | 0 |
T2 | 137568 | 137510 | 0 | 0 |
T3 | 61359 | 61297 | 0 | 0 |
T4 | 108402 | 108116 | 0 | 0 |
T7 | 90005 | 89739 | 0 | 0 |
T15 | 77313 | 77249 | 0 | 0 |
T33 | 3910 | 3845 | 0 | 0 |
T34 | 2847 | 2782 | 0 | 0 |
T35 | 2358 | 2291 | 0 | 0 |
T36 | 81687 | 81636 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 53161446 | 53102104 | 0 | 0 |
T1 | 16311 | 16243 | 0 | 0 |
T2 | 137568 | 137510 | 0 | 0 |
T3 | 61359 | 61297 | 0 | 0 |
T4 | 108402 | 108116 | 0 | 0 |
T7 | 90005 | 89739 | 0 | 0 |
T15 | 77313 | 77249 | 0 | 0 |
T33 | 3910 | 3845 | 0 | 0 |
T34 | 2847 | 2782 | 0 | 0 |
T35 | 2358 | 2291 | 0 | 0 |
T36 | 81687 | 81636 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 263 | 263 | 0 | 0 |
OutputsKnown_A | 53243737 | 53184395 | 0 | 0 |
gen_flops.OutputDelay_A | 53243737 | 53182232 | 0 | 789 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 263 | 263 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
T34 | 1 | 1 | 0 | 0 |
T35 | 1 | 1 | 0 | 0 |
T36 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 53243737 | 53184395 | 0 | 0 |
T1 | 16311 | 16243 | 0 | 0 |
T2 | 137568 | 137510 | 0 | 0 |
T3 | 61359 | 61297 | 0 | 0 |
T4 | 108402 | 108116 | 0 | 0 |
T7 | 90005 | 89739 | 0 | 0 |
T15 | 77313 | 77249 | 0 | 0 |
T33 | 3910 | 3845 | 0 | 0 |
T34 | 2847 | 2782 | 0 | 0 |
T35 | 2358 | 2291 | 0 | 0 |
T36 | 81687 | 81636 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 53243737 | 53182232 | 0 | 789 |
T1 | 16311 | 16240 | 0 | 3 |
T2 | 137568 | 137507 | 0 | 3 |
T3 | 61359 | 61294 | 0 | 3 |
T4 | 108402 | 108104 | 0 | 3 |
T7 | 90005 | 89727 | 0 | 3 |
T15 | 77313 | 77246 | 0 | 3 |
T33 | 3910 | 3842 | 0 | 3 |
T34 | 2847 | 2779 | 0 | 3 |
T35 | 2358 | 2288 | 0 | 3 |
T36 | 81687 | 81633 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 263 | 263 | 0 | 0 |
OutputsKnown_A | 53243737 | 53184395 | 0 | 0 |
gen_no_flops.OutputDelay_A | 53243737 | 53184395 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 263 | 263 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
T34 | 1 | 1 | 0 | 0 |
T35 | 1 | 1 | 0 | 0 |
T36 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 53243737 | 53184395 | 0 | 0 |
T1 | 16311 | 16243 | 0 | 0 |
T2 | 137568 | 137510 | 0 | 0 |
T3 | 61359 | 61297 | 0 | 0 |
T4 | 108402 | 108116 | 0 | 0 |
T7 | 90005 | 89739 | 0 | 0 |
T15 | 77313 | 77249 | 0 | 0 |
T33 | 3910 | 3845 | 0 | 0 |
T34 | 2847 | 2782 | 0 | 0 |
T35 | 2358 | 2291 | 0 | 0 |
T36 | 81687 | 81636 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 53243737 | 53184395 | 0 | 0 |
T1 | 16311 | 16243 | 0 | 0 |
T2 | 137568 | 137510 | 0 | 0 |
T3 | 61359 | 61297 | 0 | 0 |
T4 | 108402 | 108116 | 0 | 0 |
T7 | 90005 | 89739 | 0 | 0 |
T15 | 77313 | 77249 | 0 | 0 |
T33 | 3910 | 3845 | 0 | 0 |
T34 | 2847 | 2782 | 0 | 0 |
T35 | 2358 | 2291 | 0 | 0 |
T36 | 81687 | 81636 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 263 | 263 | 0 | 0 |
OutputsKnown_A | 53243737 | 53184395 | 0 | 0 |
gen_no_flops.OutputDelay_A | 53243737 | 53184395 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 263 | 263 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
T34 | 1 | 1 | 0 | 0 |
T35 | 1 | 1 | 0 | 0 |
T36 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 53243737 | 53184395 | 0 | 0 |
T1 | 16311 | 16243 | 0 | 0 |
T2 | 137568 | 137510 | 0 | 0 |
T3 | 61359 | 61297 | 0 | 0 |
T4 | 108402 | 108116 | 0 | 0 |
T7 | 90005 | 89739 | 0 | 0 |
T15 | 77313 | 77249 | 0 | 0 |
T33 | 3910 | 3845 | 0 | 0 |
T34 | 2847 | 2782 | 0 | 0 |
T35 | 2358 | 2291 | 0 | 0 |
T36 | 81687 | 81636 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 53243737 | 53184395 | 0 | 0 |
T1 | 16311 | 16243 | 0 | 0 |
T2 | 137568 | 137510 | 0 | 0 |
T3 | 61359 | 61297 | 0 | 0 |
T4 | 108402 | 108116 | 0 | 0 |
T7 | 90005 | 89739 | 0 | 0 |
T15 | 77313 | 77249 | 0 | 0 |
T33 | 3910 | 3845 | 0 | 0 |
T34 | 2847 | 2782 | 0 | 0 |
T35 | 2358 | 2291 | 0 | 0 |
T36 | 81687 | 81636 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |