SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_mubi32_sync_late_debug_enable | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
97.61 | 100.00 | 90.48 | 97.60 | 100.00 | 100.00 | dut |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 5 | 5 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 4 | 4 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 263 | 263 | 0 | 0 |
OutputsKnown_A | 53243737 | 53184395 | 0 | 0 |
gen_no_flops.OutputDelay_A | 53243737 | 53184395 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 263 | 263 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
T34 | 1 | 1 | 0 | 0 |
T35 | 1 | 1 | 0 | 0 |
T36 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 53243737 | 53184395 | 0 | 0 |
T1 | 16311 | 16243 | 0 | 0 |
T2 | 137568 | 137510 | 0 | 0 |
T3 | 61359 | 61297 | 0 | 0 |
T4 | 108402 | 108116 | 0 | 0 |
T7 | 90005 | 89739 | 0 | 0 |
T15 | 77313 | 77249 | 0 | 0 |
T33 | 3910 | 3845 | 0 | 0 |
T34 | 2847 | 2782 | 0 | 0 |
T35 | 2358 | 2291 | 0 | 0 |
T36 | 81687 | 81636 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 53243737 | 53184395 | 0 | 0 |
T1 | 16311 | 16243 | 0 | 0 |
T2 | 137568 | 137510 | 0 | 0 |
T3 | 61359 | 61297 | 0 | 0 |
T4 | 108402 | 108116 | 0 | 0 |
T7 | 90005 | 89739 | 0 | 0 |
T15 | 77313 | 77249 | 0 | 0 |
T33 | 3910 | 3845 | 0 | 0 |
T34 | 2847 | 2782 | 0 | 0 |
T35 | 2358 | 2291 | 0 | 0 |
T36 | 81687 | 81636 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |