Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
88.53 96.32 89.25 92.10 94.67 90.27 98.63 58.45


Total test records in report: 483
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html
T316 /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.3306221432 Aug 17 04:49:55 PM PDT 24 Aug 17 04:50:15 PM PDT 24 6974634449 ps
T36 /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.2312528651 Aug 17 04:49:14 PM PDT 24 Aug 17 04:49:16 PM PDT 24 656931349 ps
T317 /workspace/coverage/default/19.rv_dm_stress_all.2228091134 Aug 17 04:49:52 PM PDT 24 Aug 17 04:49:54 PM PDT 24 1449296519 ps
T318 /workspace/coverage/default/39.rv_dm_stress_all.3546004270 Aug 17 04:49:53 PM PDT 24 Aug 17 04:49:55 PM PDT 24 3899019917 ps
T319 /workspace/coverage/default/17.rv_dm_sba_tl_access.1732000507 Aug 17 04:49:55 PM PDT 24 Aug 17 04:49:57 PM PDT 24 2664458998 ps
T320 /workspace/coverage/default/43.rv_dm_alert_test.1477863351 Aug 17 04:50:01 PM PDT 24 Aug 17 04:50:01 PM PDT 24 117431706 ps
T321 /workspace/coverage/default/0.rv_dm_stress_all.2457497190 Aug 17 04:49:24 PM PDT 24 Aug 17 04:49:30 PM PDT 24 3808042336 ps
T62 /workspace/coverage/default/0.rv_dm_dmi_failed_op.589213432 Aug 17 04:49:17 PM PDT 24 Aug 17 04:49:18 PM PDT 24 146444367 ps
T322 /workspace/coverage/default/7.rv_dm_alert_test.2851860710 Aug 17 04:49:49 PM PDT 24 Aug 17 04:49:50 PM PDT 24 157212487 ps
T323 /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.4241151764 Aug 17 04:49:42 PM PDT 24 Aug 17 04:50:48 PM PDT 24 37928828015 ps
T324 /workspace/coverage/default/4.rv_dm_buffered_enable.4110112280 Aug 17 04:49:41 PM PDT 24 Aug 17 04:49:43 PM PDT 24 152731753 ps
T325 /workspace/coverage/default/19.rv_dm_alert_test.4099297313 Aug 17 04:49:52 PM PDT 24 Aug 17 04:49:53 PM PDT 24 85835975 ps
T60 /workspace/coverage/default/3.rv_dm_sparse_lc_gate_fsm.967249868 Aug 17 04:49:46 PM PDT 24 Aug 17 04:49:48 PM PDT 24 329019306 ps
T120 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.3085296691 Aug 17 04:49:16 PM PDT 24 Aug 17 04:49:18 PM PDT 24 220899748 ps
T107 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3546740002 Aug 17 04:48:47 PM PDT 24 Aug 17 04:48:48 PM PDT 24 455289426 ps
T170 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3912896120 Aug 17 04:49:10 PM PDT 24 Aug 17 04:49:20 PM PDT 24 2862030534 ps
T108 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.769168654 Aug 17 04:49:07 PM PDT 24 Aug 17 04:49:09 PM PDT 24 558727082 ps
T326 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.1847425023 Aug 17 04:49:09 PM PDT 24 Aug 17 04:49:18 PM PDT 24 5970283880 ps
T171 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.430612511 Aug 17 04:48:58 PM PDT 24 Aug 17 04:49:17 PM PDT 24 1566985842 ps
T327 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.3658199025 Aug 17 04:49:00 PM PDT 24 Aug 17 04:49:16 PM PDT 24 25491247958 ps
T121 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.3320771273 Aug 17 04:48:53 PM PDT 24 Aug 17 04:49:00 PM PDT 24 1686160039 ps
T109 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.64245346 Aug 17 04:49:17 PM PDT 24 Aug 17 04:49:18 PM PDT 24 153960170 ps
T328 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.3145712643 Aug 17 04:49:02 PM PDT 24 Aug 17 04:49:03 PM PDT 24 169204222 ps
T329 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.2267399400 Aug 17 04:49:16 PM PDT 24 Aug 17 04:49:20 PM PDT 24 4205730897 ps
T122 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.3007520017 Aug 17 04:48:51 PM PDT 24 Aug 17 04:48:53 PM PDT 24 141222822 ps
T159 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.3513661611 Aug 17 04:49:11 PM PDT 24 Aug 17 04:49:13 PM PDT 24 123182540 ps
T330 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.3587226359 Aug 17 04:49:03 PM PDT 24 Aug 17 04:49:16 PM PDT 24 4205659634 ps
T331 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.3090808238 Aug 17 04:48:57 PM PDT 24 Aug 17 04:48:58 PM PDT 24 28921181 ps
T332 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.4163497857 Aug 17 04:49:04 PM PDT 24 Aug 17 04:49:08 PM PDT 24 6126472335 ps
T333 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.2368868525 Aug 17 04:49:15 PM PDT 24 Aug 17 04:49:17 PM PDT 24 756005036 ps
T334 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.452001050 Aug 17 04:49:02 PM PDT 24 Aug 17 04:49:17 PM PDT 24 4811380341 ps
T335 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.3749963902 Aug 17 04:48:56 PM PDT 24 Aug 17 04:48:58 PM PDT 24 2285516881 ps
T336 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.943081734 Aug 17 04:48:58 PM PDT 24 Aug 17 04:49:00 PM PDT 24 1364054124 ps
T337 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.3322775349 Aug 17 04:48:46 PM PDT 24 Aug 17 04:48:47 PM PDT 24 368168817 ps
T338 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.2670658667 Aug 17 04:49:11 PM PDT 24 Aug 17 04:49:15 PM PDT 24 2116606946 ps
T339 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.1495780842 Aug 17 04:48:48 PM PDT 24 Aug 17 04:49:05 PM PDT 24 6150962212 ps
T340 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.2865658765 Aug 17 04:49:06 PM PDT 24 Aug 17 04:49:07 PM PDT 24 308843642 ps
T160 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.2990205288 Aug 17 04:49:10 PM PDT 24 Aug 17 04:49:15 PM PDT 24 313598745 ps
T341 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.1066911476 Aug 17 04:48:57 PM PDT 24 Aug 17 04:49:17 PM PDT 24 7609224962 ps
T123 /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.1943198721 Aug 17 04:49:16 PM PDT 24 Aug 17 04:49:20 PM PDT 24 425467293 ps
T124 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.258563433 Aug 17 04:48:50 PM PDT 24 Aug 17 04:49:21 PM PDT 24 4279107114 ps
T342 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.3413804703 Aug 17 04:48:58 PM PDT 24 Aug 17 04:49:08 PM PDT 24 6235134411 ps
T125 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.3996902947 Aug 17 04:49:03 PM PDT 24 Aug 17 04:49:05 PM PDT 24 119048713 ps
T343 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.2751689859 Aug 17 04:49:01 PM PDT 24 Aug 17 04:49:04 PM PDT 24 223057031 ps
T344 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.1160914911 Aug 17 04:49:00 PM PDT 24 Aug 17 04:49:00 PM PDT 24 49642790 ps
T96 /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.793053682 Aug 17 04:48:56 PM PDT 24 Aug 17 04:50:09 PM PDT 24 8510003162 ps
T345 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.2662924378 Aug 17 04:49:16 PM PDT 24 Aug 17 04:49:18 PM PDT 24 1142806260 ps
T98 /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.2860121711 Aug 17 04:48:59 PM PDT 24 Aug 17 04:50:27 PM PDT 24 4512859304 ps
T346 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.1504459237 Aug 17 04:48:56 PM PDT 24 Aug 17 04:48:57 PM PDT 24 284687042 ps
T126 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.1075607531 Aug 17 04:48:58 PM PDT 24 Aug 17 04:49:32 PM PDT 24 2468528072 ps
T347 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.50215916 Aug 17 04:48:43 PM PDT 24 Aug 17 04:48:45 PM PDT 24 537060230 ps
T172 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.3382793283 Aug 17 04:48:52 PM PDT 24 Aug 17 04:49:12 PM PDT 24 8140381108 ps
T348 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1363671272 Aug 17 04:48:39 PM PDT 24 Aug 17 04:48:40 PM PDT 24 142040492 ps
T349 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.3425439370 Aug 17 04:48:49 PM PDT 24 Aug 17 04:48:58 PM PDT 24 5423487339 ps
T131 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.123531688 Aug 17 04:48:45 PM PDT 24 Aug 17 04:48:52 PM PDT 24 7176244942 ps
T350 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.2801250445 Aug 17 04:48:44 PM PDT 24 Aug 17 04:49:22 PM PDT 24 13759972013 ps
T127 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.2088100682 Aug 17 04:49:13 PM PDT 24 Aug 17 04:49:16 PM PDT 24 321664708 ps
T351 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.3091586545 Aug 17 04:49:06 PM PDT 24 Aug 17 04:49:07 PM PDT 24 358015550 ps
T352 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.2948016375 Aug 17 04:49:06 PM PDT 24 Aug 17 04:49:15 PM PDT 24 3075267679 ps
T353 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.2493900194 Aug 17 04:49:07 PM PDT 24 Aug 17 04:49:09 PM PDT 24 1918135896 ps
T128 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.2992629744 Aug 17 04:49:03 PM PDT 24 Aug 17 04:49:05 PM PDT 24 197049234 ps
T129 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.660466846 Aug 17 04:49:02 PM PDT 24 Aug 17 04:49:09 PM PDT 24 498043629 ps
T152 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3671960091 Aug 17 04:49:10 PM PDT 24 Aug 17 04:49:18 PM PDT 24 508482890 ps
T132 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.4029950907 Aug 17 04:48:53 PM PDT 24 Aug 17 04:48:58 PM PDT 24 15617262862 ps
T354 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.3231983998 Aug 17 04:48:47 PM PDT 24 Aug 17 04:48:48 PM PDT 24 70785705 ps
T135 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.3895954145 Aug 17 04:49:04 PM PDT 24 Aug 17 04:49:07 PM PDT 24 337848084 ps
T190 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.550145986 Aug 17 04:49:17 PM PDT 24 Aug 17 04:49:27 PM PDT 24 991967602 ps
T104 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1577209456 Aug 17 04:49:11 PM PDT 24 Aug 17 04:49:14 PM PDT 24 57104513 ps
T133 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.966399765 Aug 17 04:48:48 PM PDT 24 Aug 17 04:49:04 PM PDT 24 5397611074 ps
T355 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1478610056 Aug 17 04:48:46 PM PDT 24 Aug 17 04:48:59 PM PDT 24 14393645262 ps
T356 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2918554326 Aug 17 04:48:56 PM PDT 24 Aug 17 04:48:58 PM PDT 24 7876763892 ps
T357 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.450199094 Aug 17 04:49:10 PM PDT 24 Aug 17 04:49:14 PM PDT 24 167801646 ps
T136 /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.2067751843 Aug 17 04:48:48 PM PDT 24 Aug 17 04:48:55 PM PDT 24 192164435 ps
T358 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.917099352 Aug 17 04:48:48 PM PDT 24 Aug 17 04:49:24 PM PDT 24 21295617265 ps
T359 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.837950795 Aug 17 04:49:02 PM PDT 24 Aug 17 04:49:19 PM PDT 24 5794504338 ps
T144 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.1698216492 Aug 17 04:49:03 PM PDT 24 Aug 17 04:49:05 PM PDT 24 624877741 ps
T360 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.795460129 Aug 17 04:49:05 PM PDT 24 Aug 17 04:49:06 PM PDT 24 211395457 ps
T156 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.1261333302 Aug 17 04:49:10 PM PDT 24 Aug 17 04:49:12 PM PDT 24 163345824 ps
T153 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.2945066437 Aug 17 04:48:58 PM PDT 24 Aug 17 04:49:03 PM PDT 24 3532845180 ps
T361 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.92569548 Aug 17 04:48:52 PM PDT 24 Aug 17 04:48:56 PM PDT 24 240759283 ps
T105 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3984526916 Aug 17 04:49:11 PM PDT 24 Aug 17 04:49:13 PM PDT 24 128843773 ps
T362 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.726220309 Aug 17 04:48:58 PM PDT 24 Aug 17 04:49:20 PM PDT 24 16214835613 ps
T363 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.1514194055 Aug 17 04:48:46 PM PDT 24 Aug 17 04:48:47 PM PDT 24 247331250 ps
T364 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.1566015017 Aug 17 04:49:02 PM PDT 24 Aug 17 04:49:09 PM PDT 24 2289572678 ps
T365 /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.1886688822 Aug 17 04:48:55 PM PDT 24 Aug 17 04:49:36 PM PDT 24 11170105514 ps
T366 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.1811746621 Aug 17 04:49:01 PM PDT 24 Aug 17 04:49:02 PM PDT 24 56904280 ps
T145 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.1163015342 Aug 17 04:48:41 PM PDT 24 Aug 17 04:49:54 PM PDT 24 14040914088 ps
T154 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.3030428062 Aug 17 04:48:57 PM PDT 24 Aug 17 04:49:05 PM PDT 24 501896142 ps
T367 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2883955266 Aug 17 04:49:08 PM PDT 24 Aug 17 04:49:09 PM PDT 24 76847398 ps
T191 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.2783234200 Aug 17 04:48:44 PM PDT 24 Aug 17 04:49:05 PM PDT 24 5734764691 ps
T368 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.1782628683 Aug 17 04:49:01 PM PDT 24 Aug 17 04:49:35 PM PDT 24 4935375318 ps
T146 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.1555777339 Aug 17 04:49:02 PM PDT 24 Aug 17 04:49:04 PM PDT 24 218564904 ps
T369 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.945243921 Aug 17 04:49:02 PM PDT 24 Aug 17 04:49:04 PM PDT 24 64986207 ps
T192 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.2682201177 Aug 17 04:49:03 PM PDT 24 Aug 17 04:49:22 PM PDT 24 4815285927 ps
T370 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.706785297 Aug 17 04:49:06 PM PDT 24 Aug 17 04:49:21 PM PDT 24 12733058816 ps
T371 /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.943488771 Aug 17 04:49:01 PM PDT 24 Aug 17 04:49:04 PM PDT 24 209017883 ps
T372 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.3264104859 Aug 17 04:48:56 PM PDT 24 Aug 17 04:48:57 PM PDT 24 169558100 ps
T373 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.3876838102 Aug 17 04:49:15 PM PDT 24 Aug 17 04:49:19 PM PDT 24 3112678646 ps
T193 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.609693471 Aug 17 04:48:59 PM PDT 24 Aug 17 04:49:18 PM PDT 24 1410317328 ps
T374 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.3051956918 Aug 17 04:49:10 PM PDT 24 Aug 17 04:49:31 PM PDT 24 3623091465 ps
T155 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.754127741 Aug 17 04:49:12 PM PDT 24 Aug 17 04:49:20 PM PDT 24 1534525525 ps
T106 /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.2276914101 Aug 17 04:48:51 PM PDT 24 Aug 17 04:48:54 PM PDT 24 176040527 ps
T375 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.521007251 Aug 17 04:48:48 PM PDT 24 Aug 17 04:48:53 PM PDT 24 119403856 ps
T147 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.2114475661 Aug 17 04:48:53 PM PDT 24 Aug 17 04:49:30 PM PDT 24 3834895262 ps
T376 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.799175161 Aug 17 04:48:49 PM PDT 24 Aug 17 04:48:50 PM PDT 24 40271226 ps
T377 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.2064030958 Aug 17 04:49:05 PM PDT 24 Aug 17 04:49:11 PM PDT 24 4556333703 ps
T99 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3814600844 Aug 17 04:49:02 PM PDT 24 Aug 17 04:49:05 PM PDT 24 208631363 ps
T148 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1081976550 Aug 17 04:48:59 PM PDT 24 Aug 17 04:49:02 PM PDT 24 557807408 ps
T378 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.3782224172 Aug 17 04:49:02 PM PDT 24 Aug 17 04:49:04 PM PDT 24 175136870 ps
T194 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2475624296 Aug 17 04:48:58 PM PDT 24 Aug 17 04:49:12 PM PDT 24 1467124831 ps
T379 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.342593218 Aug 17 04:48:42 PM PDT 24 Aug 17 04:48:51 PM PDT 24 21762202682 ps
T380 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.1802357380 Aug 17 04:49:00 PM PDT 24 Aug 17 04:49:04 PM PDT 24 573363198 ps
T196 /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.3064812957 Aug 17 04:49:07 PM PDT 24 Aug 17 04:49:18 PM PDT 24 9610573252 ps
T381 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.3654046266 Aug 17 04:48:58 PM PDT 24 Aug 17 04:48:59 PM PDT 24 42819144 ps
T382 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.3592941979 Aug 17 04:48:58 PM PDT 24 Aug 17 04:49:02 PM PDT 24 149065235 ps
T97 /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.875949582 Aug 17 04:48:48 PM PDT 24 Aug 17 04:49:36 PM PDT 24 6212619340 ps
T383 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.593779885 Aug 17 04:48:54 PM PDT 24 Aug 17 04:49:04 PM PDT 24 1499519151 ps
T384 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.315939996 Aug 17 04:49:00 PM PDT 24 Aug 17 04:49:07 PM PDT 24 8316385182 ps
T385 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.1921010047 Aug 17 04:49:07 PM PDT 24 Aug 17 04:49:09 PM PDT 24 192540110 ps
T386 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.45880297 Aug 17 04:49:07 PM PDT 24 Aug 17 04:49:09 PM PDT 24 125825555 ps
T387 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1594697642 Aug 17 04:48:43 PM PDT 24 Aug 17 04:48:47 PM PDT 24 692465936 ps
T388 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1967528463 Aug 17 04:48:46 PM PDT 24 Aug 17 04:48:52 PM PDT 24 1794817826 ps
T389 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.4152918697 Aug 17 04:48:55 PM PDT 24 Aug 17 04:50:28 PM PDT 24 34249318105 ps
T390 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.249031845 Aug 17 04:49:03 PM PDT 24 Aug 17 04:49:20 PM PDT 24 1777064787 ps
T137 /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.1446214520 Aug 17 04:49:04 PM PDT 24 Aug 17 04:49:06 PM PDT 24 193491286 ps
T138 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.336172807 Aug 17 04:48:46 PM PDT 24 Aug 17 04:49:15 PM PDT 24 5193319211 ps
T391 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.4048184206 Aug 17 04:49:00 PM PDT 24 Aug 17 04:49:02 PM PDT 24 375003974 ps
T392 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.3313569580 Aug 17 04:49:10 PM PDT 24 Aug 17 04:49:15 PM PDT 24 759791228 ps
T393 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.2974563080 Aug 17 04:48:58 PM PDT 24 Aug 17 04:49:01 PM PDT 24 177236337 ps
T394 /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.2776928819 Aug 17 04:49:05 PM PDT 24 Aug 17 04:50:02 PM PDT 24 39029547096 ps
T395 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.3630982587 Aug 17 04:49:00 PM PDT 24 Aug 17 04:50:36 PM PDT 24 35555385824 ps
T396 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.52721785 Aug 17 04:49:12 PM PDT 24 Aug 17 04:49:26 PM PDT 24 4360108409 ps
T397 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.819932112 Aug 17 04:49:10 PM PDT 24 Aug 17 04:49:25 PM PDT 24 8433739172 ps
T398 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.2743784501 Aug 17 04:48:49 PM PDT 24 Aug 17 04:49:02 PM PDT 24 4270820895 ps
T150 /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.906920881 Aug 17 04:48:58 PM PDT 24 Aug 17 04:49:00 PM PDT 24 110099504 ps
T198 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.3318411578 Aug 17 04:49:09 PM PDT 24 Aug 17 04:49:27 PM PDT 24 4301421461 ps
T399 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.613158913 Aug 17 04:48:57 PM PDT 24 Aug 17 04:52:57 PM PDT 24 85660367663 ps
T139 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.4047879458 Aug 17 04:48:51 PM PDT 24 Aug 17 04:49:58 PM PDT 24 8879438466 ps
T400 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.824646237 Aug 17 04:49:00 PM PDT 24 Aug 17 04:49:04 PM PDT 24 492623363 ps
T401 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.584749482 Aug 17 04:49:05 PM PDT 24 Aug 17 04:50:16 PM PDT 24 23284480818 ps
T402 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.1484207755 Aug 17 04:49:01 PM PDT 24 Aug 17 04:49:04 PM PDT 24 4285960247 ps
T151 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.4258771527 Aug 17 04:49:01 PM PDT 24 Aug 17 04:49:04 PM PDT 24 71395815 ps
T403 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.4268877761 Aug 17 04:48:58 PM PDT 24 Aug 17 04:49:01 PM PDT 24 570917835 ps
T404 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.563971992 Aug 17 04:49:06 PM PDT 24 Aug 17 04:49:21 PM PDT 24 5158869122 ps
T63 /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.1610971718 Aug 17 04:49:03 PM PDT 24 Aug 17 04:50:19 PM PDT 24 9803260807 ps
T140 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.297931010 Aug 17 04:48:56 PM PDT 24 Aug 17 04:49:00 PM PDT 24 630245894 ps
T197 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.722230866 Aug 17 04:48:55 PM PDT 24 Aug 17 04:49:11 PM PDT 24 3433397817 ps
T405 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.4143448751 Aug 17 04:49:03 PM PDT 24 Aug 17 04:49:05 PM PDT 24 190213881 ps
T406 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.3368924721 Aug 17 04:49:06 PM PDT 24 Aug 17 04:49:11 PM PDT 24 430720836 ps
T407 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.3920441878 Aug 17 04:49:10 PM PDT 24 Aug 17 04:49:12 PM PDT 24 183198351 ps
T408 /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.3641462726 Aug 17 04:48:48 PM PDT 24 Aug 17 04:48:50 PM PDT 24 198954153 ps
T141 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.3125946390 Aug 17 04:48:48 PM PDT 24 Aug 17 04:48:55 PM PDT 24 1761216863 ps
T142 /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.1463428771 Aug 17 04:49:02 PM PDT 24 Aug 17 04:49:10 PM PDT 24 674523415 ps
T409 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.12065131 Aug 17 04:49:07 PM PDT 24 Aug 17 04:49:17 PM PDT 24 5365510246 ps
T410 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1110764776 Aug 17 04:49:07 PM PDT 24 Aug 17 04:49:10 PM PDT 24 166269928 ps
T411 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.744370883 Aug 17 04:49:02 PM PDT 24 Aug 17 04:49:07 PM PDT 24 4589580660 ps
T412 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.361642090 Aug 17 04:48:50 PM PDT 24 Aug 17 04:48:52 PM PDT 24 272516006 ps
T413 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.3408281714 Aug 17 04:49:04 PM PDT 24 Aug 17 04:49:06 PM PDT 24 813494691 ps
T414 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.700089530 Aug 17 04:48:49 PM PDT 24 Aug 17 04:48:50 PM PDT 24 386355791 ps
T415 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.3323188757 Aug 17 04:49:00 PM PDT 24 Aug 17 04:49:03 PM PDT 24 1517841489 ps
T416 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.469217076 Aug 17 04:49:10 PM PDT 24 Aug 17 04:49:15 PM PDT 24 1650782161 ps
T417 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.1572018817 Aug 17 04:49:03 PM PDT 24 Aug 17 04:50:22 PM PDT 24 25792291071 ps
T418 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.3140978131 Aug 17 04:48:48 PM PDT 24 Aug 17 04:48:51 PM PDT 24 1451680611 ps
T419 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1503246918 Aug 17 04:49:09 PM PDT 24 Aug 17 04:49:11 PM PDT 24 251857633 ps
T420 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.2201633651 Aug 17 04:48:59 PM PDT 24 Aug 17 04:49:05 PM PDT 24 165758048 ps
T195 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.1098174949 Aug 17 04:48:48 PM PDT 24 Aug 17 04:49:05 PM PDT 24 9190711023 ps
T421 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.366598039 Aug 17 04:49:08 PM PDT 24 Aug 17 04:50:15 PM PDT 24 26410332565 ps
T422 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.2524087546 Aug 17 04:48:51 PM PDT 24 Aug 17 04:49:46 PM PDT 24 1468525909 ps
T423 /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.223487953 Aug 17 04:49:05 PM PDT 24 Aug 17 04:49:08 PM PDT 24 395885061 ps
T424 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.1946826982 Aug 17 04:48:58 PM PDT 24 Aug 17 04:49:01 PM PDT 24 144272096 ps
T425 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.2503290992 Aug 17 04:49:09 PM PDT 24 Aug 17 04:49:10 PM PDT 24 188015550 ps
T426 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.2035278184 Aug 17 04:48:59 PM PDT 24 Aug 17 04:49:02 PM PDT 24 117854759 ps
T427 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3152942877 Aug 17 04:48:39 PM PDT 24 Aug 17 04:48:40 PM PDT 24 218634861 ps
T428 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.1233237697 Aug 17 04:48:51 PM PDT 24 Aug 17 04:48:53 PM PDT 24 183220481 ps
T429 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.646867482 Aug 17 04:49:00 PM PDT 24 Aug 17 04:49:02 PM PDT 24 574909356 ps
T430 /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.1074881954 Aug 17 04:49:12 PM PDT 24 Aug 17 04:49:20 PM PDT 24 467680302 ps
T431 /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.1046475100 Aug 17 04:48:39 PM PDT 24 Aug 17 04:49:11 PM PDT 24 2428661649 ps
T432 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.1843512090 Aug 17 04:48:46 PM PDT 24 Aug 17 04:48:47 PM PDT 24 207542292 ps
T433 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.2157557442 Aug 17 04:49:01 PM PDT 24 Aug 17 04:49:04 PM PDT 24 2538936067 ps
T434 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.4026554257 Aug 17 04:48:55 PM PDT 24 Aug 17 04:48:57 PM PDT 24 314782850 ps
T143 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.2868813977 Aug 17 04:49:10 PM PDT 24 Aug 17 04:49:18 PM PDT 24 890855489 ps
T435 /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.705654067 Aug 17 04:49:10 PM PDT 24 Aug 17 04:49:14 PM PDT 24 164767399 ps
T436 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.1938057911 Aug 17 04:49:03 PM PDT 24 Aug 17 04:49:06 PM PDT 24 96327022 ps
T437 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.3053245932 Aug 17 04:49:00 PM PDT 24 Aug 17 04:49:13 PM PDT 24 9147403334 ps
T438 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.2697919667 Aug 17 04:48:51 PM PDT 24 Aug 17 04:48:53 PM PDT 24 505559296 ps
T439 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.804058186 Aug 17 04:49:09 PM PDT 24 Aug 17 04:49:19 PM PDT 24 13297717048 ps
T440 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2684844100 Aug 17 04:49:06 PM PDT 24 Aug 17 04:49:08 PM PDT 24 232209470 ps
T441 /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.3412506334 Aug 17 04:48:56 PM PDT 24 Aug 17 04:49:32 PM PDT 24 2256416698 ps
T442 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.3982323718 Aug 17 04:48:46 PM PDT 24 Aug 17 04:48:50 PM PDT 24 307892191 ps
T443 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.2194530392 Aug 17 04:48:54 PM PDT 24 Aug 17 04:48:56 PM PDT 24 398722905 ps
T444 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.1444573825 Aug 17 04:48:48 PM PDT 24 Aug 17 04:48:49 PM PDT 24 160443400 ps
T445 /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1601263608 Aug 17 04:49:02 PM PDT 24 Aug 17 04:49:06 PM PDT 24 508056319 ps
T446 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.2308218537 Aug 17 04:48:47 PM PDT 24 Aug 17 04:51:08 PM PDT 24 93790962565 ps
T447 /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.3492035688 Aug 17 04:49:11 PM PDT 24 Aug 17 04:49:20 PM PDT 24 875062641 ps
T448 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.3200580131 Aug 17 04:49:17 PM PDT 24 Aug 17 04:49:20 PM PDT 24 114098082 ps
T449 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3981181267 Aug 17 04:49:13 PM PDT 24 Aug 17 04:49:23 PM PDT 24 2365580805 ps
T450 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.288308902 Aug 17 04:49:03 PM PDT 24 Aug 17 04:49:05 PM PDT 24 91881803 ps
T451 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.4144616622 Aug 17 04:49:00 PM PDT 24 Aug 17 04:49:02 PM PDT 24 1214578207 ps
T452 /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.4085545048 Aug 17 04:48:47 PM PDT 24 Aug 17 04:48:49 PM PDT 24 292856090 ps
T453 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.3452868764 Aug 17 04:48:54 PM PDT 24 Aug 17 04:48:55 PM PDT 24 69212944 ps
T454 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.2870207677 Aug 17 04:49:03 PM PDT 24 Aug 17 04:49:06 PM PDT 24 189671124 ps
T455 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.3635585052 Aug 17 04:49:13 PM PDT 24 Aug 17 04:49:15 PM PDT 24 441090477 ps
T456 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.3955243708 Aug 17 04:48:54 PM PDT 24 Aug 17 04:48:56 PM PDT 24 267553899 ps
T457 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.958306292 Aug 17 04:48:58 PM PDT 24 Aug 17 04:49:02 PM PDT 24 207562464 ps
T199 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.3347969017 Aug 17 04:48:59 PM PDT 24 Aug 17 04:49:08 PM PDT 24 527034528 ps
T458 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.830965199 Aug 17 04:48:55 PM PDT 24 Aug 17 04:49:18 PM PDT 24 8787387980 ps
T459 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.3544377881 Aug 17 04:49:06 PM PDT 24 Aug 17 04:49:12 PM PDT 24 285925804 ps
T460 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.1107571993 Aug 17 04:49:01 PM PDT 24 Aug 17 04:49:12 PM PDT 24 2406933000 ps
T461 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.4099974347 Aug 17 04:48:53 PM PDT 24 Aug 17 04:48:53 PM PDT 24 54125220 ps
T462 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3969313637 Aug 17 04:48:59 PM PDT 24 Aug 17 04:49:01 PM PDT 24 743527053 ps
T463 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.3199821173 Aug 17 04:48:59 PM PDT 24 Aug 17 04:49:00 PM PDT 24 82202293 ps
T464 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.1467686933 Aug 17 04:49:13 PM PDT 24 Aug 17 04:49:20 PM PDT 24 663192845 ps
T465 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.164720823 Aug 17 04:49:02 PM PDT 24 Aug 17 04:49:21 PM PDT 24 6555674521 ps
T466 /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.2612088254 Aug 17 04:49:06 PM PDT 24 Aug 17 04:49:10 PM PDT 24 88802531 ps
T467 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.2861090037 Aug 17 04:49:11 PM PDT 24 Aug 17 04:49:14 PM PDT 24 296679298 ps
T468 /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3382236992 Aug 17 04:49:09 PM PDT 24 Aug 17 04:49:12 PM PDT 24 156836037 ps
T469 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.3437193747 Aug 17 04:49:00 PM PDT 24 Aug 17 04:49:02 PM PDT 24 206413826 ps
T470 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.4050425967 Aug 17 04:49:03 PM PDT 24 Aug 17 04:49:18 PM PDT 24 5131675603 ps
T471 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.1318694987 Aug 17 04:48:47 PM PDT 24 Aug 17 04:48:48 PM PDT 24 230888254 ps
T472 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.880716278 Aug 17 04:48:47 PM PDT 24 Aug 17 04:48:48 PM PDT 24 347588359 ps
T473 /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.1762074808 Aug 17 04:49:10 PM PDT 24 Aug 17 04:49:14 PM PDT 24 276213955 ps
T474 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.2023610825 Aug 17 04:48:57 PM PDT 24 Aug 17 04:48:58 PM PDT 24 518183015 ps
T475 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.3525266899 Aug 17 04:49:00 PM PDT 24 Aug 17 04:49:00 PM PDT 24 130690140 ps
T476 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3283443500 Aug 17 04:48:48 PM PDT 24 Aug 17 04:48:55 PM PDT 24 24701244132 ps
T477 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.652389375 Aug 17 04:48:56 PM PDT 24 Aug 17 04:50:01 PM PDT 24 43481023778 ps
T478 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.1648759319 Aug 17 04:48:51 PM PDT 24 Aug 17 04:48:58 PM PDT 24 623996371 ps
T100 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2114085780 Aug 17 04:49:07 PM PDT 24 Aug 17 04:49:10 PM PDT 24 126627966 ps
T479 /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.1883643924 Aug 17 04:49:07 PM PDT 24 Aug 17 04:49:40 PM PDT 24 17237347600 ps
T480 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.621654244 Aug 17 04:49:10 PM PDT 24 Aug 17 04:49:30 PM PDT 24 4636455321 ps
T481 /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.115148344 Aug 17 04:49:03 PM PDT 24 Aug 17 04:49:07 PM PDT 24 164943306 ps
T482 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.4182656350 Aug 17 04:49:16 PM PDT 24 Aug 17 04:50:42 PM PDT 24 122479639674 ps
T149 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1204212373 Aug 17 04:48:46 PM PDT 24 Aug 17 04:49:53 PM PDT 24 1180594418 ps
T483 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3472170583 Aug 17 04:49:18 PM PDT 24 Aug 17 04:49:29 PM PDT 24 14517956485 ps

Test location /workspace/coverage/default/2.rv_dm_stress_all_with_rand_reset.3751317029
Short name T5
Test name
Test status
Simulation time 8615927887 ps
CPU time 54.93 seconds
Started Aug 17 04:49:44 PM PDT 24
Finished Aug 17 04:50:39 PM PDT 24
Peak memory 221596 kb
Host smart-b5529a72-ee75-4dc7-a63f-4581cc1f9755
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751317029 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all_with_rand_reset.3751317029
Directory /workspace/2.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.4139934980
Short name T28
Test name
Test status
Simulation time 10363748438 ps
CPU time 16.28 seconds
Started Aug 17 04:50:03 PM PDT 24
Finished Aug 17 04:50:19 PM PDT 24
Peak memory 215664 kb
Host smart-2670e8b6-1ba5-4c0c-8d20-1407f0a30e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139934980 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.4139934980
Directory /workspace/8.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_stress_all_with_rand_reset.2845847170
Short name T101
Test name
Test status
Simulation time 4259979415 ps
CPU time 71.82 seconds
Started Aug 17 04:49:38 PM PDT 24
Finished Aug 17 04:50:50 PM PDT 24
Peak memory 218628 kb
Host smart-2191a950-f817-44ea-b166-30e6dc21a335
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845847170 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all_with_rand_reset.2845847170
Directory /workspace/5.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.3382793283
Short name T172
Test name
Test status
Simulation time 8140381108 ps
CPU time 20.36 seconds
Started Aug 17 04:48:52 PM PDT 24
Finished Aug 17 04:49:12 PM PDT 24
Peak memory 221972 kb
Host smart-d2a7ab0a-580c-4748-83e2-0e5e9f6a517d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382793283 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.3382793283
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.878765732
Short name T95
Test name
Test status
Simulation time 5915289545 ps
CPU time 7.29 seconds
Started Aug 17 04:49:14 PM PDT 24
Finished Aug 17 04:49:22 PM PDT 24
Peak memory 205288 kb
Host smart-56476f28-8630-4452-a8f1-35453f6fe755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878765732 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.878765732
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/8.rv_dm_stress_all_with_rand_reset.1768069983
Short name T82
Test name
Test status
Simulation time 1990901269 ps
CPU time 20.61 seconds
Started Aug 17 04:49:50 PM PDT 24
Finished Aug 17 04:50:11 PM PDT 24
Peak memory 221548 kb
Host smart-4191fe2c-2892-4a42-9f0a-444e86d21160
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768069983 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all_with_rand_reset.1768069983
Directory /workspace/8.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.3527549251
Short name T30
Test name
Test status
Simulation time 10294877298 ps
CPU time 18.56 seconds
Started Aug 17 04:49:34 PM PDT 24
Finished Aug 17 04:49:52 PM PDT 24
Peak memory 213588 kb
Host smart-38ece18e-e248-4283-a585-76bf0450cbd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527549251 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.3527549251
Directory /workspace/1.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_buffered_enable.2736171546
Short name T59
Test name
Test status
Simulation time 249883903 ps
CPU time 1.16 seconds
Started Aug 17 04:49:41 PM PDT 24
Finished Aug 17 04:49:43 PM PDT 24
Peak memory 226400 kb
Host smart-a2226abc-cc53-4c80-a46a-01ff4cf41a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736171546 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_buffered_enable.2736171546
Directory /workspace/3.rv_dm_buffered_enable/latest

Test location /workspace/coverage/default/3.rv_dm_stress_all_with_rand_reset.4161234045
Short name T56
Test name
Test status
Simulation time 11584417820 ps
CPU time 90.15 seconds
Started Aug 17 04:49:42 PM PDT 24
Finished Aug 17 04:51:12 PM PDT 24
Peak memory 221672 kb
Host smart-4d048517-6f07-4963-a035-3f73c7bc6baf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161234045 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all_with_rand_reset.4161234045
Directory /workspace/3.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2114085780
Short name T100
Test name
Test status
Simulation time 126627966 ps
CPU time 3 seconds
Started Aug 17 04:49:07 PM PDT 24
Finished Aug 17 04:49:10 PM PDT 24
Peak memory 218768 kb
Host smart-0ae369ab-b209-4f1c-becd-2235bb4ea866
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114085780 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.2114085780
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/26.rv_dm_stress_all.643013153
Short name T37
Test name
Test status
Simulation time 1710340223 ps
CPU time 2.51 seconds
Started Aug 17 04:49:54 PM PDT 24
Finished Aug 17 04:49:56 PM PDT 24
Peak memory 205188 kb
Host smart-9bea8a0a-569a-40e8-abb2-2472bc894742
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643013153 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.643013153
Directory /workspace/26.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_scanmode.1136504510
Short name T94
Test name
Test status
Simulation time 15339358 ps
CPU time 0.69 seconds
Started Aug 17 04:49:25 PM PDT 24
Finished Aug 17 04:49:26 PM PDT 24
Peak memory 204908 kb
Host smart-3813204e-610b-4047-a4e9-4f857ee42933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136504510 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_scanmode_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_scanmode.1136504510
Directory /workspace/0.rv_dm_scanmode/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.3163383266
Short name T33
Test name
Test status
Simulation time 41715697 ps
CPU time 0.81 seconds
Started Aug 17 04:49:54 PM PDT 24
Finished Aug 17 04:49:55 PM PDT 24
Peak memory 204988 kb
Host smart-4e7a4b5e-7471-46b8-8a30-82c24faea2ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163383266 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.3163383266
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1594697642
Short name T387
Test name
Test status
Simulation time 692465936 ps
CPU time 2.98 seconds
Started Aug 17 04:48:43 PM PDT 24
Finished Aug 17 04:48:47 PM PDT 24
Peak memory 213688 kb
Host smart-fa1bc861-ab4e-470e-ada5-c4af9c3cebfc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594697642 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.1594697642
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/9.rv_dm_stress_all_with_rand_reset.1925535379
Short name T3
Test name
Test status
Simulation time 900465893 ps
CPU time 22.89 seconds
Started Aug 17 04:49:49 PM PDT 24
Finished Aug 17 04:50:12 PM PDT 24
Peak memory 221612 kb
Host smart-1bc770ce-1b3f-4f74-afdb-96ee7ba7b8c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925535379 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all_with_rand_reset.1925535379
Directory /workspace/9.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.rv_dm_sba_debug_disabled.777098508
Short name T91
Test name
Test status
Simulation time 4986124524 ps
CPU time 8.86 seconds
Started Aug 17 04:49:19 PM PDT 24
Finished Aug 17 04:49:27 PM PDT 24
Peak memory 205184 kb
Host smart-9bc53d42-134e-4021-aa1e-15bffc916312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777098508 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.777098508
Directory /workspace/0.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.3023171403
Short name T67
Test name
Test status
Simulation time 413360832 ps
CPU time 1.48 seconds
Started Aug 17 04:49:38 PM PDT 24
Finished Aug 17 04:49:40 PM PDT 24
Peak memory 229544 kb
Host smart-30eb5cc0-b838-4fe7-ac1e-0d763c840146
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023171403 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.3023171403
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/27.rv_dm_stress_all.1835572634
Short name T19
Test name
Test status
Simulation time 2171425428 ps
CPU time 4.15 seconds
Started Aug 17 04:49:55 PM PDT 24
Finished Aug 17 04:49:59 PM PDT 24
Peak memory 205232 kb
Host smart-1fa85b96-da48-40e9-be16-787552ddeb8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835572634 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.1835572634
Directory /workspace/27.rv_dm_stress_all/latest

Test location /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.1259174666
Short name T309
Test name
Test status
Simulation time 2872660543 ps
CPU time 5.36 seconds
Started Aug 17 04:49:58 PM PDT 24
Finished Aug 17 04:50:03 PM PDT 24
Peak memory 213596 kb
Host smart-bbe8cc7b-16c5-47ff-8dcc-575e80a5b29f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259174666 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.1259174666
Directory /workspace/17.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.2088100682
Short name T127
Test name
Test status
Simulation time 321664708 ps
CPU time 2.57 seconds
Started Aug 17 04:49:13 PM PDT 24
Finished Aug 17 04:49:16 PM PDT 24
Peak memory 213684 kb
Host smart-4b8928ad-3d6e-4ce9-8dd2-2abcada08bc1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088100682 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.2088100682
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/default/38.rv_dm_stress_all.2171869081
Short name T8
Test name
Test status
Simulation time 6806569775 ps
CPU time 6.21 seconds
Started Aug 17 04:49:54 PM PDT 24
Finished Aug 17 04:50:01 PM PDT 24
Peak memory 205228 kb
Host smart-38d2dd16-53df-4e9b-a0c5-b39359e1b542
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171869081 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.2171869081
Directory /workspace/38.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.3003009372
Short name T16
Test name
Test status
Simulation time 316921192 ps
CPU time 0.91 seconds
Started Aug 17 04:49:20 PM PDT 24
Finished Aug 17 04:49:21 PM PDT 24
Peak memory 204904 kb
Host smart-53ba0412-6973-4601-8b75-deb7c7d937fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003009372 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.3003009372
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.2783234200
Short name T191
Test name
Test status
Simulation time 5734764691 ps
CPU time 20.82 seconds
Started Aug 17 04:48:44 PM PDT 24
Finished Aug 17 04:49:05 PM PDT 24
Peak memory 221864 kb
Host smart-d2c3e010-441c-45c1-ac38-62a5466e28d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783234200 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.2783234200
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_dmi_failed_op.589213432
Short name T62
Test name
Test status
Simulation time 146444367 ps
CPU time 0.86 seconds
Started Aug 17 04:49:17 PM PDT 24
Finished Aug 17 04:49:18 PM PDT 24
Peak memory 204872 kb
Host smart-deeb0a4d-8f76-4e00-a858-730f05411716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589213432 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dmi_failed_op.589213432
Directory /workspace/0.rv_dm_dmi_failed_op/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.336172807
Short name T138
Test name
Test status
Simulation time 5193319211 ps
CPU time 29.34 seconds
Started Aug 17 04:48:46 PM PDT 24
Finished Aug 17 04:49:15 PM PDT 24
Peak memory 205576 kb
Host smart-064dfa03-3a95-4b1c-b20b-07254821c851
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336172807 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.rv_dm_csr_aliasing.336172807
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.926499585
Short name T38
Test name
Test status
Simulation time 50051359 ps
CPU time 0.89 seconds
Started Aug 17 04:49:34 PM PDT 24
Finished Aug 17 04:49:35 PM PDT 24
Peak memory 213200 kb
Host smart-635c3c4d-3c8f-4398-88a5-f3cc6e08052d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926499585 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.926499585
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/23.rv_dm_stress_all.64656845
Short name T40
Test name
Test status
Simulation time 3990023887 ps
CPU time 6.88 seconds
Started Aug 17 04:49:56 PM PDT 24
Finished Aug 17 04:50:02 PM PDT 24
Peak memory 213472 kb
Host smart-029c97e4-7d2f-4494-b5da-dec9a53425a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64656845 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.64656845
Directory /workspace/23.rv_dm_stress_all/latest

Test location /workspace/coverage/default/2.rv_dm_sparse_lc_gate_fsm.2928820571
Short name T55
Test name
Test status
Simulation time 205885195 ps
CPU time 0.92 seconds
Started Aug 17 04:49:45 PM PDT 24
Finished Aug 17 04:49:46 PM PDT 24
Peak memory 213272 kb
Host smart-bc9c98e2-ec5f-4c80-a778-dc7272e3b3a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928820571 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sparse_lc_gate_fsm.2928820571
Directory /workspace/2.rv_dm_sparse_lc_gate_fsm/latest

Test location /workspace/coverage/default/0.rv_dm_abstractcmd_status.3523315638
Short name T51
Test name
Test status
Simulation time 478279765 ps
CPU time 0.8 seconds
Started Aug 17 04:49:38 PM PDT 24
Finished Aug 17 04:49:39 PM PDT 24
Peak memory 204932 kb
Host smart-f2a45b12-c6a2-4a73-9a35-4efc61effff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523315638 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.3523315638
Directory /workspace/0.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.1827087584
Short name T181
Test name
Test status
Simulation time 1934505572 ps
CPU time 6.53 seconds
Started Aug 17 04:49:54 PM PDT 24
Finished Aug 17 04:50:01 PM PDT 24
Peak memory 213564 kb
Host smart-5353c9f8-0ffc-4c46-864c-47693e20110e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827087584 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.1827087584
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.2067751843
Short name T136
Test name
Test status
Simulation time 192164435 ps
CPU time 6.72 seconds
Started Aug 17 04:48:48 PM PDT 24
Finished Aug 17 04:48:55 PM PDT 24
Peak memory 205368 kb
Host smart-314db109-f180-4e63-90bc-ccd8f114660d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067751843 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.2067751843
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.3064812957
Short name T196
Test name
Test status
Simulation time 9610573252 ps
CPU time 10.62 seconds
Started Aug 17 04:49:07 PM PDT 24
Finished Aug 17 04:49:18 PM PDT 24
Peak memory 221848 kb
Host smart-4ab88f4d-fc7f-407f-bd9b-d1f9d1b914cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064812957 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.3
064812957
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.3306221432
Short name T316
Test name
Test status
Simulation time 6974634449 ps
CPU time 19.34 seconds
Started Aug 17 04:49:55 PM PDT 24
Finished Aug 17 04:50:15 PM PDT 24
Peak memory 214384 kb
Host smart-dd2713b9-a1ca-49e7-b58f-c37c9bbe0452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306221432 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.3306221432
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3546740002
Short name T107
Test name
Test status
Simulation time 455289426 ps
CPU time 1.01 seconds
Started Aug 17 04:48:47 PM PDT 24
Finished Aug 17 04:48:48 PM PDT 24
Peak memory 205244 kb
Host smart-da9a4912-0e06-4bbc-9936-9b939bfabeb9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546740002 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.3
546740002
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/default/18.rv_dm_stress_all.457845796
Short name T47
Test name
Test status
Simulation time 1805978349 ps
CPU time 5.55 seconds
Started Aug 17 04:49:57 PM PDT 24
Finished Aug 17 04:50:03 PM PDT 24
Peak memory 205168 kb
Host smart-e8ae58d9-3911-4d2c-9266-c85928b626fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457845796 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.457845796
Directory /workspace/18.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.2312528651
Short name T36
Test name
Test status
Simulation time 656931349 ps
CPU time 2.15 seconds
Started Aug 17 04:49:14 PM PDT 24
Finished Aug 17 04:49:16 PM PDT 24
Peak memory 204924 kb
Host smart-9348377d-5d1a-45c0-bf84-0332ce810925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312528651 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.2312528651
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.3744833108
Short name T182
Test name
Test status
Simulation time 6882850600 ps
CPU time 7.56 seconds
Started Aug 17 04:49:45 PM PDT 24
Finished Aug 17 04:49:52 PM PDT 24
Peak memory 213632 kb
Host smart-f0408e8f-8253-4c0d-8683-d2425e70f59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744833108 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.3744833108
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_sparse_lc_gate_fsm.126627988
Short name T57
Test name
Test status
Simulation time 232567865 ps
CPU time 0.93 seconds
Started Aug 17 04:49:26 PM PDT 24
Finished Aug 17 04:49:27 PM PDT 24
Peak memory 213340 kb
Host smart-b4cf7cae-c7ae-4ad8-bd97-760f33d78dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126627988 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sparse_lc_gate_fsm.126627988
Directory /workspace/0.rv_dm_sparse_lc_gate_fsm/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.325160065
Short name T111
Test name
Test status
Simulation time 12394507255 ps
CPU time 9.49 seconds
Started Aug 17 04:49:25 PM PDT 24
Finished Aug 17 04:49:34 PM PDT 24
Peak memory 214684 kb
Host smart-b3d39008-9eb1-4d0c-8ad1-d616ca338b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325160065 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.325160065
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1204212373
Short name T149
Test name
Test status
Simulation time 1180594418 ps
CPU time 66.46 seconds
Started Aug 17 04:48:46 PM PDT 24
Finished Aug 17 04:49:53 PM PDT 24
Peak memory 213796 kb
Host smart-187b7f5f-50f6-4480-b9af-d9417dc28796
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204212373 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.1204212373
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.1163015342
Short name T145
Test name
Test status
Simulation time 14040914088 ps
CPU time 73.18 seconds
Started Aug 17 04:48:41 PM PDT 24
Finished Aug 17 04:49:54 PM PDT 24
Peak memory 213712 kb
Host smart-0984f112-2e41-462b-aeb2-98f55bdafb51
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163015342 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.1163015342
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.2697919667
Short name T438
Test name
Test status
Simulation time 505559296 ps
CPU time 2.53 seconds
Started Aug 17 04:48:51 PM PDT 24
Finished Aug 17 04:48:53 PM PDT 24
Peak memory 213628 kb
Host smart-a8c3d2fa-2e11-4ec9-a1b2-7d208d2f97ca
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697919667 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.2697919667
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.1233237697
Short name T428
Test name
Test status
Simulation time 183220481 ps
CPU time 2.21 seconds
Started Aug 17 04:48:51 PM PDT 24
Finished Aug 17 04:48:53 PM PDT 24
Peak memory 219176 kb
Host smart-83c83409-4b4d-47a5-aae2-ab2aa9912e39
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233237697 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.1233237697
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.2308218537
Short name T446
Test name
Test status
Simulation time 93790962565 ps
CPU time 140.18 seconds
Started Aug 17 04:48:47 PM PDT 24
Finished Aug 17 04:51:08 PM PDT 24
Peak memory 205436 kb
Host smart-f2876369-c26c-4851-bc02-8ea60b21e6b2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308218537 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_aliasing.2308218537
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.2801250445
Short name T350
Test name
Test status
Simulation time 13759972013 ps
CPU time 37.33 seconds
Started Aug 17 04:48:44 PM PDT 24
Finished Aug 17 04:49:22 PM PDT 24
Peak memory 205360 kb
Host smart-f0499793-3964-4680-8fa6-8a9d166a7974
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801250445 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
rv_dm_jtag_dmi_csr_bit_bash.2801250445
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.123531688
Short name T131
Test name
Test status
Simulation time 7176244942 ps
CPU time 6.14 seconds
Started Aug 17 04:48:45 PM PDT 24
Finished Aug 17 04:48:52 PM PDT 24
Peak memory 205516 kb
Host smart-8cc2fb31-7882-4306-ac80-352f68c1a35a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123531688 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr
_hw_reset.123531688
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2918554326
Short name T356
Test name
Test status
Simulation time 7876763892 ps
CPU time 2.57 seconds
Started Aug 17 04:48:56 PM PDT 24
Finished Aug 17 04:48:58 PM PDT 24
Peak memory 205424 kb
Host smart-b537bc93-1bdb-401c-9ed8-3edfe341709d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918554326 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.2
918554326
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.50215916
Short name T347
Test name
Test status
Simulation time 537060230 ps
CPU time 1.05 seconds
Started Aug 17 04:48:43 PM PDT 24
Finished Aug 17 04:48:45 PM PDT 24
Peak memory 205132 kb
Host smart-361ea220-22f2-4042-9c54-efff4c34381f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50215916 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_
aliasing.50215916
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.342593218
Short name T379
Test name
Test status
Simulation time 21762202682 ps
CPU time 8.55 seconds
Started Aug 17 04:48:42 PM PDT 24
Finished Aug 17 04:48:51 PM PDT 24
Peak memory 205388 kb
Host smart-92cca716-3dcd-474a-b767-a9924879830d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342593218 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr
_bit_bash.342593218
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3152942877
Short name T427
Test name
Test status
Simulation time 218634861 ps
CPU time 0.94 seconds
Started Aug 17 04:48:39 PM PDT 24
Finished Aug 17 04:48:40 PM PDT 24
Peak memory 205248 kb
Host smart-abac8975-222f-4524-acc3-853dc7ab783a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152942877 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.3152942877
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1363671272
Short name T348
Test name
Test status
Simulation time 142040492 ps
CPU time 0.74 seconds
Started Aug 17 04:48:39 PM PDT 24
Finished Aug 17 04:48:40 PM PDT 24
Peak memory 205152 kb
Host smart-30b3cc6f-39c9-4e02-bf5b-16bedb9a3683
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363671272 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.1
363671272
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.3452868764
Short name T453
Test name
Test status
Simulation time 69212944 ps
CPU time 0.75 seconds
Started Aug 17 04:48:54 PM PDT 24
Finished Aug 17 04:48:55 PM PDT 24
Peak memory 205080 kb
Host smart-cdd88805-9763-4688-abb9-d992297a7fec
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452868764 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.3452868764
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.1318694987
Short name T471
Test name
Test status
Simulation time 230888254 ps
CPU time 0.71 seconds
Started Aug 17 04:48:47 PM PDT 24
Finished Aug 17 04:48:48 PM PDT 24
Peak memory 205140 kb
Host smart-5a9cd0ee-3c17-435f-becf-f75367fce6f1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318694987 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.1318694987
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.1046475100
Short name T431
Test name
Test status
Simulation time 2428661649 ps
CPU time 31.88 seconds
Started Aug 17 04:48:39 PM PDT 24
Finished Aug 17 04:49:11 PM PDT 24
Peak memory 216732 kb
Host smart-3638ad53-b241-4137-a93b-a798159dec86
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046475100 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.1046475100
Directory /workspace/0.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.521007251
Short name T375
Test name
Test status
Simulation time 119403856 ps
CPU time 4.28 seconds
Started Aug 17 04:48:48 PM PDT 24
Finished Aug 17 04:48:53 PM PDT 24
Peak memory 213692 kb
Host smart-fc13ed3e-5c51-4c39-a546-ab7c862d3211
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521007251 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.521007251
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.1572018817
Short name T417
Test name
Test status
Simulation time 25792291071 ps
CPU time 79.51 seconds
Started Aug 17 04:49:03 PM PDT 24
Finished Aug 17 04:50:22 PM PDT 24
Peak memory 205508 kb
Host smart-c6d0b79e-6d9b-4be0-b6a7-f2c5b8621b28
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572018817 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.1572018817
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.4026554257
Short name T434
Test name
Test status
Simulation time 314782850 ps
CPU time 2.3 seconds
Started Aug 17 04:48:55 PM PDT 24
Finished Aug 17 04:48:57 PM PDT 24
Peak memory 213556 kb
Host smart-7d3cfad1-5939-4b62-a113-bac3f4f3601c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026554257 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.4026554257
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.1946826982
Short name T424
Test name
Test status
Simulation time 144272096 ps
CPU time 3.12 seconds
Started Aug 17 04:48:58 PM PDT 24
Finished Aug 17 04:49:01 PM PDT 24
Peak memory 221388 kb
Host smart-9f43a9c3-f41e-4471-a9a6-6c6225004051
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946826982 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.1946826982
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.3641462726
Short name T408
Test name
Test status
Simulation time 198954153 ps
CPU time 1.55 seconds
Started Aug 17 04:48:48 PM PDT 24
Finished Aug 17 04:48:50 PM PDT 24
Peak memory 218996 kb
Host smart-5d51cbe4-3dcc-4d72-aa5e-edd7eb031f2d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641462726 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.3641462726
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1478610056
Short name T355
Test name
Test status
Simulation time 14393645262 ps
CPU time 13.35 seconds
Started Aug 17 04:48:46 PM PDT 24
Finished Aug 17 04:48:59 PM PDT 24
Peak memory 205528 kb
Host smart-7eb7f3c6-1314-4664-a76e-de894dd1d387
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478610056 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_aliasing.1478610056
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3283443500
Short name T476
Test name
Test status
Simulation time 24701244132 ps
CPU time 6.96 seconds
Started Aug 17 04:48:48 PM PDT 24
Finished Aug 17 04:48:55 PM PDT 24
Peak memory 205428 kb
Host smart-dfe11439-612b-4ba3-9922-8584a1727b88
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283443500 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
rv_dm_jtag_dmi_csr_bit_bash.3283443500
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.943081734
Short name T336
Test name
Test status
Simulation time 1364054124 ps
CPU time 1.77 seconds
Started Aug 17 04:48:58 PM PDT 24
Finished Aug 17 04:49:00 PM PDT 24
Peak memory 205676 kb
Host smart-c7c57e5f-967c-465f-83de-de341a370538
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943081734 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr
_hw_reset.943081734
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1967528463
Short name T388
Test name
Test status
Simulation time 1794817826 ps
CPU time 5.28 seconds
Started Aug 17 04:48:46 PM PDT 24
Finished Aug 17 04:48:52 PM PDT 24
Peak memory 205356 kb
Host smart-405d2553-1d4b-41bd-83ea-e2c71be31611
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967528463 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.1
967528463
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.646867482
Short name T429
Test name
Test status
Simulation time 574909356 ps
CPU time 2.31 seconds
Started Aug 17 04:49:00 PM PDT 24
Finished Aug 17 04:49:02 PM PDT 24
Peak memory 205116 kb
Host smart-5b02a473-9240-415d-b9b0-b53c1a41aa27
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646867482 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr
_aliasing.646867482
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.726220309
Short name T362
Test name
Test status
Simulation time 16214835613 ps
CPU time 21.52 seconds
Started Aug 17 04:48:58 PM PDT 24
Finished Aug 17 04:49:20 PM PDT 24
Peak memory 205328 kb
Host smart-627c3057-d9aa-4790-ad48-9da879e349a3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726220309 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr
_bit_bash.726220309
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.880716278
Short name T472
Test name
Test status
Simulation time 347588359 ps
CPU time 0.96 seconds
Started Aug 17 04:48:47 PM PDT 24
Finished Aug 17 04:48:48 PM PDT 24
Peak memory 205120 kb
Host smart-f093bc17-626a-431b-8d28-748b0079f597
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880716278 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr
_hw_reset.880716278
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.4099974347
Short name T461
Test name
Test status
Simulation time 54125220 ps
CPU time 0.69 seconds
Started Aug 17 04:48:53 PM PDT 24
Finished Aug 17 04:48:53 PM PDT 24
Peak memory 205104 kb
Host smart-f2a8186b-cc7e-4594-82ab-76167af0acff
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099974347 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.4099974347
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.3264104859
Short name T372
Test name
Test status
Simulation time 169558100 ps
CPU time 0.77 seconds
Started Aug 17 04:48:56 PM PDT 24
Finished Aug 17 04:48:57 PM PDT 24
Peak memory 205236 kb
Host smart-7f448bd1-d2d6-4b85-85f7-ded97388891f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264104859 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.3264104859
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.3982323718
Short name T442
Test name
Test status
Simulation time 307892191 ps
CPU time 4.32 seconds
Started Aug 17 04:48:46 PM PDT 24
Finished Aug 17 04:48:50 PM PDT 24
Peak memory 205452 kb
Host smart-d1620f51-7e30-4fa8-b075-f0cf622ad9e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982323718 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_
csr_outstanding.3982323718
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.3412506334
Short name T441
Test name
Test status
Simulation time 2256416698 ps
CPU time 35.19 seconds
Started Aug 17 04:48:56 PM PDT 24
Finished Aug 17 04:49:32 PM PDT 24
Peak memory 221812 kb
Host smart-c383b6f8-f340-469e-8b84-99f05ae68e15
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412506334 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.3412506334
Directory /workspace/1.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.92569548
Short name T361
Test name
Test status
Simulation time 240759283 ps
CPU time 3.7 seconds
Started Aug 17 04:48:52 PM PDT 24
Finished Aug 17 04:48:56 PM PDT 24
Peak memory 213688 kb
Host smart-0b583dae-4291-4044-bc8b-fe03208aafb8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92569548 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.92569548
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3382236992
Short name T468
Test name
Test status
Simulation time 156836037 ps
CPU time 3.1 seconds
Started Aug 17 04:49:09 PM PDT 24
Finished Aug 17 04:49:12 PM PDT 24
Peak memory 219072 kb
Host smart-27ad4e79-4901-402b-81f4-80e592b1e585
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382236992 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.3382236992
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.1698216492
Short name T144
Test name
Test status
Simulation time 624877741 ps
CPU time 2.57 seconds
Started Aug 17 04:49:03 PM PDT 24
Finished Aug 17 04:49:05 PM PDT 24
Peak memory 213644 kb
Host smart-02318dd1-3169-4eff-bafd-23461325946b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698216492 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.1698216492
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.804058186
Short name T439
Test name
Test status
Simulation time 13297717048 ps
CPU time 10.04 seconds
Started Aug 17 04:49:09 PM PDT 24
Finished Aug 17 04:49:19 PM PDT 24
Peak memory 205456 kb
Host smart-81f8495c-b073-4012-8870-688715835d36
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804058186 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
rv_dm_jtag_dmi_csr_bit_bash.804058186
Directory /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.4163497857
Short name T332
Test name
Test status
Simulation time 6126472335 ps
CPU time 3.37 seconds
Started Aug 17 04:49:04 PM PDT 24
Finished Aug 17 04:49:08 PM PDT 24
Peak memory 205548 kb
Host smart-545cd3f5-382a-4127-98d2-7937f4495310
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163497857 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.
4163497857
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1503246918
Short name T419
Test name
Test status
Simulation time 251857633 ps
CPU time 1.51 seconds
Started Aug 17 04:49:09 PM PDT 24
Finished Aug 17 04:49:11 PM PDT 24
Peak memory 205088 kb
Host smart-9e0c555d-bab8-44a6-b977-d3acc5cac977
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503246918 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
1503246918
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.3895954145
Short name T135
Test name
Test status
Simulation time 337848084 ps
CPU time 3.4 seconds
Started Aug 17 04:49:04 PM PDT 24
Finished Aug 17 04:49:07 PM PDT 24
Peak memory 205420 kb
Host smart-cac30615-f9e4-4d9c-a3a4-0d6f8d96422c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895954145 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same
_csr_outstanding.3895954145
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.45880297
Short name T386
Test name
Test status
Simulation time 125825555 ps
CPU time 2.37 seconds
Started Aug 17 04:49:07 PM PDT 24
Finished Aug 17 04:49:09 PM PDT 24
Peak memory 213612 kb
Host smart-3e99548b-cbae-4cb5-b0d6-d545367e675b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45880297 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.45880297
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.609693471
Short name T193
Test name
Test status
Simulation time 1410317328 ps
CPU time 19.4 seconds
Started Aug 17 04:48:59 PM PDT 24
Finished Aug 17 04:49:18 PM PDT 24
Peak memory 213680 kb
Host smart-a4b9662d-b1cb-4e13-b031-2c7022feb635
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609693471 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.609693471
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1110764776
Short name T410
Test name
Test status
Simulation time 166269928 ps
CPU time 2.16 seconds
Started Aug 17 04:49:07 PM PDT 24
Finished Aug 17 04:49:10 PM PDT 24
Peak memory 215676 kb
Host smart-7ae403cd-22af-4348-8d0a-8785bf69b18e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110764776 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.1110764776
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.2974563080
Short name T393
Test name
Test status
Simulation time 177236337 ps
CPU time 2.2 seconds
Started Aug 17 04:48:58 PM PDT 24
Finished Aug 17 04:49:01 PM PDT 24
Peak memory 218416 kb
Host smart-0b4f5c8f-5d23-4f37-9a1a-74062fb7bdbf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974563080 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.2974563080
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.706785297
Short name T370
Test name
Test status
Simulation time 12733058816 ps
CPU time 14.87 seconds
Started Aug 17 04:49:06 PM PDT 24
Finished Aug 17 04:49:21 PM PDT 24
Peak memory 205392 kb
Host smart-0e7e5b20-d3b1-4085-8029-d1f31a27d12d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706785297 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
rv_dm_jtag_dmi_csr_bit_bash.706785297
Directory /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.469217076
Short name T416
Test name
Test status
Simulation time 1650782161 ps
CPU time 4.77 seconds
Started Aug 17 04:49:10 PM PDT 24
Finished Aug 17 04:49:15 PM PDT 24
Peak memory 205232 kb
Host smart-8c15f2a7-b6ba-48ae-b984-d36823a075f3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469217076 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.469217076
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.64245346
Short name T109
Test name
Test status
Simulation time 153960170 ps
CPU time 0.88 seconds
Started Aug 17 04:49:17 PM PDT 24
Finished Aug 17 04:49:18 PM PDT 24
Peak memory 205172 kb
Host smart-d26d6cb3-ea4a-44b6-8f47-dc79c40eee23
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64245346 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.64245346
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.660466846
Short name T129
Test name
Test status
Simulation time 498043629 ps
CPU time 6.37 seconds
Started Aug 17 04:49:02 PM PDT 24
Finished Aug 17 04:49:09 PM PDT 24
Peak memory 205472 kb
Host smart-673724ee-acc6-473c-b9af-0b3189558615
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660466846 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same_
csr_outstanding.660466846
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.1938057911
Short name T436
Test name
Test status
Simulation time 96327022 ps
CPU time 2.29 seconds
Started Aug 17 04:49:03 PM PDT 24
Finished Aug 17 04:49:06 PM PDT 24
Peak memory 213740 kb
Host smart-510769e7-f294-40a9-a5ea-d6745e5ac1a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938057911 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.1938057911
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.3347969017
Short name T199
Test name
Test status
Simulation time 527034528 ps
CPU time 9.06 seconds
Started Aug 17 04:48:59 PM PDT 24
Finished Aug 17 04:49:08 PM PDT 24
Peak memory 221876 kb
Host smart-40e8bc52-6247-423a-aef9-20cff8fd813d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347969017 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.3
347969017
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.2612088254
Short name T466
Test name
Test status
Simulation time 88802531 ps
CPU time 3.93 seconds
Started Aug 17 04:49:06 PM PDT 24
Finished Aug 17 04:49:10 PM PDT 24
Peak memory 221568 kb
Host smart-b2aac920-846c-4395-ae9d-dafd79b84fb1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612088254 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.2612088254
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.1446214520
Short name T137
Test name
Test status
Simulation time 193491286 ps
CPU time 2.22 seconds
Started Aug 17 04:49:04 PM PDT 24
Finished Aug 17 04:49:06 PM PDT 24
Peak memory 213784 kb
Host smart-6a30d14c-cd24-4a62-9f1a-e925d2520ee2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446214520 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.1446214520
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.819932112
Short name T397
Test name
Test status
Simulation time 8433739172 ps
CPU time 14.58 seconds
Started Aug 17 04:49:10 PM PDT 24
Finished Aug 17 04:49:25 PM PDT 24
Peak memory 205756 kb
Host smart-9c677115-5509-402d-855e-5c6f46e8ca0d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819932112 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
rv_dm_jtag_dmi_csr_bit_bash.819932112
Directory /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.3408281714
Short name T413
Test name
Test status
Simulation time 813494691 ps
CPU time 1.99 seconds
Started Aug 17 04:49:04 PM PDT 24
Finished Aug 17 04:49:06 PM PDT 24
Peak memory 205372 kb
Host smart-48d8b21a-9d82-4ef0-995b-fb206b4eee06
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408281714 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.
3408281714
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.769168654
Short name T108
Test name
Test status
Simulation time 558727082 ps
CPU time 2.09 seconds
Started Aug 17 04:49:07 PM PDT 24
Finished Aug 17 04:49:09 PM PDT 24
Peak memory 205088 kb
Host smart-e009e8c6-0167-4fd7-be40-3fa7bf75dfab
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769168654 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.769168654
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1601263608
Short name T445
Test name
Test status
Simulation time 508056319 ps
CPU time 4.1 seconds
Started Aug 17 04:49:02 PM PDT 24
Finished Aug 17 04:49:06 PM PDT 24
Peak memory 205480 kb
Host smart-efe4168f-3722-4e70-b197-808322463efb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601263608 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.1601263608
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.2990205288
Short name T160
Test name
Test status
Simulation time 313598745 ps
CPU time 5.51 seconds
Started Aug 17 04:49:10 PM PDT 24
Finished Aug 17 04:49:15 PM PDT 24
Peak memory 213564 kb
Host smart-ae19296e-8421-48aa-b669-197f9ab6d5a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990205288 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.2990205288
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.249031845
Short name T390
Test name
Test status
Simulation time 1777064787 ps
CPU time 16.99 seconds
Started Aug 17 04:49:03 PM PDT 24
Finished Aug 17 04:49:20 PM PDT 24
Peak memory 213748 kb
Host smart-68950180-d9f9-470c-bc46-53466671c85c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249031845 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.249031845
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3814600844
Short name T99
Test name
Test status
Simulation time 208631363 ps
CPU time 3.06 seconds
Started Aug 17 04:49:02 PM PDT 24
Finished Aug 17 04:49:05 PM PDT 24
Peak memory 218688 kb
Host smart-8058da58-e9a2-40a6-9847-43e61c215a6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814600844 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.3814600844
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.906920881
Short name T150
Test name
Test status
Simulation time 110099504 ps
CPU time 2.16 seconds
Started Aug 17 04:48:58 PM PDT 24
Finished Aug 17 04:49:00 PM PDT 24
Peak memory 219232 kb
Host smart-636707fc-ec6e-4e5a-a8a2-0de188e11d04
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906920881 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.906920881
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.4050425967
Short name T470
Test name
Test status
Simulation time 5131675603 ps
CPU time 15.09 seconds
Started Aug 17 04:49:03 PM PDT 24
Finished Aug 17 04:49:18 PM PDT 24
Peak memory 205408 kb
Host smart-ceafad80-8f60-4d7d-aab2-2577110f1877
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050425967 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.rv_dm_jtag_dmi_csr_bit_bash.4050425967
Directory /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.2662924378
Short name T345
Test name
Test status
Simulation time 1142806260 ps
CPU time 2.28 seconds
Started Aug 17 04:49:16 PM PDT 24
Finished Aug 17 04:49:18 PM PDT 24
Peak memory 205368 kb
Host smart-0027ca57-808e-4e7d-8ad4-5729f17d7be6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662924378 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
2662924378
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.3091586545
Short name T351
Test name
Test status
Simulation time 358015550 ps
CPU time 1.15 seconds
Started Aug 17 04:49:06 PM PDT 24
Finished Aug 17 04:49:07 PM PDT 24
Peak memory 205544 kb
Host smart-86838dbd-7bab-48ba-b835-d596f3364ede
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091586545 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
3091586545
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.1762074808
Short name T473
Test name
Test status
Simulation time 276213955 ps
CPU time 4.21 seconds
Started Aug 17 04:49:10 PM PDT 24
Finished Aug 17 04:49:14 PM PDT 24
Peak memory 205416 kb
Host smart-abf8bb80-0566-4069-8a67-402f0fc44d07
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762074808 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.1762074808
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.3544377881
Short name T459
Test name
Test status
Simulation time 285925804 ps
CPU time 5.45 seconds
Started Aug 17 04:49:06 PM PDT 24
Finished Aug 17 04:49:12 PM PDT 24
Peak memory 213704 kb
Host smart-3d8b76e3-75e1-4065-aabb-eca2e32e8d89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544377881 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.3544377881
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.2682201177
Short name T192
Test name
Test status
Simulation time 4815285927 ps
CPU time 18.74 seconds
Started Aug 17 04:49:03 PM PDT 24
Finished Aug 17 04:49:22 PM PDT 24
Peak memory 213744 kb
Host smart-3d6893cd-964d-4e89-83ee-8e93176a2aea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682201177 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.2
682201177
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3984526916
Short name T105
Test name
Test status
Simulation time 128843773 ps
CPU time 1.79 seconds
Started Aug 17 04:49:11 PM PDT 24
Finished Aug 17 04:49:13 PM PDT 24
Peak memory 215144 kb
Host smart-aa4ed096-e657-4e75-bed9-609ba39784ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984526916 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.3984526916
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.2870207677
Short name T454
Test name
Test status
Simulation time 189671124 ps
CPU time 2.64 seconds
Started Aug 17 04:49:03 PM PDT 24
Finished Aug 17 04:49:06 PM PDT 24
Peak memory 219408 kb
Host smart-d64e2eb2-e0de-4984-bf9a-99c35b2e3f19
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870207677 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.2870207677
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.1811746621
Short name T366
Test name
Test status
Simulation time 56904280 ps
CPU time 0.69 seconds
Started Aug 17 04:49:01 PM PDT 24
Finished Aug 17 04:49:02 PM PDT 24
Peak memory 205124 kb
Host smart-d65d3cc9-4ec0-40c5-845a-f7b0157c145b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811746621 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.rv_dm_jtag_dmi_csr_bit_bash.1811746621
Directory /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.2948016375
Short name T352
Test name
Test status
Simulation time 3075267679 ps
CPU time 8.32 seconds
Started Aug 17 04:49:06 PM PDT 24
Finished Aug 17 04:49:15 PM PDT 24
Peak memory 205152 kb
Host smart-1168ed17-564c-4b5a-a034-2e009eb392e6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948016375 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
2948016375
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2684844100
Short name T440
Test name
Test status
Simulation time 232209470 ps
CPU time 1.29 seconds
Started Aug 17 04:49:06 PM PDT 24
Finished Aug 17 04:49:08 PM PDT 24
Peak memory 204904 kb
Host smart-01f0c512-b48e-41ac-a6fa-e257afdb2b39
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684844100 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
2684844100
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3671960091
Short name T152
Test name
Test status
Simulation time 508482890 ps
CPU time 7.78 seconds
Started Aug 17 04:49:10 PM PDT 24
Finished Aug 17 04:49:18 PM PDT 24
Peak memory 205436 kb
Host smart-70b8e910-5707-4de1-bd0c-70b6156f178f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671960091 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.3671960091
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.288308902
Short name T450
Test name
Test status
Simulation time 91881803 ps
CPU time 2.07 seconds
Started Aug 17 04:49:03 PM PDT 24
Finished Aug 17 04:49:05 PM PDT 24
Peak memory 213672 kb
Host smart-c50d948f-e8b8-410e-859c-d57e2ea11ff5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288308902 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.288308902
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3981181267
Short name T449
Test name
Test status
Simulation time 2365580805 ps
CPU time 10.45 seconds
Started Aug 17 04:49:13 PM PDT 24
Finished Aug 17 04:49:23 PM PDT 24
Peak memory 221880 kb
Host smart-7d215510-cfa5-412c-942f-63ff0f26e1aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981181267 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.3
981181267
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1577209456
Short name T104
Test name
Test status
Simulation time 57104513 ps
CPU time 2.57 seconds
Started Aug 17 04:49:11 PM PDT 24
Finished Aug 17 04:49:14 PM PDT 24
Peak memory 217728 kb
Host smart-c13ec610-3b55-4f0f-b3e8-dfdae3312bf0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577209456 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.1577209456
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.3085296691
Short name T120
Test name
Test status
Simulation time 220899748 ps
CPU time 1.71 seconds
Started Aug 17 04:49:16 PM PDT 24
Finished Aug 17 04:49:18 PM PDT 24
Peak memory 219096 kb
Host smart-39f9eada-521f-4625-801b-6f46c4dacfb4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085296691 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.3085296691
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.1847425023
Short name T326
Test name
Test status
Simulation time 5970283880 ps
CPU time 8.49 seconds
Started Aug 17 04:49:09 PM PDT 24
Finished Aug 17 04:49:18 PM PDT 24
Peak memory 205416 kb
Host smart-82659f57-a4a6-4bc1-806c-7691fe04e789
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847425023 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.rv_dm_jtag_dmi_csr_bit_bash.1847425023
Directory /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3472170583
Short name T483
Test name
Test status
Simulation time 14517956485 ps
CPU time 10.65 seconds
Started Aug 17 04:49:18 PM PDT 24
Finished Aug 17 04:49:29 PM PDT 24
Peak memory 205436 kb
Host smart-f87556cb-17eb-4757-8394-0c98e83973dc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472170583 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
3472170583
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.4048184206
Short name T391
Test name
Test status
Simulation time 375003974 ps
CPU time 1.79 seconds
Started Aug 17 04:49:00 PM PDT 24
Finished Aug 17 04:49:02 PM PDT 24
Peak memory 205120 kb
Host smart-bd070c59-24d8-4a7d-b99a-f4ff9d7d02b2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048184206 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
4048184206
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.1943198721
Short name T123
Test name
Test status
Simulation time 425467293 ps
CPU time 3.94 seconds
Started Aug 17 04:49:16 PM PDT 24
Finished Aug 17 04:49:20 PM PDT 24
Peak memory 205424 kb
Host smart-d4986b5b-197d-45bb-91b2-777cf2790b1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943198721 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.1943198721
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.450199094
Short name T357
Test name
Test status
Simulation time 167801646 ps
CPU time 3.44 seconds
Started Aug 17 04:49:10 PM PDT 24
Finished Aug 17 04:49:14 PM PDT 24
Peak memory 213616 kb
Host smart-a013d994-02a3-44d8-89e2-4d0529ac983f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450199094 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.450199094
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.3051956918
Short name T374
Test name
Test status
Simulation time 3623091465 ps
CPU time 21.11 seconds
Started Aug 17 04:49:10 PM PDT 24
Finished Aug 17 04:49:31 PM PDT 24
Peak memory 221812 kb
Host smart-ed44fcbe-acf0-4386-8121-38ecc08335eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051956918 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.3
051956918
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.2861090037
Short name T467
Test name
Test status
Simulation time 296679298 ps
CPU time 3.07 seconds
Started Aug 17 04:49:11 PM PDT 24
Finished Aug 17 04:49:14 PM PDT 24
Peak memory 221224 kb
Host smart-e71af360-b91d-4d61-bcd8-106bdd07525f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861090037 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.2861090037
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.3920441878
Short name T407
Test name
Test status
Simulation time 183198351 ps
CPU time 1.83 seconds
Started Aug 17 04:49:10 PM PDT 24
Finished Aug 17 04:49:12 PM PDT 24
Peak memory 218660 kb
Host smart-424cf5e2-b0c9-4e65-bfbb-ae8f3f12755a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920441878 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.3920441878
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.4182656350
Short name T482
Test name
Test status
Simulation time 122479639674 ps
CPU time 86.15 seconds
Started Aug 17 04:49:16 PM PDT 24
Finished Aug 17 04:50:42 PM PDT 24
Peak memory 205336 kb
Host smart-679b8cf0-e32c-4b2c-a9a7-725ab813ca4e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182656350 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.rv_dm_jtag_dmi_csr_bit_bash.4182656350
Directory /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.2267399400
Short name T329
Test name
Test status
Simulation time 4205730897 ps
CPU time 3.84 seconds
Started Aug 17 04:49:16 PM PDT 24
Finished Aug 17 04:49:20 PM PDT 24
Peak memory 205440 kb
Host smart-8e1f357b-e08a-4ac5-852a-ed91f8dc39fa
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267399400 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
2267399400
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.2503290992
Short name T425
Test name
Test status
Simulation time 188015550 ps
CPU time 1.2 seconds
Started Aug 17 04:49:09 PM PDT 24
Finished Aug 17 04:49:10 PM PDT 24
Peak memory 205124 kb
Host smart-f7e1ab93-790b-4f8f-aa5d-831d6e71b91f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503290992 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
2503290992
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.754127741
Short name T155
Test name
Test status
Simulation time 1534525525 ps
CPU time 7.4 seconds
Started Aug 17 04:49:12 PM PDT 24
Finished Aug 17 04:49:20 PM PDT 24
Peak memory 205352 kb
Host smart-230ffd99-b62f-428c-b066-0b1c7ec52688
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754127741 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same_
csr_outstanding.754127741
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.3313569580
Short name T392
Test name
Test status
Simulation time 759791228 ps
CPU time 5.22 seconds
Started Aug 17 04:49:10 PM PDT 24
Finished Aug 17 04:49:15 PM PDT 24
Peak memory 213572 kb
Host smart-84922d7f-7c2e-450a-9d11-ed0791a0a20c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313569580 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.3313569580
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.621654244
Short name T480
Test name
Test status
Simulation time 4636455321 ps
CPU time 19.92 seconds
Started Aug 17 04:49:10 PM PDT 24
Finished Aug 17 04:49:30 PM PDT 24
Peak memory 221872 kb
Host smart-17a5d49a-2d9a-4a83-a57e-aa90e5847c8f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621654244 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.621654244
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.3513661611
Short name T159
Test name
Test status
Simulation time 123182540 ps
CPU time 1.75 seconds
Started Aug 17 04:49:11 PM PDT 24
Finished Aug 17 04:49:13 PM PDT 24
Peak memory 215216 kb
Host smart-49a86e75-c1ce-4090-9e81-2af669b0b8b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513661611 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.3513661611
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.584749482
Short name T401
Test name
Test status
Simulation time 23284480818 ps
CPU time 70.42 seconds
Started Aug 17 04:49:05 PM PDT 24
Finished Aug 17 04:50:16 PM PDT 24
Peak memory 205328 kb
Host smart-59ea5c15-fed8-44f6-9e8a-71fa910ad916
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584749482 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
rv_dm_jtag_dmi_csr_bit_bash.584749482
Directory /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.2064030958
Short name T377
Test name
Test status
Simulation time 4556333703 ps
CPU time 5.87 seconds
Started Aug 17 04:49:05 PM PDT 24
Finished Aug 17 04:49:11 PM PDT 24
Peak memory 205372 kb
Host smart-4df18874-b3cd-4b33-9ad1-0a34cd61ea10
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064030958 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.
2064030958
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.2368868525
Short name T333
Test name
Test status
Simulation time 756005036 ps
CPU time 2.4 seconds
Started Aug 17 04:49:15 PM PDT 24
Finished Aug 17 04:49:17 PM PDT 24
Peak memory 205140 kb
Host smart-15c5f346-98d0-48de-a923-a03a4da4dbeb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368868525 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.
2368868525
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.1467686933
Short name T464
Test name
Test status
Simulation time 663192845 ps
CPU time 6.17 seconds
Started Aug 17 04:49:13 PM PDT 24
Finished Aug 17 04:49:20 PM PDT 24
Peak memory 205428 kb
Host smart-7e9300ed-e373-4ddd-92af-51491765fb30
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467686933 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.1467686933
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.2670658667
Short name T338
Test name
Test status
Simulation time 2116606946 ps
CPU time 3.81 seconds
Started Aug 17 04:49:11 PM PDT 24
Finished Aug 17 04:49:15 PM PDT 24
Peak memory 213636 kb
Host smart-73d06cff-2c43-416c-8437-6290ca18adb1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670658667 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.2670658667
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.1261333302
Short name T156
Test name
Test status
Simulation time 163345824 ps
CPU time 1.63 seconds
Started Aug 17 04:49:10 PM PDT 24
Finished Aug 17 04:49:12 PM PDT 24
Peak memory 219104 kb
Host smart-ae2c83c0-55f5-4cab-a6c1-3289acb324fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261333302 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.1261333302
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.12065131
Short name T409
Test name
Test status
Simulation time 5365510246 ps
CPU time 9.56 seconds
Started Aug 17 04:49:07 PM PDT 24
Finished Aug 17 04:49:17 PM PDT 24
Peak memory 205388 kb
Host smart-5d725dc3-54d2-4d1d-b62c-9740475e6cb4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12065131 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.r
v_dm_jtag_dmi_csr_bit_bash.12065131
Directory /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.52721785
Short name T396
Test name
Test status
Simulation time 4360108409 ps
CPU time 13.16 seconds
Started Aug 17 04:49:12 PM PDT 24
Finished Aug 17 04:49:26 PM PDT 24
Peak memory 205324 kb
Host smart-e6ba43d5-adab-4620-aba8-708ef07a793f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52721785 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.52721785
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2883955266
Short name T367
Test name
Test status
Simulation time 76847398 ps
CPU time 0.9 seconds
Started Aug 17 04:49:08 PM PDT 24
Finished Aug 17 04:49:09 PM PDT 24
Peak memory 205088 kb
Host smart-b5f30300-1c85-4839-863a-866896a6959b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883955266 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
2883955266
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.2868813977
Short name T143
Test name
Test status
Simulation time 890855489 ps
CPU time 7.5 seconds
Started Aug 17 04:49:10 PM PDT 24
Finished Aug 17 04:49:18 PM PDT 24
Peak memory 205416 kb
Host smart-8641051c-20b8-4b63-830a-024557353674
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868813977 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.2868813977
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.1921010047
Short name T385
Test name
Test status
Simulation time 192540110 ps
CPU time 2.44 seconds
Started Aug 17 04:49:07 PM PDT 24
Finished Aug 17 04:49:09 PM PDT 24
Peak memory 213616 kb
Host smart-ca523a94-f023-47f7-832e-74bfcb32e7db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921010047 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.1921010047
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3912896120
Short name T170
Test name
Test status
Simulation time 2862030534 ps
CPU time 10.01 seconds
Started Aug 17 04:49:10 PM PDT 24
Finished Aug 17 04:49:20 PM PDT 24
Peak memory 213732 kb
Host smart-1da0d088-1183-4c93-b062-03c71ea977db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912896120 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.3
912896120
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.3200580131
Short name T448
Test name
Test status
Simulation time 114098082 ps
CPU time 3.14 seconds
Started Aug 17 04:49:17 PM PDT 24
Finished Aug 17 04:49:20 PM PDT 24
Peak memory 218780 kb
Host smart-bcdd2330-535d-4f39-a5f6-3e6c25e32f83
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200580131 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.3200580131
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.3635585052
Short name T455
Test name
Test status
Simulation time 441090477 ps
CPU time 2.37 seconds
Started Aug 17 04:49:13 PM PDT 24
Finished Aug 17 04:49:15 PM PDT 24
Peak memory 213684 kb
Host smart-6095fb32-40ba-4875-85d7-063f6205b4bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635585052 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.3635585052
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.366598039
Short name T421
Test name
Test status
Simulation time 26410332565 ps
CPU time 66.45 seconds
Started Aug 17 04:49:08 PM PDT 24
Finished Aug 17 04:50:15 PM PDT 24
Peak memory 205468 kb
Host smart-42133d0f-3277-4dec-bf62-d0acc4ed0b6b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366598039 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
rv_dm_jtag_dmi_csr_bit_bash.366598039
Directory /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.3876838102
Short name T373
Test name
Test status
Simulation time 3112678646 ps
CPU time 3.45 seconds
Started Aug 17 04:49:15 PM PDT 24
Finished Aug 17 04:49:19 PM PDT 24
Peak memory 205448 kb
Host smart-fed9d516-8a75-4a29-9c99-01db72319ec8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876838102 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.
3876838102
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.2865658765
Short name T340
Test name
Test status
Simulation time 308843642 ps
CPU time 0.86 seconds
Started Aug 17 04:49:06 PM PDT 24
Finished Aug 17 04:49:07 PM PDT 24
Peak memory 205124 kb
Host smart-e7aaebe0-7bcd-4d36-b391-6f41cdbf183c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865658765 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
2865658765
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.1074881954
Short name T430
Test name
Test status
Simulation time 467680302 ps
CPU time 7.58 seconds
Started Aug 17 04:49:12 PM PDT 24
Finished Aug 17 04:49:20 PM PDT 24
Peak memory 205376 kb
Host smart-53cc2d19-bbb1-449a-918a-a549fdfbcbdd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074881954 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.1074881954
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.705654067
Short name T435
Test name
Test status
Simulation time 164767399 ps
CPU time 3.85 seconds
Started Aug 17 04:49:10 PM PDT 24
Finished Aug 17 04:49:14 PM PDT 24
Peak memory 213608 kb
Host smart-dc99b49d-983e-483f-9506-da99f0638525
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705654067 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.705654067
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.550145986
Short name T190
Test name
Test status
Simulation time 991967602 ps
CPU time 10.14 seconds
Started Aug 17 04:49:17 PM PDT 24
Finished Aug 17 04:49:27 PM PDT 24
Peak memory 221776 kb
Host smart-e99c4b00-dccc-4508-8842-49867f8fc4dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550145986 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.550145986
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.1075607531
Short name T126
Test name
Test status
Simulation time 2468528072 ps
CPU time 33.29 seconds
Started Aug 17 04:48:58 PM PDT 24
Finished Aug 17 04:49:32 PM PDT 24
Peak memory 205484 kb
Host smart-999d88fa-d7e2-4cd6-bd55-3f83a5b3cf6c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075607531 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.1075607531
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.2524087546
Short name T422
Test name
Test status
Simulation time 1468525909 ps
CPU time 54.16 seconds
Started Aug 17 04:48:51 PM PDT 24
Finished Aug 17 04:49:46 PM PDT 24
Peak memory 205492 kb
Host smart-af48ce31-b816-4472-8313-9edf2602ffd1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524087546 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.2524087546
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3969313637
Short name T462
Test name
Test status
Simulation time 743527053 ps
CPU time 1.63 seconds
Started Aug 17 04:48:59 PM PDT 24
Finished Aug 17 04:49:01 PM PDT 24
Peak memory 213584 kb
Host smart-156132cf-1430-4fcd-a8b1-89dacb54e6a5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969313637 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.3969313637
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.4085545048
Short name T452
Test name
Test status
Simulation time 292856090 ps
CPU time 1.99 seconds
Started Aug 17 04:48:47 PM PDT 24
Finished Aug 17 04:48:49 PM PDT 24
Peak memory 216600 kb
Host smart-50270275-c491-4c34-ae47-975857f429fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085545048 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.4085545048
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.1648759319
Short name T478
Test name
Test status
Simulation time 623996371 ps
CPU time 1.62 seconds
Started Aug 17 04:48:51 PM PDT 24
Finished Aug 17 04:48:58 PM PDT 24
Peak memory 213696 kb
Host smart-fdca237d-e31b-4101-8c5b-92caec78f245
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648759319 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.1648759319
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.613158913
Short name T399
Test name
Test status
Simulation time 85660367663 ps
CPU time 239.06 seconds
Started Aug 17 04:48:57 PM PDT 24
Finished Aug 17 04:52:57 PM PDT 24
Peak memory 205384 kb
Host smart-24e4587b-ff59-4f88-8a6f-0e3a30dbbf92
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613158913 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr
_aliasing.613158913
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.1495780842
Short name T339
Test name
Test status
Simulation time 6150962212 ps
CPU time 17.2 seconds
Started Aug 17 04:48:48 PM PDT 24
Finished Aug 17 04:49:05 PM PDT 24
Peak memory 205428 kb
Host smart-43f4b63c-1ff6-4c42-969f-5763b7983a5e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495780842 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
rv_dm_jtag_dmi_csr_bit_bash.1495780842
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.4029950907
Short name T132
Test name
Test status
Simulation time 15617262862 ps
CPU time 4.32 seconds
Started Aug 17 04:48:53 PM PDT 24
Finished Aug 17 04:48:58 PM PDT 24
Peak memory 205436 kb
Host smart-84c04e1f-ad95-4512-88b7-bdea63a8257c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029950907 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.4029950907
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.744370883
Short name T411
Test name
Test status
Simulation time 4589580660 ps
CPU time 4.69 seconds
Started Aug 17 04:49:02 PM PDT 24
Finished Aug 17 04:49:07 PM PDT 24
Peak memory 205424 kb
Host smart-2ec60da5-513f-4739-917d-a52c664c450c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744370883 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.744370883
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.3322775349
Short name T337
Test name
Test status
Simulation time 368168817 ps
CPU time 1.24 seconds
Started Aug 17 04:48:46 PM PDT 24
Finished Aug 17 04:48:47 PM PDT 24
Peak memory 205184 kb
Host smart-92416fbb-b440-4227-ae38-6137411724db
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322775349 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_aliasing.3322775349
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.652389375
Short name T477
Test name
Test status
Simulation time 43481023778 ps
CPU time 64.53 seconds
Started Aug 17 04:48:56 PM PDT 24
Finished Aug 17 04:50:01 PM PDT 24
Peak memory 205376 kb
Host smart-a5735584-4f8f-4980-990c-bb3cbab3ea7e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652389375 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr
_bit_bash.652389375
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.2023610825
Short name T474
Test name
Test status
Simulation time 518183015 ps
CPU time 0.98 seconds
Started Aug 17 04:48:57 PM PDT 24
Finished Aug 17 04:48:58 PM PDT 24
Peak memory 205124 kb
Host smart-c76a37e9-03bb-49e6-801e-3e30fe08c6c7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023610825 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.2023610825
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.1514194055
Short name T363
Test name
Test status
Simulation time 247331250 ps
CPU time 1.37 seconds
Started Aug 17 04:48:46 PM PDT 24
Finished Aug 17 04:48:47 PM PDT 24
Peak memory 205176 kb
Host smart-b825ea7a-1cc3-409d-9a3d-c1eccf0a1498
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514194055 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.1
514194055
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.3654046266
Short name T381
Test name
Test status
Simulation time 42819144 ps
CPU time 0.78 seconds
Started Aug 17 04:48:58 PM PDT 24
Finished Aug 17 04:48:59 PM PDT 24
Peak memory 205192 kb
Host smart-63e0cfaf-5e8e-4a25-afa1-4e22e0cc65e2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654046266 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.3654046266
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.3231983998
Short name T354
Test name
Test status
Simulation time 70785705 ps
CPU time 0.74 seconds
Started Aug 17 04:48:47 PM PDT 24
Finished Aug 17 04:48:48 PM PDT 24
Peak memory 205180 kb
Host smart-a6652ee4-5134-4b84-a888-a011f7a696fd
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231983998 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.3231983998
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.3125946390
Short name T141
Test name
Test status
Simulation time 1761216863 ps
CPU time 7.33 seconds
Started Aug 17 04:48:48 PM PDT 24
Finished Aug 17 04:48:55 PM PDT 24
Peak memory 205468 kb
Host smart-a45702f7-95ed-42f8-a85a-1fab486aa9a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125946390 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.3125946390
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.793053682
Short name T96
Test name
Test status
Simulation time 8510003162 ps
CPU time 72.9 seconds
Started Aug 17 04:48:56 PM PDT 24
Finished Aug 17 04:50:09 PM PDT 24
Peak memory 218412 kb
Host smart-5de77e63-3e8e-408b-8421-bdb542f661e3
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793053682 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.793053682
Directory /workspace/2.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.4268877761
Short name T403
Test name
Test status
Simulation time 570917835 ps
CPU time 3.01 seconds
Started Aug 17 04:48:58 PM PDT 24
Finished Aug 17 04:49:01 PM PDT 24
Peak memory 213620 kb
Host smart-a214a3f1-b694-43a0-978d-ca8342c51518
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268877761 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.4268877761
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.1098174949
Short name T195
Test name
Test status
Simulation time 9190711023 ps
CPU time 16.79 seconds
Started Aug 17 04:48:48 PM PDT 24
Finished Aug 17 04:49:05 PM PDT 24
Peak memory 216572 kb
Host smart-1c926340-7ffb-42a5-8a94-1181107af759
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098174949 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.1098174949
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.258563433
Short name T124
Test name
Test status
Simulation time 4279107114 ps
CPU time 30.65 seconds
Started Aug 17 04:48:50 PM PDT 24
Finished Aug 17 04:49:21 PM PDT 24
Peak memory 205436 kb
Host smart-ca91fecb-cda3-4f9a-8189-1e71d2a567e7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258563433 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.rv_dm_csr_aliasing.258563433
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.2114475661
Short name T147
Test name
Test status
Simulation time 3834895262 ps
CPU time 36.24 seconds
Started Aug 17 04:48:53 PM PDT 24
Finished Aug 17 04:49:30 PM PDT 24
Peak memory 205504 kb
Host smart-86c2f7c5-be4a-4ae6-bccb-4038924780a1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114475661 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.2114475661
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.3007520017
Short name T122
Test name
Test status
Simulation time 141222822 ps
CPU time 1.8 seconds
Started Aug 17 04:48:51 PM PDT 24
Finished Aug 17 04:48:53 PM PDT 24
Peak memory 213568 kb
Host smart-78f148b0-f165-4967-a1c9-68d0a371a47f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007520017 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.3007520017
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.2276914101
Short name T106
Test name
Test status
Simulation time 176040527 ps
CPU time 2.26 seconds
Started Aug 17 04:48:51 PM PDT 24
Finished Aug 17 04:48:54 PM PDT 24
Peak memory 217992 kb
Host smart-a43d2faa-d0ca-4dbf-8e9d-f15e2e631ce3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276914101 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.2276914101
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.2194530392
Short name T443
Test name
Test status
Simulation time 398722905 ps
CPU time 1.69 seconds
Started Aug 17 04:48:54 PM PDT 24
Finished Aug 17 04:48:56 PM PDT 24
Peak memory 218720 kb
Host smart-bfa0c0b2-a140-42dc-bced-2aac906b50cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194530392 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.2194530392
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.3630982587
Short name T395
Test name
Test status
Simulation time 35555385824 ps
CPU time 95.77 seconds
Started Aug 17 04:49:00 PM PDT 24
Finished Aug 17 04:50:36 PM PDT 24
Peak memory 205508 kb
Host smart-5207d0c8-0342-4f6c-8958-765e5ad1f6d9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630982587 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.3630982587
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.2743784501
Short name T398
Test name
Test status
Simulation time 4270820895 ps
CPU time 13.07 seconds
Started Aug 17 04:48:49 PM PDT 24
Finished Aug 17 04:49:02 PM PDT 24
Peak memory 205316 kb
Host smart-17b78da3-2af3-484f-b67e-8c8d2a9329ba
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743784501 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
rv_dm_jtag_dmi_csr_bit_bash.2743784501
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.966399765
Short name T133
Test name
Test status
Simulation time 5397611074 ps
CPU time 16.19 seconds
Started Aug 17 04:48:48 PM PDT 24
Finished Aug 17 04:49:04 PM PDT 24
Peak memory 205388 kb
Host smart-00bd2df4-8bf1-4fc2-90aa-3a8de108fb07
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966399765 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr
_hw_reset.966399765
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.3425439370
Short name T349
Test name
Test status
Simulation time 5423487339 ps
CPU time 8.9 seconds
Started Aug 17 04:48:49 PM PDT 24
Finished Aug 17 04:48:58 PM PDT 24
Peak memory 205356 kb
Host smart-14966a40-e1b3-42aa-b606-b94ba9dcf39b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425439370 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.3
425439370
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.3749963902
Short name T335
Test name
Test status
Simulation time 2285516881 ps
CPU time 2.19 seconds
Started Aug 17 04:48:56 PM PDT 24
Finished Aug 17 04:48:58 PM PDT 24
Peak memory 205180 kb
Host smart-099113d7-1920-432e-9f8d-82931a5a2ffd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749963902 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.3749963902
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.1066911476
Short name T341
Test name
Test status
Simulation time 7609224962 ps
CPU time 19.88 seconds
Started Aug 17 04:48:57 PM PDT 24
Finished Aug 17 04:49:17 PM PDT 24
Peak memory 205452 kb
Host smart-7d2e390b-1613-4cff-bb37-eaa42185fa3b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066911476 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_bit_bash.1066911476
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.3525266899
Short name T475
Test name
Test status
Simulation time 130690140 ps
CPU time 0.83 seconds
Started Aug 17 04:49:00 PM PDT 24
Finished Aug 17 04:49:00 PM PDT 24
Peak memory 205120 kb
Host smart-b1d13a44-b237-4b52-a71a-ea4498224720
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525266899 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_hw_reset.3525266899
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.1504459237
Short name T346
Test name
Test status
Simulation time 284687042 ps
CPU time 1.09 seconds
Started Aug 17 04:48:56 PM PDT 24
Finished Aug 17 04:48:57 PM PDT 24
Peak memory 205140 kb
Host smart-6f3b7399-f361-4609-82d0-6fddc7fe2850
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504459237 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.1
504459237
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.1444573825
Short name T444
Test name
Test status
Simulation time 160443400 ps
CPU time 0.88 seconds
Started Aug 17 04:48:48 PM PDT 24
Finished Aug 17 04:48:49 PM PDT 24
Peak memory 205104 kb
Host smart-e67998e2-c708-431f-b06d-649d004cb371
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444573825 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.1444573825
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.799175161
Short name T376
Test name
Test status
Simulation time 40271226 ps
CPU time 0.68 seconds
Started Aug 17 04:48:49 PM PDT 24
Finished Aug 17 04:48:50 PM PDT 24
Peak memory 205144 kb
Host smart-aa7fff13-eb66-405f-ae64-3ee3883774c4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799175161 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.799175161
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.3140978131
Short name T418
Test name
Test status
Simulation time 1451680611 ps
CPU time 3.75 seconds
Started Aug 17 04:48:48 PM PDT 24
Finished Aug 17 04:48:51 PM PDT 24
Peak memory 205548 kb
Host smart-e2c49c47-243b-4059-8487-5c0d85215ca0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140978131 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_
csr_outstanding.3140978131
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.875949582
Short name T97
Test name
Test status
Simulation time 6212619340 ps
CPU time 48.63 seconds
Started Aug 17 04:48:48 PM PDT 24
Finished Aug 17 04:49:36 PM PDT 24
Peak memory 221632 kb
Host smart-3a4017a7-cf5b-43c1-8eb8-59aad9711594
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875949582 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.875949582
Directory /workspace/3.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.3782224172
Short name T378
Test name
Test status
Simulation time 175136870 ps
CPU time 2.29 seconds
Started Aug 17 04:49:02 PM PDT 24
Finished Aug 17 04:49:04 PM PDT 24
Peak memory 213692 kb
Host smart-903457e4-6f8e-4b6a-9377-31840487a7a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782224172 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.3782224172
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.593779885
Short name T383
Test name
Test status
Simulation time 1499519151 ps
CPU time 10.08 seconds
Started Aug 17 04:48:54 PM PDT 24
Finished Aug 17 04:49:04 PM PDT 24
Peak memory 213772 kb
Host smart-34665913-9b45-4dd6-bf85-5cc6191b49f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593779885 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.593779885
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.4047879458
Short name T139
Test name
Test status
Simulation time 8879438466 ps
CPU time 66.2 seconds
Started Aug 17 04:48:51 PM PDT 24
Finished Aug 17 04:49:58 PM PDT 24
Peak memory 205488 kb
Host smart-a29db1cd-3f92-46fe-8ba4-26b4d7235dde
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047879458 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.4047879458
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.1782628683
Short name T368
Test name
Test status
Simulation time 4935375318 ps
CPU time 33.88 seconds
Started Aug 17 04:49:01 PM PDT 24
Finished Aug 17 04:49:35 PM PDT 24
Peak memory 213740 kb
Host smart-9dd4bf6b-2259-484e-96bc-b6c1c9b61d39
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782628683 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.1782628683
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.3955243708
Short name T456
Test name
Test status
Simulation time 267553899 ps
CPU time 2.09 seconds
Started Aug 17 04:48:54 PM PDT 24
Finished Aug 17 04:48:56 PM PDT 24
Peak memory 213712 kb
Host smart-e46ce104-9c62-493e-a529-db67bb139904
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955243708 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.3955243708
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.945243921
Short name T369
Test name
Test status
Simulation time 64986207 ps
CPU time 2.07 seconds
Started Aug 17 04:49:02 PM PDT 24
Finished Aug 17 04:49:04 PM PDT 24
Peak memory 217220 kb
Host smart-2ad3a0ed-3503-4c5a-96fe-5003a0a45ca3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945243921 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.945243921
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.3199821173
Short name T463
Test name
Test status
Simulation time 82202293 ps
CPU time 1.67 seconds
Started Aug 17 04:48:59 PM PDT 24
Finished Aug 17 04:49:00 PM PDT 24
Peak memory 218700 kb
Host smart-173c17ed-d961-4985-8fb4-d2c4ba6e6026
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199821173 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.3199821173
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.3658199025
Short name T327
Test name
Test status
Simulation time 25491247958 ps
CPU time 15.77 seconds
Started Aug 17 04:49:00 PM PDT 24
Finished Aug 17 04:49:16 PM PDT 24
Peak memory 205380 kb
Host smart-54d5705c-3b56-4b4a-b99e-388ff034ec78
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658199025 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_aliasing.3658199025
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.4152918697
Short name T389
Test name
Test status
Simulation time 34249318105 ps
CPU time 93.1 seconds
Started Aug 17 04:48:55 PM PDT 24
Finished Aug 17 04:50:28 PM PDT 24
Peak memory 205352 kb
Host smart-8f9d870b-1b93-46e6-9622-1033235ca940
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152918697 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
rv_dm_jtag_dmi_csr_bit_bash.4152918697
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.1566015017
Short name T364
Test name
Test status
Simulation time 2289572678 ps
CPU time 6.98 seconds
Started Aug 17 04:49:02 PM PDT 24
Finished Aug 17 04:49:09 PM PDT 24
Peak memory 205460 kb
Host smart-5bae62b3-6c6b-4312-9628-31e7a955719a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566015017 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.1566015017
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.837950795
Short name T359
Test name
Test status
Simulation time 5794504338 ps
CPU time 16.9 seconds
Started Aug 17 04:49:02 PM PDT 24
Finished Aug 17 04:49:19 PM PDT 24
Peak memory 205480 kb
Host smart-bb15aee8-cb92-4882-83f0-2ace3e4fe13a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837950795 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.837950795
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.2157557442
Short name T433
Test name
Test status
Simulation time 2538936067 ps
CPU time 3.35 seconds
Started Aug 17 04:49:01 PM PDT 24
Finished Aug 17 04:49:04 PM PDT 24
Peak memory 205212 kb
Host smart-7ab0ecbd-a456-4b4f-9822-bc63c8958d87
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157557442 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_aliasing.2157557442
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.917099352
Short name T358
Test name
Test status
Simulation time 21295617265 ps
CPU time 35.99 seconds
Started Aug 17 04:48:48 PM PDT 24
Finished Aug 17 04:49:24 PM PDT 24
Peak memory 205368 kb
Host smart-bc3e8d2a-8a0c-4eac-8187-e84ff1d2d5d4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917099352 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr
_bit_bash.917099352
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.700089530
Short name T414
Test name
Test status
Simulation time 386355791 ps
CPU time 1.02 seconds
Started Aug 17 04:48:49 PM PDT 24
Finished Aug 17 04:48:50 PM PDT 24
Peak memory 205240 kb
Host smart-9ccc59ed-9485-4bff-aa62-1316eb57b926
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700089530 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr
_hw_reset.700089530
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.1843512090
Short name T432
Test name
Test status
Simulation time 207542292 ps
CPU time 0.93 seconds
Started Aug 17 04:48:46 PM PDT 24
Finished Aug 17 04:48:47 PM PDT 24
Peak memory 205160 kb
Host smart-9a198487-81dc-4903-963a-a2d95d9e8201
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843512090 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.1
843512090
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.1160914911
Short name T344
Test name
Test status
Simulation time 49642790 ps
CPU time 0.67 seconds
Started Aug 17 04:49:00 PM PDT 24
Finished Aug 17 04:49:00 PM PDT 24
Peak memory 205076 kb
Host smart-f8432ff9-0647-484e-905e-727f41a2ebf8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160914911 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.1160914911
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.3090808238
Short name T331
Test name
Test status
Simulation time 28921181 ps
CPU time 0.75 seconds
Started Aug 17 04:48:57 PM PDT 24
Finished Aug 17 04:48:58 PM PDT 24
Peak memory 205216 kb
Host smart-3dbb6626-d75c-4db8-a522-4c7c28d965ea
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090808238 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.3090808238
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.2201633651
Short name T420
Test name
Test status
Simulation time 165758048 ps
CPU time 6.54 seconds
Started Aug 17 04:48:59 PM PDT 24
Finished Aug 17 04:49:05 PM PDT 24
Peak memory 205412 kb
Host smart-115c426e-3c40-4369-b9b3-b0b09fb64f4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201633651 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.2201633651
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.3492035688
Short name T447
Test name
Test status
Simulation time 875062641 ps
CPU time 8.59 seconds
Started Aug 17 04:49:11 PM PDT 24
Finished Aug 17 04:49:20 PM PDT 24
Peak memory 221712 kb
Host smart-79db46e4-0fa6-48cd-b1be-8370adda525a
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492035688 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.3492035688
Directory /workspace/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.3592941979
Short name T382
Test name
Test status
Simulation time 149065235 ps
CPU time 3.78 seconds
Started Aug 17 04:48:58 PM PDT 24
Finished Aug 17 04:49:02 PM PDT 24
Peak memory 213716 kb
Host smart-53917f00-1cb7-4f2e-a7d9-6f5b485133fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592941979 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.3592941979
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.164720823
Short name T465
Test name
Test status
Simulation time 6555674521 ps
CPU time 19.04 seconds
Started Aug 17 04:49:02 PM PDT 24
Finished Aug 17 04:49:21 PM PDT 24
Peak memory 221912 kb
Host smart-17f79895-b5d2-4083-a532-b33a262004d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164720823 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.164720823
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.223487953
Short name T423
Test name
Test status
Simulation time 395885061 ps
CPU time 2.92 seconds
Started Aug 17 04:49:05 PM PDT 24
Finished Aug 17 04:49:08 PM PDT 24
Peak memory 217972 kb
Host smart-ae01f8bd-2870-4cff-b248-d3c9ebfe25b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223487953 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.223487953
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.2992629744
Short name T128
Test name
Test status
Simulation time 197049234 ps
CPU time 1.59 seconds
Started Aug 17 04:49:03 PM PDT 24
Finished Aug 17 04:49:05 PM PDT 24
Peak memory 218612 kb
Host smart-bd8c924b-c31a-4105-8f26-46c361d9f716
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992629744 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.2992629744
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.830965199
Short name T458
Test name
Test status
Simulation time 8787387980 ps
CPU time 22.5 seconds
Started Aug 17 04:48:55 PM PDT 24
Finished Aug 17 04:49:18 PM PDT 24
Peak memory 205504 kb
Host smart-717beb2b-2d19-44a6-ad2c-ea8a209d1e13
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830965199 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.r
v_dm_jtag_dmi_csr_bit_bash.830965199
Directory /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.3053245932
Short name T437
Test name
Test status
Simulation time 9147403334 ps
CPU time 12.56 seconds
Started Aug 17 04:49:00 PM PDT 24
Finished Aug 17 04:49:13 PM PDT 24
Peak memory 205424 kb
Host smart-5cd798dd-fd67-421d-b2a6-4fb003e2f835
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053245932 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.3
053245932
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.361642090
Short name T412
Test name
Test status
Simulation time 272516006 ps
CPU time 1.41 seconds
Started Aug 17 04:48:50 PM PDT 24
Finished Aug 17 04:48:52 PM PDT 24
Peak memory 205208 kb
Host smart-f3902c98-f321-4a99-8da9-a36211af2275
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361642090 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.361642090
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.2945066437
Short name T153
Test name
Test status
Simulation time 3532845180 ps
CPU time 4.92 seconds
Started Aug 17 04:48:58 PM PDT 24
Finished Aug 17 04:49:03 PM PDT 24
Peak memory 205588 kb
Host smart-710197a0-b041-47af-a549-7b3d18ce9937
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945066437 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.2945066437
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.1886688822
Short name T365
Test name
Test status
Simulation time 11170105514 ps
CPU time 40.22 seconds
Started Aug 17 04:48:55 PM PDT 24
Finished Aug 17 04:49:36 PM PDT 24
Peak memory 221632 kb
Host smart-b85653dd-c9a3-4d39-80ea-a0e0b0793ca1
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886688822 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.1886688822
Directory /workspace/5.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.2035278184
Short name T426
Test name
Test status
Simulation time 117854759 ps
CPU time 3.06 seconds
Started Aug 17 04:48:59 PM PDT 24
Finished Aug 17 04:49:02 PM PDT 24
Peak memory 213816 kb
Host smart-bd21c6b5-ec25-4116-9651-b2af788a896f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035278184 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.2035278184
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.722230866
Short name T197
Test name
Test status
Simulation time 3433397817 ps
CPU time 16.2 seconds
Started Aug 17 04:48:55 PM PDT 24
Finished Aug 17 04:49:11 PM PDT 24
Peak memory 221880 kb
Host smart-0af3fb52-553a-4604-83fc-a5b0fb52145f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722230866 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.722230866
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.958306292
Short name T457
Test name
Test status
Simulation time 207562464 ps
CPU time 4.02 seconds
Started Aug 17 04:48:58 PM PDT 24
Finished Aug 17 04:49:02 PM PDT 24
Peak memory 219156 kb
Host smart-bc4f2184-e318-49aa-a60a-97269ad1d6f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958306292 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.958306292
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.3996902947
Short name T125
Test name
Test status
Simulation time 119048713 ps
CPU time 2.42 seconds
Started Aug 17 04:49:03 PM PDT 24
Finished Aug 17 04:49:05 PM PDT 24
Peak memory 219224 kb
Host smart-73b59e8d-b80b-4ed2-82e7-68bca4ead748
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996902947 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.3996902947
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.315939996
Short name T384
Test name
Test status
Simulation time 8316385182 ps
CPU time 7.48 seconds
Started Aug 17 04:49:00 PM PDT 24
Finished Aug 17 04:49:07 PM PDT 24
Peak memory 205360 kb
Host smart-a834334e-47a8-4e9c-90aa-96a1884c6bdd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315939996 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.r
v_dm_jtag_dmi_csr_bit_bash.315939996
Directory /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.3323188757
Short name T415
Test name
Test status
Simulation time 1517841489 ps
CPU time 3.52 seconds
Started Aug 17 04:49:00 PM PDT 24
Finished Aug 17 04:49:03 PM PDT 24
Peak memory 205664 kb
Host smart-d9568f29-36e1-41f1-8518-96e5a7f0465d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323188757 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.3
323188757
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.795460129
Short name T360
Test name
Test status
Simulation time 211395457 ps
CPU time 1.02 seconds
Started Aug 17 04:49:05 PM PDT 24
Finished Aug 17 04:49:06 PM PDT 24
Peak memory 205140 kb
Host smart-49fbb19e-d526-4a72-bf48-330702664d0b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795460129 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.795460129
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.3320771273
Short name T121
Test name
Test status
Simulation time 1686160039 ps
CPU time 7.59 seconds
Started Aug 17 04:48:53 PM PDT 24
Finished Aug 17 04:49:00 PM PDT 24
Peak memory 205496 kb
Host smart-c761a78d-917c-44bf-9c9c-508f71adc1c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320771273 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.3320771273
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.1883643924
Short name T479
Test name
Test status
Simulation time 17237347600 ps
CPU time 33.37 seconds
Started Aug 17 04:49:07 PM PDT 24
Finished Aug 17 04:49:40 PM PDT 24
Peak memory 218092 kb
Host smart-98b604aa-96aa-4770-8e08-80e5ef83f683
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883643924 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.1883643924
Directory /workspace/6.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.2751689859
Short name T343
Test name
Test status
Simulation time 223057031 ps
CPU time 2.59 seconds
Started Aug 17 04:49:01 PM PDT 24
Finished Aug 17 04:49:04 PM PDT 24
Peak memory 213612 kb
Host smart-edf331e9-79a2-4ec1-b6a3-68d6d528c198
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751689859 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.2751689859
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.1107571993
Short name T460
Test name
Test status
Simulation time 2406933000 ps
CPU time 10.43 seconds
Started Aug 17 04:49:01 PM PDT 24
Finished Aug 17 04:49:12 PM PDT 24
Peak memory 221848 kb
Host smart-f5a56649-45fb-4803-b168-f47723429b93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107571993 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.1107571993
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.943488771
Short name T371
Test name
Test status
Simulation time 209017883 ps
CPU time 2.7 seconds
Started Aug 17 04:49:01 PM PDT 24
Finished Aug 17 04:49:04 PM PDT 24
Peak memory 217444 kb
Host smart-d5d6f1a4-d775-4e29-a46b-cb05ab1d69c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943488771 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.943488771
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.4258771527
Short name T151
Test name
Test status
Simulation time 71395815 ps
CPU time 2.28 seconds
Started Aug 17 04:49:01 PM PDT 24
Finished Aug 17 04:49:04 PM PDT 24
Peak memory 219328 kb
Host smart-8a8f3d3a-c2e0-44e0-9916-9e0a078e7495
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258771527 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.4258771527
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.2493900194
Short name T353
Test name
Test status
Simulation time 1918135896 ps
CPU time 1.4 seconds
Started Aug 17 04:49:07 PM PDT 24
Finished Aug 17 04:49:09 PM PDT 24
Peak memory 205340 kb
Host smart-2794b87b-4963-48fc-be64-fa9136bde4f1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493900194 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
rv_dm_jtag_dmi_csr_bit_bash.2493900194
Directory /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.452001050
Short name T334
Test name
Test status
Simulation time 4811380341 ps
CPU time 15 seconds
Started Aug 17 04:49:02 PM PDT 24
Finished Aug 17 04:49:17 PM PDT 24
Peak memory 205416 kb
Host smart-5130206a-607d-4b31-8273-c22b229b7498
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452001050 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.452001050
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.3145712643
Short name T328
Test name
Test status
Simulation time 169204222 ps
CPU time 1.19 seconds
Started Aug 17 04:49:02 PM PDT 24
Finished Aug 17 04:49:03 PM PDT 24
Peak memory 205176 kb
Host smart-73213b1e-3f5f-4f32-86f7-056f82f42bc2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145712643 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.3
145712643
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.3030428062
Short name T154
Test name
Test status
Simulation time 501896142 ps
CPU time 7.38 seconds
Started Aug 17 04:48:57 PM PDT 24
Finished Aug 17 04:49:05 PM PDT 24
Peak memory 205352 kb
Host smart-abbf3ba1-4385-4a6b-a470-71478defc5bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030428062 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.3030428062
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.2860121711
Short name T98
Test name
Test status
Simulation time 4512859304 ps
CPU time 88.52 seconds
Started Aug 17 04:48:59 PM PDT 24
Finished Aug 17 04:50:27 PM PDT 24
Peak memory 218712 kb
Host smart-25e104f4-6c2c-4fa8-93af-8c18ee898fbc
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860121711 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.2860121711
Directory /workspace/7.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.115148344
Short name T481
Test name
Test status
Simulation time 164943306 ps
CPU time 3.76 seconds
Started Aug 17 04:49:03 PM PDT 24
Finished Aug 17 04:49:07 PM PDT 24
Peak memory 213584 kb
Host smart-e3984b10-d011-4d1a-b37d-e9b8c7d143de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115148344 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.115148344
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2475624296
Short name T194
Test name
Test status
Simulation time 1467124831 ps
CPU time 12.94 seconds
Started Aug 17 04:48:58 PM PDT 24
Finished Aug 17 04:49:12 PM PDT 24
Peak memory 221808 kb
Host smart-79abc1bf-d212-4c94-93c9-0c2d7b059304
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475624296 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.2475624296
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.824646237
Short name T400
Test name
Test status
Simulation time 492623363 ps
CPU time 3.96 seconds
Started Aug 17 04:49:00 PM PDT 24
Finished Aug 17 04:49:04 PM PDT 24
Peak memory 219688 kb
Host smart-2074d4f3-0443-4da0-ab38-697966834955
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824646237 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.824646237
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.1555777339
Short name T146
Test name
Test status
Simulation time 218564904 ps
CPU time 1.63 seconds
Started Aug 17 04:49:02 PM PDT 24
Finished Aug 17 04:49:04 PM PDT 24
Peak memory 213784 kb
Host smart-09c8f966-0d24-48d4-99c4-6186434a6f89
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555777339 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.1555777339
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.3587226359
Short name T330
Test name
Test status
Simulation time 4205659634 ps
CPU time 12.22 seconds
Started Aug 17 04:49:03 PM PDT 24
Finished Aug 17 04:49:16 PM PDT 24
Peak memory 205348 kb
Host smart-c9e1336f-9719-4e30-ba5c-8ebd50a042fe
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587226359 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
rv_dm_jtag_dmi_csr_bit_bash.3587226359
Directory /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.3413804703
Short name T342
Test name
Test status
Simulation time 6235134411 ps
CPU time 9.67 seconds
Started Aug 17 04:48:58 PM PDT 24
Finished Aug 17 04:49:08 PM PDT 24
Peak memory 205384 kb
Host smart-3882364d-4849-4461-bb4f-ad87a391ee58
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413804703 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.3
413804703
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.3437193747
Short name T469
Test name
Test status
Simulation time 206413826 ps
CPU time 1.23 seconds
Started Aug 17 04:49:00 PM PDT 24
Finished Aug 17 04:49:02 PM PDT 24
Peak memory 205104 kb
Host smart-af318ecf-37b1-49bc-a34c-e7847ada6440
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437193747 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.3
437193747
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.297931010
Short name T140
Test name
Test status
Simulation time 630245894 ps
CPU time 4.08 seconds
Started Aug 17 04:48:56 PM PDT 24
Finished Aug 17 04:49:00 PM PDT 24
Peak memory 205420 kb
Host smart-ccd650d5-108a-4051-bfde-0e5eeb9ddb8e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297931010 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_c
sr_outstanding.297931010
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.2776928819
Short name T394
Test name
Test status
Simulation time 39029547096 ps
CPU time 57.37 seconds
Started Aug 17 04:49:05 PM PDT 24
Finished Aug 17 04:50:02 PM PDT 24
Peak memory 219444 kb
Host smart-dd6a413a-cb26-4d1a-a02b-b262f187c18b
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776928819 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.2776928819
Directory /workspace/8.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.1802357380
Short name T380
Test name
Test status
Simulation time 573363198 ps
CPU time 3.74 seconds
Started Aug 17 04:49:00 PM PDT 24
Finished Aug 17 04:49:04 PM PDT 24
Peak memory 213688 kb
Host smart-0ab2bb59-75e5-4b9b-8fed-17cc6fde0492
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802357380 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.1802357380
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.430612511
Short name T171
Test name
Test status
Simulation time 1566985842 ps
CPU time 18.93 seconds
Started Aug 17 04:48:58 PM PDT 24
Finished Aug 17 04:49:17 PM PDT 24
Peak memory 221816 kb
Host smart-09423108-5854-4021-9fd4-860b6d36a78f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430612511 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.430612511
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.4143448751
Short name T405
Test name
Test status
Simulation time 190213881 ps
CPU time 1.97 seconds
Started Aug 17 04:49:03 PM PDT 24
Finished Aug 17 04:49:05 PM PDT 24
Peak memory 215608 kb
Host smart-f2082c45-9f46-46c7-a561-1c7c33fc0c45
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143448751 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.4143448751
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1081976550
Short name T148
Test name
Test status
Simulation time 557807408 ps
CPU time 2.49 seconds
Started Aug 17 04:48:59 PM PDT 24
Finished Aug 17 04:49:02 PM PDT 24
Peak memory 213620 kb
Host smart-fe0cc6a5-e70d-4113-88a3-083da7d7fa46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081976550 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.1081976550
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.1484207755
Short name T402
Test name
Test status
Simulation time 4285960247 ps
CPU time 2.97 seconds
Started Aug 17 04:49:01 PM PDT 24
Finished Aug 17 04:49:04 PM PDT 24
Peak memory 205312 kb
Host smart-d2d523f3-5b72-4fad-bf2b-b21a7715cb5c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484207755 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
rv_dm_jtag_dmi_csr_bit_bash.1484207755
Directory /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.563971992
Short name T404
Test name
Test status
Simulation time 5158869122 ps
CPU time 14.8 seconds
Started Aug 17 04:49:06 PM PDT 24
Finished Aug 17 04:49:21 PM PDT 24
Peak memory 205488 kb
Host smart-61e86d1e-f894-494d-a6c4-ac8dd6b985a6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563971992 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.563971992
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.4144616622
Short name T451
Test name
Test status
Simulation time 1214578207 ps
CPU time 1.68 seconds
Started Aug 17 04:49:00 PM PDT 24
Finished Aug 17 04:49:02 PM PDT 24
Peak memory 205244 kb
Host smart-293f5d3d-303d-424c-8669-7da6103ba93d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144616622 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.4
144616622
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.1463428771
Short name T142
Test name
Test status
Simulation time 674523415 ps
CPU time 7.05 seconds
Started Aug 17 04:49:02 PM PDT 24
Finished Aug 17 04:49:10 PM PDT 24
Peak memory 205376 kb
Host smart-097e8db1-2ee2-44d4-862f-dc53b1afdc13
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463428771 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_
csr_outstanding.1463428771
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.1610971718
Short name T63
Test name
Test status
Simulation time 9803260807 ps
CPU time 75.56 seconds
Started Aug 17 04:49:03 PM PDT 24
Finished Aug 17 04:50:19 PM PDT 24
Peak memory 221520 kb
Host smart-b4d1c557-53cc-40eb-865d-b68c25a9e523
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610971718 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.1610971718
Directory /workspace/9.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.3368924721
Short name T406
Test name
Test status
Simulation time 430720836 ps
CPU time 5.11 seconds
Started Aug 17 04:49:06 PM PDT 24
Finished Aug 17 04:49:11 PM PDT 24
Peak memory 213612 kb
Host smart-0cb387b9-7c4f-4349-98d7-32482933dd3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368924721 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.3368924721
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.3318411578
Short name T198
Test name
Test status
Simulation time 4301421461 ps
CPU time 18.02 seconds
Started Aug 17 04:49:09 PM PDT 24
Finished Aug 17 04:49:27 PM PDT 24
Peak memory 221744 kb
Host smart-f6325e50-8b41-4bf1-83aa-b253c4a00750
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318411578 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.3318411578
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.2876970854
Short name T200
Test name
Test status
Simulation time 83029528 ps
CPU time 0.71 seconds
Started Aug 17 04:49:42 PM PDT 24
Finished Aug 17 04:49:42 PM PDT 24
Peak memory 204912 kb
Host smart-d9d156c2-ace3-4b73-bd84-1b769a963a7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876970854 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.2876970854
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.613816385
Short name T297
Test name
Test status
Simulation time 15884828090 ps
CPU time 23.82 seconds
Started Aug 17 04:49:15 PM PDT 24
Finished Aug 17 04:49:39 PM PDT 24
Peak memory 213684 kb
Host smart-087bbdc9-ebe0-49b5-8082-329a97f68182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613816385 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.613816385
Directory /workspace/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_buffered_enable.3865630203
Short name T225
Test name
Test status
Simulation time 661918677 ps
CPU time 1.82 seconds
Started Aug 17 04:49:24 PM PDT 24
Finished Aug 17 04:49:26 PM PDT 24
Peak memory 234128 kb
Host smart-1f6dcb82-79f9-4ce9-a887-b5b5687d2ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865630203 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_buffered_enable.3865630203
Directory /workspace/0.rv_dm_buffered_enable/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.2506203065
Short name T14
Test name
Test status
Simulation time 1387685691 ps
CPU time 1.91 seconds
Started Aug 17 04:49:18 PM PDT 24
Finished Aug 17 04:49:20 PM PDT 24
Peak memory 204928 kb
Host smart-18e0003e-f563-4d65-90c5-6f47426b97e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506203065 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.2506203065
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.1902800199
Short name T273
Test name
Test status
Simulation time 361974075 ps
CPU time 1.17 seconds
Started Aug 17 04:49:38 PM PDT 24
Finished Aug 17 04:49:39 PM PDT 24
Peak memory 204876 kb
Host smart-d3eb11d5-e088-4420-8518-96b7670214ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902800199 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.1902800199
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.3118947047
Short name T245
Test name
Test status
Simulation time 118967537 ps
CPU time 0.76 seconds
Started Aug 17 04:49:26 PM PDT 24
Finished Aug 17 04:49:27 PM PDT 24
Peak memory 204908 kb
Host smart-9d2ce9b5-6684-46e2-ba01-15a72f793296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118947047 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.3118947047
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_debug_disabled.2518959183
Short name T93
Test name
Test status
Simulation time 56153436 ps
CPU time 0.91 seconds
Started Aug 17 04:49:16 PM PDT 24
Finished Aug 17 04:49:17 PM PDT 24
Peak memory 214936 kb
Host smart-dc1a13bf-f995-4766-9a20-e600d83008cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518959183 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.2518959183
Directory /workspace/0.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.1881253056
Short name T202
Test name
Test status
Simulation time 3424293816 ps
CPU time 4.35 seconds
Started Aug 17 04:49:26 PM PDT 24
Finished Aug 17 04:49:31 PM PDT 24
Peak memory 213600 kb
Host smart-572ed836-87e4-449d-8bcb-ec823843cf5c
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1881253056 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t
l_access.1881253056
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.1408187007
Short name T184
Test name
Test status
Simulation time 458122856 ps
CPU time 1.88 seconds
Started Aug 17 04:49:16 PM PDT 24
Finished Aug 17 04:49:18 PM PDT 24
Peak memory 204924 kb
Host smart-3aaea3f6-45e2-455b-bfa4-4eee1a6f948a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408187007 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.1408187007
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.504707084
Short name T214
Test name
Test status
Simulation time 145488301 ps
CPU time 0.97 seconds
Started Aug 17 04:49:13 PM PDT 24
Finished Aug 17 04:49:14 PM PDT 24
Peak memory 204920 kb
Host smart-3d62cf34-e606-4fd7-b11e-77bfe7777ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504707084 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.504707084
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_hartsel_warl.4213429271
Short name T265
Test name
Test status
Simulation time 70377892 ps
CPU time 0.82 seconds
Started Aug 17 04:49:15 PM PDT 24
Finished Aug 17 04:49:16 PM PDT 24
Peak memory 204920 kb
Host smart-16227755-4d79-4e0c-bbaf-b765a1b7c952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213429271 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hartsel_warl_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hartsel_warl.4213429271
Directory /workspace/0.rv_dm_hartsel_warl/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.873654259
Short name T75
Test name
Test status
Simulation time 287080338 ps
CPU time 0.88 seconds
Started Aug 17 04:49:14 PM PDT 24
Finished Aug 17 04:49:15 PM PDT 24
Peak memory 204856 kb
Host smart-b49d6672-939b-4d11-b075-258da561c098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873654259 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.873654259
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.137228554
Short name T203
Test name
Test status
Simulation time 561504774 ps
CPU time 2.23 seconds
Started Aug 17 04:49:13 PM PDT 24
Finished Aug 17 04:49:15 PM PDT 24
Peak memory 204932 kb
Host smart-cd11f953-a526-4f2a-a0dc-d108d41b469a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137228554 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.137228554
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.2066160863
Short name T162
Test name
Test status
Simulation time 700498818 ps
CPU time 1.31 seconds
Started Aug 17 04:49:17 PM PDT 24
Finished Aug 17 04:49:18 PM PDT 24
Peak memory 204992 kb
Host smart-3a416aa7-5fe6-4097-9b84-d53c6304604e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066160863 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.2066160863
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.3778424080
Short name T304
Test name
Test status
Simulation time 134726063 ps
CPU time 0.79 seconds
Started Aug 17 04:49:12 PM PDT 24
Finished Aug 17 04:49:13 PM PDT 24
Peak memory 204892 kb
Host smart-957fce9f-a3d1-4dec-9574-988bad55878d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778424080 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.3778424080
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.637177770
Short name T113
Test name
Test status
Simulation time 270690468 ps
CPU time 0.94 seconds
Started Aug 17 04:49:26 PM PDT 24
Finished Aug 17 04:49:27 PM PDT 24
Peak memory 204996 kb
Host smart-48c24059-5af8-44df-bd6a-bce5dafef475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637177770 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.637177770
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.3596902480
Short name T237
Test name
Test status
Simulation time 178839786 ps
CPU time 1.21 seconds
Started Aug 17 04:49:14 PM PDT 24
Finished Aug 17 04:49:15 PM PDT 24
Peak memory 205260 kb
Host smart-f537b5f1-f802-4e1c-b1c7-ed33900743a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596902480 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.3596902480
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.3591004204
Short name T311
Test name
Test status
Simulation time 233162186 ps
CPU time 1.03 seconds
Started Aug 17 04:49:16 PM PDT 24
Finished Aug 17 04:49:17 PM PDT 24
Peak memory 213136 kb
Host smart-4330390b-1064-4c02-9f13-8a8e0d2a8a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591004204 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.3591004204
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.3529018209
Short name T48
Test name
Test status
Simulation time 838795951 ps
CPU time 1.42 seconds
Started Aug 17 04:49:26 PM PDT 24
Finished Aug 17 04:49:28 PM PDT 24
Peak memory 204992 kb
Host smart-293c7ddd-9ba3-48a7-a24c-e46438569c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529018209 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.3529018209
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.2372405304
Short name T130
Test name
Test status
Simulation time 15995652029 ps
CPU time 34.99 seconds
Started Aug 17 04:49:31 PM PDT 24
Finished Aug 17 04:50:07 PM PDT 24
Peak memory 205396 kb
Host smart-0547dd08-6d41-499a-9bfd-0cb46a521313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372405304 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.2372405304
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.3123027559
Short name T292
Test name
Test status
Simulation time 3567214566 ps
CPU time 5.76 seconds
Started Aug 17 04:49:12 PM PDT 24
Finished Aug 17 04:49:18 PM PDT 24
Peak memory 205268 kb
Host smart-a4e4ac18-5cb9-4406-a02a-c1b454ad30b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123027559 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.3123027559
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/0.rv_dm_stress_all.2457497190
Short name T321
Test name
Test status
Simulation time 3808042336 ps
CPU time 6.02 seconds
Started Aug 17 04:49:24 PM PDT 24
Finished Aug 17 04:49:30 PM PDT 24
Peak memory 205576 kb
Host smart-e8d73667-ab18-4cb8-a5bb-46d31781b6b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457497190 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.2457497190
Directory /workspace/0.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_stress_all_with_rand_reset.40430471
Short name T103
Test name
Test status
Simulation time 1497558532 ps
CPU time 15.53 seconds
Started Aug 17 04:49:35 PM PDT 24
Finished Aug 17 04:49:51 PM PDT 24
Peak memory 215372 kb
Host smart-ae0fb222-18ab-41e8-a0cd-6650c3815eb3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40430471 -assert nopostpr
oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all_with_rand_reset.40430471
Directory /workspace/0.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rv_dm_abstractcmd_status.3754917996
Short name T315
Test name
Test status
Simulation time 207895865 ps
CPU time 0.85 seconds
Started Aug 17 04:49:27 PM PDT 24
Finished Aug 17 04:49:27 PM PDT 24
Peak memory 205008 kb
Host smart-ef6680c7-bee6-414c-9794-0e2da5e2888e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754917996 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.3754917996
Directory /workspace/1.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.1786333451
Short name T291
Test name
Test status
Simulation time 105497925 ps
CPU time 0.91 seconds
Started Aug 17 04:49:46 PM PDT 24
Finished Aug 17 04:49:47 PM PDT 24
Peak memory 204988 kb
Host smart-b86b1188-b8fe-48d7-987b-7196018e3751
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786333451 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.1786333451
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.3420130101
Short name T76
Test name
Test status
Simulation time 7756095745 ps
CPU time 11.11 seconds
Started Aug 17 04:49:21 PM PDT 24
Finished Aug 17 04:49:32 PM PDT 24
Peak memory 213500 kb
Host smart-9551457a-2c5a-46c2-8c9e-307d9d77abf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420130101 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.3420130101
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_buffered_enable.291033151
Short name T49
Test name
Test status
Simulation time 441249766 ps
CPU time 1.95 seconds
Started Aug 17 04:49:36 PM PDT 24
Finished Aug 17 04:49:38 PM PDT 24
Peak memory 234056 kb
Host smart-b773a48a-ef48-4b62-bc89-d3ecc2f183f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291033151 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_buffered_enable.291033151
Directory /workspace/1.rv_dm_buffered_enable/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.3935107809
Short name T90
Test name
Test status
Simulation time 730756233 ps
CPU time 1.68 seconds
Started Aug 17 04:49:36 PM PDT 24
Finished Aug 17 04:49:38 PM PDT 24
Peak memory 204892 kb
Host smart-704eed52-0f9f-4ced-b508-bde993574975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935107809 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.3935107809
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.3507391570
Short name T15
Test name
Test status
Simulation time 212623286 ps
CPU time 0.84 seconds
Started Aug 17 04:49:22 PM PDT 24
Finished Aug 17 04:49:22 PM PDT 24
Peak memory 204908 kb
Host smart-48104881-faed-4775-b381-e8582b997d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507391570 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.3507391570
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.2657125144
Short name T35
Test name
Test status
Simulation time 573539103 ps
CPU time 1.43 seconds
Started Aug 17 04:49:38 PM PDT 24
Finished Aug 17 04:49:40 PM PDT 24
Peak memory 204892 kb
Host smart-f771dc3b-97c9-4d55-b9d4-09a9d02c9d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657125144 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.2657125144
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.2693596554
Short name T260
Test name
Test status
Simulation time 319000035 ps
CPU time 1.12 seconds
Started Aug 17 04:49:39 PM PDT 24
Finished Aug 17 04:49:41 PM PDT 24
Peak memory 204996 kb
Host smart-6f191c53-d04b-4a11-9cac-fe966d57f20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693596554 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.2693596554
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.2360803962
Short name T175
Test name
Test status
Simulation time 250889347 ps
CPU time 1.13 seconds
Started Aug 17 04:49:21 PM PDT 24
Finished Aug 17 04:49:22 PM PDT 24
Peak memory 204892 kb
Host smart-0c97da52-33d8-483c-ba9b-de88067b571a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360803962 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.2360803962
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_debug_disabled.646787382
Short name T83
Test name
Test status
Simulation time 71633296 ps
CPU time 0.86 seconds
Started Aug 17 04:49:35 PM PDT 24
Finished Aug 17 04:49:36 PM PDT 24
Peak memory 214896 kb
Host smart-838fd732-7508-4aaa-9c84-96f437e2ac73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646787382 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.646787382
Directory /workspace/1.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.1755601119
Short name T168
Test name
Test status
Simulation time 1265660439 ps
CPU time 1.86 seconds
Started Aug 17 04:49:32 PM PDT 24
Finished Aug 17 04:49:34 PM PDT 24
Peak memory 205268 kb
Host smart-b71e29eb-69d9-4f21-9efb-abf4442d2a36
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1755601119 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t
l_access.1755601119
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_dmi_failed_op.3198668388
Short name T61
Test name
Test status
Simulation time 132564820 ps
CPU time 0.81 seconds
Started Aug 17 04:49:27 PM PDT 24
Finished Aug 17 04:49:28 PM PDT 24
Peak memory 204968 kb
Host smart-78f8a892-d20b-4cb5-8208-955438d194d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198668388 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dmi_failed_op.3198668388
Directory /workspace/1.rv_dm_dmi_failed_op/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.993609608
Short name T44
Test name
Test status
Simulation time 1034984045 ps
CPU time 1.53 seconds
Started Aug 17 04:49:44 PM PDT 24
Finished Aug 17 04:49:46 PM PDT 24
Peak memory 204928 kb
Host smart-fe0d9e0e-055f-4506-a443-4cff6a43af04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993609608 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.993609608
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.4291056332
Short name T134
Test name
Test status
Simulation time 423406993 ps
CPU time 0.8 seconds
Started Aug 17 04:49:36 PM PDT 24
Finished Aug 17 04:49:37 PM PDT 24
Peak memory 204824 kb
Host smart-486ff59e-608e-4e30-8087-8d77fefb931a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291056332 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.4291056332
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.1845252590
Short name T65
Test name
Test status
Simulation time 692040194 ps
CPU time 1.03 seconds
Started Aug 17 04:49:28 PM PDT 24
Finished Aug 17 04:49:30 PM PDT 24
Peak memory 204876 kb
Host smart-eb559f0c-5a65-439e-9302-a90c7cd38054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845252590 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.1845252590
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.3612260098
Short name T295
Test name
Test status
Simulation time 2506680165 ps
CPU time 4.4 seconds
Started Aug 17 04:49:40 PM PDT 24
Finished Aug 17 04:49:44 PM PDT 24
Peak memory 204908 kb
Host smart-a8d8eeb4-89b6-4f43-b6c4-dad673df12b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612260098 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.3612260098
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.4216130426
Short name T78
Test name
Test status
Simulation time 386839724 ps
CPU time 0.94 seconds
Started Aug 17 04:49:23 PM PDT 24
Finished Aug 17 04:49:24 PM PDT 24
Peak memory 204924 kb
Host smart-acc88245-08aa-4ea2-8793-67de9e3c5098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216130426 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.4216130426
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.2522768381
Short name T89
Test name
Test status
Simulation time 859381913 ps
CPU time 1.19 seconds
Started Aug 17 04:49:26 PM PDT 24
Finished Aug 17 04:49:28 PM PDT 24
Peak memory 204992 kb
Host smart-ad0fd757-ba37-4af9-906b-d6b95613365a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522768381 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.2522768381
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.3904845969
Short name T219
Test name
Test status
Simulation time 581589970 ps
CPU time 1.09 seconds
Started Aug 17 04:49:35 PM PDT 24
Finished Aug 17 04:49:37 PM PDT 24
Peak memory 205260 kb
Host smart-0f6715e2-5d5c-4c04-a036-54a7a45e8b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904845969 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.3904845969
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.2909065228
Short name T119
Test name
Test status
Simulation time 751345432 ps
CPU time 2.68 seconds
Started Aug 17 04:49:36 PM PDT 24
Finished Aug 17 04:49:39 PM PDT 24
Peak memory 204992 kb
Host smart-e94e9cd9-26db-4347-85a3-0f45993b43c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909065228 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.2909065228
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.2006435075
Short name T215
Test name
Test status
Simulation time 293040879 ps
CPU time 1.49 seconds
Started Aug 17 04:49:23 PM PDT 24
Finished Aug 17 04:49:25 PM PDT 24
Peak memory 213196 kb
Host smart-6b1c32a0-6696-4784-89d6-3357d7b69e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006435075 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.2006435075
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.262747732
Short name T263
Test name
Test status
Simulation time 602665207 ps
CPU time 1.55 seconds
Started Aug 17 04:49:40 PM PDT 24
Finished Aug 17 04:49:42 PM PDT 24
Peak memory 204988 kb
Host smart-0ec50570-12b3-4f79-95b6-5541c8367432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262747732 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.262747732
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.639307787
Short name T39
Test name
Test status
Simulation time 154483776 ps
CPU time 0.91 seconds
Started Aug 17 04:49:21 PM PDT 24
Finished Aug 17 04:49:22 PM PDT 24
Peak memory 213264 kb
Host smart-63a41105-fcb8-4a69-8486-86497a49b31a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639307787 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.639307787
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_sba_debug_disabled.2281834626
Short name T92
Test name
Test status
Simulation time 2536754565 ps
CPU time 6.12 seconds
Started Aug 17 04:49:37 PM PDT 24
Finished Aug 17 04:49:43 PM PDT 24
Peak memory 205188 kb
Host smart-57f2c43b-e280-4079-b51c-3c81a021bbd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281834626 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.2281834626
Directory /workspace/1.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.1267539992
Short name T1
Test name
Test status
Simulation time 4942426767 ps
CPU time 2.53 seconds
Started Aug 17 04:49:32 PM PDT 24
Finished Aug 17 04:49:35 PM PDT 24
Peak memory 205424 kb
Host smart-a35a6274-9390-4baa-9018-3130fa0edacd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267539992 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.1267539992
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.612893507
Short name T66
Test name
Test status
Simulation time 523363296 ps
CPU time 2.36 seconds
Started Aug 17 04:49:37 PM PDT 24
Finished Aug 17 04:49:45 PM PDT 24
Peak memory 228536 kb
Host smart-96ff9745-fc07-47ac-9cce-437c21cdc6ae
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612893507 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.612893507
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.2206226617
Short name T68
Test name
Test status
Simulation time 465213712 ps
CPU time 1.96 seconds
Started Aug 17 04:49:23 PM PDT 24
Finished Aug 17 04:49:25 PM PDT 24
Peak memory 204908 kb
Host smart-620bd455-3bcc-449b-b309-7375bdf59406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206226617 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.2206226617
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/1.rv_dm_sparse_lc_gate_fsm.3627389912
Short name T58
Test name
Test status
Simulation time 228919327 ps
CPU time 1.04 seconds
Started Aug 17 04:49:23 PM PDT 24
Finished Aug 17 04:49:29 PM PDT 24
Peak memory 213272 kb
Host smart-6f329102-fdc7-42fa-8e88-4417fcf1f95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627389912 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sparse_lc_gate_fsm.3627389912
Directory /workspace/1.rv_dm_sparse_lc_gate_fsm/latest

Test location /workspace/coverage/default/1.rv_dm_stress_all.1507953660
Short name T6
Test name
Test status
Simulation time 3114959377 ps
CPU time 3.37 seconds
Started Aug 17 04:49:33 PM PDT 24
Finished Aug 17 04:49:37 PM PDT 24
Peak memory 205292 kb
Host smart-bc81d66e-471d-4561-91d7-bb8468bed9f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507953660 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.1507953660
Directory /workspace/1.rv_dm_stress_all/latest

Test location /workspace/coverage/default/1.rv_dm_stress_all_with_rand_reset.249567403
Short name T102
Test name
Test status
Simulation time 1767558772 ps
CPU time 44.07 seconds
Started Aug 17 04:49:38 PM PDT 24
Finished Aug 17 04:50:22 PM PDT 24
Peak memory 221636 kb
Host smart-0cc1d556-a6e2-4b09-9e31-77f6328577a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249567403 -assert nopostp
roc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all_with_rand_reset.249567403
Directory /workspace/1.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.3333255415
Short name T157
Test name
Test status
Simulation time 64948471 ps
CPU time 0.76 seconds
Started Aug 17 04:49:54 PM PDT 24
Finished Aug 17 04:49:55 PM PDT 24
Peak memory 204996 kb
Host smart-c317a860-04ad-4eef-aea0-396a31c47357
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333255415 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.3333255415
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.1176908088
Short name T303
Test name
Test status
Simulation time 125302572350 ps
CPU time 315.38 seconds
Started Aug 17 04:49:58 PM PDT 24
Finished Aug 17 04:55:13 PM PDT 24
Peak memory 213704 kb
Host smart-8988c96b-52d7-4831-8e2a-a01be2072c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176908088 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.1176908088
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.3404827255
Short name T285
Test name
Test status
Simulation time 2032740928 ps
CPU time 6.87 seconds
Started Aug 17 04:49:52 PM PDT 24
Finished Aug 17 04:49:59 PM PDT 24
Peak memory 205468 kb
Host smart-d2769654-eda2-496a-8409-9535fc7a6cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404827255 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.3404827255
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.224189067
Short name T286
Test name
Test status
Simulation time 2855899361 ps
CPU time 8.59 seconds
Started Aug 17 04:49:47 PM PDT 24
Finished Aug 17 04:49:55 PM PDT 24
Peak memory 205432 kb
Host smart-fbf84a70-6f33-4b2e-a17c-da37774dee87
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=224189067 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_t
l_access.224189067
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.150939349
Short name T231
Test name
Test status
Simulation time 760710244 ps
CPU time 2.98 seconds
Started Aug 17 04:49:54 PM PDT 24
Finished Aug 17 04:49:57 PM PDT 24
Peak memory 205252 kb
Host smart-be27105f-12c6-4e09-be1a-55a3721d1f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150939349 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.150939349
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_stress_all.2436763225
Short name T26
Test name
Test status
Simulation time 4154692005 ps
CPU time 6.88 seconds
Started Aug 17 04:49:52 PM PDT 24
Finished Aug 17 04:49:59 PM PDT 24
Peak memory 213504 kb
Host smart-65bb4a2d-9555-475c-ba62-c61e3c01eb26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436763225 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.2436763225
Directory /workspace/10.rv_dm_stress_all/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.97275252
Short name T249
Test name
Test status
Simulation time 48376187 ps
CPU time 0.73 seconds
Started Aug 17 04:49:53 PM PDT 24
Finished Aug 17 04:49:54 PM PDT 24
Peak memory 205268 kb
Host smart-d623d35b-5266-4091-9d5c-9ec873c2418c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97275252 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.97275252
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.1794555063
Short name T252
Test name
Test status
Simulation time 11433510436 ps
CPU time 10.95 seconds
Started Aug 17 04:49:51 PM PDT 24
Finished Aug 17 04:50:02 PM PDT 24
Peak memory 213660 kb
Host smart-4d28c657-bae0-41eb-b4dd-69bea2bcda62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794555063 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.1794555063
Directory /workspace/11.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.2583928735
Short name T208
Test name
Test status
Simulation time 11593887631 ps
CPU time 27.46 seconds
Started Aug 17 04:49:44 PM PDT 24
Finished Aug 17 04:50:12 PM PDT 24
Peak memory 213644 kb
Host smart-97065b2c-78d3-47e1-a13c-9ca2425b29c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583928735 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.2583928735
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.3493192337
Short name T177
Test name
Test status
Simulation time 7135471311 ps
CPU time 6.44 seconds
Started Aug 17 04:49:54 PM PDT 24
Finished Aug 17 04:50:01 PM PDT 24
Peak memory 212644 kb
Host smart-5fa23a61-a3b2-4e41-9185-50c0ae53b96f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3493192337 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_
tl_access.3493192337
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.4061097983
Short name T289
Test name
Test status
Simulation time 5867919533 ps
CPU time 5.58 seconds
Started Aug 17 04:50:00 PM PDT 24
Finished Aug 17 04:50:06 PM PDT 24
Peak memory 213544 kb
Host smart-e55e87af-0b38-4834-ad3f-8755b52654ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061097983 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.4061097983
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_stress_all.3754842067
Short name T279
Test name
Test status
Simulation time 1563696643 ps
CPU time 4.9 seconds
Started Aug 17 04:49:51 PM PDT 24
Finished Aug 17 04:49:57 PM PDT 24
Peak memory 205260 kb
Host smart-8ceb0231-0a52-4409-85ef-764130d038b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754842067 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.3754842067
Directory /workspace/11.rv_dm_stress_all/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.2205099983
Short name T251
Test name
Test status
Simulation time 60526178 ps
CPU time 0.83 seconds
Started Aug 17 04:49:44 PM PDT 24
Finished Aug 17 04:49:45 PM PDT 24
Peak memory 204908 kb
Host smart-f0a09714-58ef-4a1e-8260-c49f79e57c7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205099983 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.2205099983
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.718228370
Short name T216
Test name
Test status
Simulation time 15758712904 ps
CPU time 44.85 seconds
Started Aug 17 04:49:54 PM PDT 24
Finished Aug 17 04:50:39 PM PDT 24
Peak memory 213552 kb
Host smart-04d07c8b-8129-4604-aeb9-37b795d2e756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718228370 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.718228370
Directory /workspace/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.3758294059
Short name T27
Test name
Test status
Simulation time 3658892835 ps
CPU time 2.42 seconds
Started Aug 17 04:49:50 PM PDT 24
Finished Aug 17 04:49:52 PM PDT 24
Peak memory 205440 kb
Host smart-19563fd8-d563-4638-b7d3-eecd58906d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758294059 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.3758294059
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.3148422912
Short name T115
Test name
Test status
Simulation time 8899342513 ps
CPU time 14.38 seconds
Started Aug 17 04:49:57 PM PDT 24
Finished Aug 17 04:50:12 PM PDT 24
Peak memory 213700 kb
Host smart-68ec3ead-7342-4297-b86b-d0bf2acfda8f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3148422912 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_
tl_access.3148422912
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.63535155
Short name T211
Test name
Test status
Simulation time 2328452760 ps
CPU time 3.69 seconds
Started Aug 17 04:49:53 PM PDT 24
Finished Aug 17 04:49:56 PM PDT 24
Peak memory 205320 kb
Host smart-f60acb71-f6b5-4cf4-86ee-e3daeb155191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63535155 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.63535155
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_stress_all.204484323
Short name T88
Test name
Test status
Simulation time 1365786971 ps
CPU time 4.49 seconds
Started Aug 17 04:49:51 PM PDT 24
Finished Aug 17 04:49:56 PM PDT 24
Peak memory 205160 kb
Host smart-913fc38f-3702-474d-a93e-85cf9784cc6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204484323 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.204484323
Directory /workspace/12.rv_dm_stress_all/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.1794441477
Short name T267
Test name
Test status
Simulation time 105789396 ps
CPU time 0.76 seconds
Started Aug 17 04:49:52 PM PDT 24
Finished Aug 17 04:49:53 PM PDT 24
Peak memory 205276 kb
Host smart-05771b16-ea03-4632-8f93-7fc895cce283
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794441477 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.1794441477
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.3548016065
Short name T268
Test name
Test status
Simulation time 62637399379 ps
CPU time 83.61 seconds
Started Aug 17 04:49:47 PM PDT 24
Finished Aug 17 04:51:10 PM PDT 24
Peak memory 213576 kb
Host smart-cec1e30f-4c38-4f04-9757-32a93c283004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548016065 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.3548016065
Directory /workspace/13.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.461762219
Short name T112
Test name
Test status
Simulation time 1443157476 ps
CPU time 5.04 seconds
Started Aug 17 04:49:47 PM PDT 24
Finished Aug 17 04:49:53 PM PDT 24
Peak memory 205320 kb
Host smart-7e9720b3-82ed-471a-a26a-22713aa98233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461762219 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.461762219
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.3924760815
Short name T238
Test name
Test status
Simulation time 9656336375 ps
CPU time 3.19 seconds
Started Aug 17 04:49:44 PM PDT 24
Finished Aug 17 04:49:48 PM PDT 24
Peak memory 213532 kb
Host smart-3fdf5dd8-819e-44e2-aa01-84cb6b3cf7e2
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3924760815 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_
tl_access.3924760815
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.961564749
Short name T229
Test name
Test status
Simulation time 4982741239 ps
CPU time 3.55 seconds
Started Aug 17 04:49:56 PM PDT 24
Finished Aug 17 04:50:00 PM PDT 24
Peak memory 205352 kb
Host smart-dcc5fcfb-08ae-44d1-a745-e8b0052bc4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961564749 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.961564749
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_stress_all.3495220114
Short name T32
Test name
Test status
Simulation time 8028882829 ps
CPU time 12.17 seconds
Started Aug 17 04:49:49 PM PDT 24
Finished Aug 17 04:50:02 PM PDT 24
Peak memory 213524 kb
Host smart-a439618f-0d4c-46be-a94e-b12433229f18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495220114 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.3495220114
Directory /workspace/13.rv_dm_stress_all/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.334985644
Short name T158
Test name
Test status
Simulation time 29716545 ps
CPU time 0.77 seconds
Started Aug 17 04:49:56 PM PDT 24
Finished Aug 17 04:49:57 PM PDT 24
Peak memory 205020 kb
Host smart-29aea7d5-25ce-435e-b817-ee0b50de51e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334985644 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.334985644
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.1560435114
Short name T243
Test name
Test status
Simulation time 2343097080 ps
CPU time 3.2 seconds
Started Aug 17 04:49:52 PM PDT 24
Finished Aug 17 04:49:55 PM PDT 24
Peak memory 214612 kb
Host smart-8b25e67a-a2f7-45be-8911-bc083f33a23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560435114 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.1560435114
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.2323315834
Short name T233
Test name
Test status
Simulation time 2605134663 ps
CPU time 9.05 seconds
Started Aug 17 04:49:54 PM PDT 24
Finished Aug 17 04:50:04 PM PDT 24
Peak memory 213560 kb
Host smart-7e790016-e8b7-48bb-87f5-e21d847eb68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323315834 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.2323315834
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.553263349
Short name T166
Test name
Test status
Simulation time 2145686238 ps
CPU time 2.57 seconds
Started Aug 17 04:49:45 PM PDT 24
Finished Aug 17 04:49:48 PM PDT 24
Peak memory 205308 kb
Host smart-bd3407a7-d4bf-4389-b707-47a1190b1f67
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=553263349 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_t
l_access.553263349
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.1824190879
Short name T114
Test name
Test status
Simulation time 8033997632 ps
CPU time 13.37 seconds
Started Aug 17 04:49:45 PM PDT 24
Finished Aug 17 04:49:58 PM PDT 24
Peak memory 213472 kb
Host smart-dbdcfa40-10ff-4d21-95aa-56578fe149b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824190879 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.1824190879
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_stress_all.1267179010
Short name T293
Test name
Test status
Simulation time 2178808508 ps
CPU time 5.83 seconds
Started Aug 17 04:49:50 PM PDT 24
Finished Aug 17 04:49:56 PM PDT 24
Peak memory 205248 kb
Host smart-ca45fdec-614f-4011-8931-c1c5f8eeb00e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267179010 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.1267179010
Directory /workspace/14.rv_dm_stress_all/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.2190879338
Short name T230
Test name
Test status
Simulation time 137113808 ps
CPU time 0.95 seconds
Started Aug 17 04:49:48 PM PDT 24
Finished Aug 17 04:49:49 PM PDT 24
Peak memory 204984 kb
Host smart-54538185-0b4e-4fea-bbd1-669e62804885
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190879338 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.2190879338
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.1155348007
Short name T70
Test name
Test status
Simulation time 999414577 ps
CPU time 2.09 seconds
Started Aug 17 04:49:49 PM PDT 24
Finished Aug 17 04:49:51 PM PDT 24
Peak memory 205396 kb
Host smart-85f3cf8d-abf9-4c10-a0c6-e16c96ae1d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155348007 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.1155348007
Directory /workspace/15.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.485192859
Short name T235
Test name
Test status
Simulation time 1288183151 ps
CPU time 1.86 seconds
Started Aug 17 04:49:57 PM PDT 24
Finished Aug 17 04:49:59 PM PDT 24
Peak memory 205340 kb
Host smart-25975a84-a4be-41be-b26b-4ad27d6a0a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485192859 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.485192859
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.2146945137
Short name T80
Test name
Test status
Simulation time 2427462594 ps
CPU time 3.14 seconds
Started Aug 17 04:49:51 PM PDT 24
Finished Aug 17 04:49:54 PM PDT 24
Peak memory 205488 kb
Host smart-88c97b85-2a64-4709-9e33-77987ba2c01f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2146945137 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_
tl_access.2146945137
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.2667172088
Short name T12
Test name
Test status
Simulation time 6788196667 ps
CPU time 6.02 seconds
Started Aug 17 04:49:54 PM PDT 24
Finished Aug 17 04:50:00 PM PDT 24
Peak memory 213564 kb
Host smart-d977c481-3668-49aa-a8af-230e6b229625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667172088 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.2667172088
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_stress_all.1728168290
Short name T180
Test name
Test status
Simulation time 2152667971 ps
CPU time 2.24 seconds
Started Aug 17 04:49:51 PM PDT 24
Finished Aug 17 04:49:54 PM PDT 24
Peak memory 205168 kb
Host smart-34d95da9-b58a-4c3e-9b0e-955de15471ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728168290 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.1728168290
Directory /workspace/15.rv_dm_stress_all/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.2930307708
Short name T71
Test name
Test status
Simulation time 54463156 ps
CPU time 0.77 seconds
Started Aug 17 04:49:52 PM PDT 24
Finished Aug 17 04:49:53 PM PDT 24
Peak memory 204900 kb
Host smart-6d7dcd99-1d68-4c65-9930-31816afe5240
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930307708 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.2930307708
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.1403736821
Short name T79
Test name
Test status
Simulation time 1499664583 ps
CPU time 1.29 seconds
Started Aug 17 04:49:50 PM PDT 24
Finished Aug 17 04:49:52 PM PDT 24
Peak memory 213488 kb
Host smart-4a3ef52b-d5f8-4015-ab24-691706f4e103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403736821 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.1403736821
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.3713453005
Short name T239
Test name
Test status
Simulation time 4874162893 ps
CPU time 6.75 seconds
Started Aug 17 04:49:53 PM PDT 24
Finished Aug 17 04:50:00 PM PDT 24
Peak memory 205340 kb
Host smart-6baf4117-a7ce-476b-8f77-b24f36b495d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713453005 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.3713453005
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.3648749880
Short name T212
Test name
Test status
Simulation time 1793643491 ps
CPU time 3.6 seconds
Started Aug 17 04:49:58 PM PDT 24
Finished Aug 17 04:50:02 PM PDT 24
Peak memory 205292 kb
Host smart-ed397368-83e3-406f-9528-8df3e2a560e1
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3648749880 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_
tl_access.3648749880
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.841718137
Short name T274
Test name
Test status
Simulation time 1580045228 ps
CPU time 5.57 seconds
Started Aug 17 04:49:41 PM PDT 24
Finished Aug 17 04:49:47 PM PDT 24
Peak memory 205348 kb
Host smart-d3ad133a-49c0-4868-ab84-6c00ca37a78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841718137 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.841718137
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_stress_all.2447670817
Short name T4
Test name
Test status
Simulation time 8909345827 ps
CPU time 13.38 seconds
Started Aug 17 04:49:52 PM PDT 24
Finished Aug 17 04:50:06 PM PDT 24
Peak memory 205296 kb
Host smart-a9c4f786-d2c4-4c18-aa1f-7f5c57600618
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447670817 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.2447670817
Directory /workspace/16.rv_dm_stress_all/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.828550370
Short name T241
Test name
Test status
Simulation time 105727249 ps
CPU time 0.74 seconds
Started Aug 17 04:49:57 PM PDT 24
Finished Aug 17 04:49:58 PM PDT 24
Peak memory 204992 kb
Host smart-7f5f2f03-90ef-417c-8c0c-278b89c2f35e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828550370 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.828550370
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.3538048169
Short name T269
Test name
Test status
Simulation time 1231476853 ps
CPU time 2.38 seconds
Started Aug 17 04:50:00 PM PDT 24
Finished Aug 17 04:50:02 PM PDT 24
Peak memory 205248 kb
Host smart-b78acfb9-0f21-40b3-b2f0-3d5336ce387e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538048169 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.3538048169
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.2231108613
Short name T271
Test name
Test status
Simulation time 1827306268 ps
CPU time 2.39 seconds
Started Aug 17 04:50:03 PM PDT 24
Finished Aug 17 04:50:06 PM PDT 24
Peak memory 205424 kb
Host smart-a68e4796-55a9-497c-a5c3-7185dbc0ec2c
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2231108613 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_
tl_access.2231108613
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.1732000507
Short name T319
Test name
Test status
Simulation time 2664458998 ps
CPU time 2.08 seconds
Started Aug 17 04:49:55 PM PDT 24
Finished Aug 17 04:49:57 PM PDT 24
Peak memory 213492 kb
Host smart-f2a6e82c-cb72-47df-98c4-11c54f07ed81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732000507 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.1732000507
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_stress_all.1744377075
Short name T9
Test name
Test status
Simulation time 1066945005 ps
CPU time 2.29 seconds
Started Aug 17 04:49:56 PM PDT 24
Finished Aug 17 04:49:58 PM PDT 24
Peak memory 205108 kb
Host smart-ea1a28aa-e549-4b55-8165-ac99f77e7134
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744377075 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.1744377075
Directory /workspace/17.rv_dm_stress_all/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.307761660
Short name T169
Test name
Test status
Simulation time 40150407 ps
CPU time 0.75 seconds
Started Aug 17 04:49:53 PM PDT 24
Finished Aug 17 04:49:54 PM PDT 24
Peak memory 204904 kb
Host smart-581476fc-798d-48cc-b03b-6a01c7f9cb6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307761660 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.307761660
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.1644760717
Short name T179
Test name
Test status
Simulation time 16997153072 ps
CPU time 14.86 seconds
Started Aug 17 04:50:02 PM PDT 24
Finished Aug 17 04:50:17 PM PDT 24
Peak memory 221812 kb
Host smart-326efc05-5fce-437e-83aa-6af79f92bad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644760717 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.1644760717
Directory /workspace/18.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.378373403
Short name T284
Test name
Test status
Simulation time 4289984359 ps
CPU time 4.53 seconds
Started Aug 17 04:50:00 PM PDT 24
Finished Aug 17 04:50:04 PM PDT 24
Peak memory 213616 kb
Host smart-91e5a71f-db61-4dc0-9429-4cdfff5f2ef9
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=378373403 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_t
l_access.378373403
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.4067984822
Short name T81
Test name
Test status
Simulation time 1541980303 ps
CPU time 2.83 seconds
Started Aug 17 04:50:00 PM PDT 24
Finished Aug 17 04:50:03 PM PDT 24
Peak memory 205436 kb
Host smart-9ece17ab-6b63-4199-b634-ec4f2f9238d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067984822 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.4067984822
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.4099297313
Short name T325
Test name
Test status
Simulation time 85835975 ps
CPU time 0.73 seconds
Started Aug 17 04:49:52 PM PDT 24
Finished Aug 17 04:49:53 PM PDT 24
Peak memory 204844 kb
Host smart-1724c55b-0ced-43dd-a061-b29fcc272bd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099297313 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.4099297313
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.1409098721
Short name T31
Test name
Test status
Simulation time 19566121016 ps
CPU time 7.34 seconds
Started Aug 17 04:50:08 PM PDT 24
Finished Aug 17 04:50:16 PM PDT 24
Peak memory 213132 kb
Host smart-da99f79d-c397-4b06-8e9a-1ed65c6f46de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409098721 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.1409098721
Directory /workspace/19.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.1407227507
Short name T244
Test name
Test status
Simulation time 4650422357 ps
CPU time 2.65 seconds
Started Aug 17 04:50:08 PM PDT 24
Finished Aug 17 04:50:11 PM PDT 24
Peak memory 213056 kb
Host smart-73058281-77b7-4272-a2b8-b0846b748007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407227507 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.1407227507
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.4050800363
Short name T314
Test name
Test status
Simulation time 12719658296 ps
CPU time 35.17 seconds
Started Aug 17 04:49:55 PM PDT 24
Finished Aug 17 04:50:31 PM PDT 24
Peak memory 213512 kb
Host smart-7cabb64c-aac3-45b9-ac3a-2627fdb6422f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4050800363 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_
tl_access.4050800363
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.3410711355
Short name T258
Test name
Test status
Simulation time 3653086151 ps
CPU time 2.86 seconds
Started Aug 17 04:49:57 PM PDT 24
Finished Aug 17 04:50:00 PM PDT 24
Peak memory 205344 kb
Host smart-da16b8bc-dbff-40e9-b71e-2c4c4463966d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410711355 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.3410711355
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_stress_all.2228091134
Short name T317
Test name
Test status
Simulation time 1449296519 ps
CPU time 1.48 seconds
Started Aug 17 04:49:52 PM PDT 24
Finished Aug 17 04:49:54 PM PDT 24
Peak memory 205212 kb
Host smart-bb05b261-14e1-4c35-ae0a-c785ac379e67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228091134 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.2228091134
Directory /workspace/19.rv_dm_stress_all/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.2936223335
Short name T224
Test name
Test status
Simulation time 88381510 ps
CPU time 0.71 seconds
Started Aug 17 04:49:36 PM PDT 24
Finished Aug 17 04:49:37 PM PDT 24
Peak memory 204936 kb
Host smart-b16df0a4-4980-445a-a984-c5da5dae03f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936223335 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.2936223335
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.1268923859
Short name T255
Test name
Test status
Simulation time 3610645557 ps
CPU time 10.74 seconds
Started Aug 17 04:49:26 PM PDT 24
Finished Aug 17 04:49:37 PM PDT 24
Peak memory 214056 kb
Host smart-94b5fde1-34e0-45b4-b7de-90d28d6c8822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268923859 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.1268923859
Directory /workspace/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.2990844133
Short name T69
Test name
Test status
Simulation time 1859573844 ps
CPU time 2.3 seconds
Started Aug 17 04:49:35 PM PDT 24
Finished Aug 17 04:49:37 PM PDT 24
Peak memory 205316 kb
Host smart-78ff32ce-3fe2-467b-9a54-7ec9aa539438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990844133 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.2990844133
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_buffered_enable.3133496655
Short name T11
Test name
Test status
Simulation time 297138610 ps
CPU time 1.26 seconds
Started Aug 17 04:49:42 PM PDT 24
Finished Aug 17 04:49:44 PM PDT 24
Peak memory 234164 kb
Host smart-cb749a94-2970-499f-a3c2-c8311992af96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133496655 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_buffered_enable.3133496655
Directory /workspace/2.rv_dm_buffered_enable/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.884495081
Short name T218
Test name
Test status
Simulation time 2155144159 ps
CPU time 2.88 seconds
Started Aug 17 04:49:22 PM PDT 24
Finished Aug 17 04:49:25 PM PDT 24
Peak memory 205460 kb
Host smart-302bdb2a-e552-4dfd-a8db-237c09230e8a
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=884495081 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_tl
_access.884495081
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_halt_resume_whereto.507886934
Short name T41
Test name
Test status
Simulation time 1317044539 ps
CPU time 2.51 seconds
Started Aug 17 04:49:46 PM PDT 24
Finished Aug 17 04:49:49 PM PDT 24
Peak memory 204992 kb
Host smart-59059db7-e5d1-48b0-a6ae-9fea55f4a3f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507886934 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_halt_resume_whereto.507886934
Directory /workspace/2.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.1475803560
Short name T118
Test name
Test status
Simulation time 129101803 ps
CPU time 0.86 seconds
Started Aug 17 04:49:43 PM PDT 24
Finished Aug 17 04:49:44 PM PDT 24
Peak memory 204904 kb
Host smart-467e2f01-fec9-413d-b618-386c7c9d8819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475803560 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.1475803560
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.369517416
Short name T29
Test name
Test status
Simulation time 3281021813 ps
CPU time 9.91 seconds
Started Aug 17 04:49:21 PM PDT 24
Finished Aug 17 04:49:31 PM PDT 24
Peak memory 205412 kb
Host smart-4685d386-8599-426d-b8a4-11258f84c908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369517416 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.369517416
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.2568687874
Short name T53
Test name
Test status
Simulation time 986028236 ps
CPU time 3.55 seconds
Started Aug 17 04:49:35 PM PDT 24
Finished Aug 17 04:49:39 PM PDT 24
Peak memory 229276 kb
Host smart-c48f1d48-a8d3-4734-8376-f9025bbb2e6b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568687874 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.2568687874
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/2.rv_dm_stress_all.499374784
Short name T176
Test name
Test status
Simulation time 4850461595 ps
CPU time 6.63 seconds
Started Aug 17 04:49:40 PM PDT 24
Finished Aug 17 04:49:47 PM PDT 24
Peak memory 213456 kb
Host smart-579f605b-78ec-487b-b631-3a47a43f0425
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499374784 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.499374784
Directory /workspace/2.rv_dm_stress_all/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.3710927697
Short name T287
Test name
Test status
Simulation time 72160187 ps
CPU time 0.76 seconds
Started Aug 17 04:49:56 PM PDT 24
Finished Aug 17 04:49:57 PM PDT 24
Peak memory 204884 kb
Host smart-e01ef29a-bddc-48c7-800f-826d6c16612f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710927697 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.3710927697
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/20.rv_dm_stress_all.3693342625
Short name T313
Test name
Test status
Simulation time 5208503678 ps
CPU time 4.18 seconds
Started Aug 17 04:49:57 PM PDT 24
Finished Aug 17 04:50:01 PM PDT 24
Peak memory 205092 kb
Host smart-c64d18f4-f3e7-4405-8268-f384ca6e43d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693342625 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.3693342625
Directory /workspace/20.rv_dm_stress_all/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.2518290639
Short name T226
Test name
Test status
Simulation time 42696676 ps
CPU time 0.78 seconds
Started Aug 17 04:50:08 PM PDT 24
Finished Aug 17 04:50:08 PM PDT 24
Peak memory 204884 kb
Host smart-ee7b59ab-5145-466a-a546-1e5c01e6dffb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518290639 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.2518290639
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_stress_all.3393147942
Short name T187
Test name
Test status
Simulation time 4695424537 ps
CPU time 7.3 seconds
Started Aug 17 04:50:10 PM PDT 24
Finished Aug 17 04:50:18 PM PDT 24
Peak memory 205244 kb
Host smart-ee6807aa-5b06-427b-9f4d-502c215e9146
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393147942 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.3393147942
Directory /workspace/21.rv_dm_stress_all/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.4159316221
Short name T282
Test name
Test status
Simulation time 70802475 ps
CPU time 0.85 seconds
Started Aug 17 04:50:03 PM PDT 24
Finished Aug 17 04:50:04 PM PDT 24
Peak memory 204912 kb
Host smart-92cf8231-7867-4d6b-9211-2f35e1ff196d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159316221 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.4159316221
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_stress_all.3784758870
Short name T2
Test name
Test status
Simulation time 3721212279 ps
CPU time 3.85 seconds
Started Aug 17 04:49:56 PM PDT 24
Finished Aug 17 04:50:00 PM PDT 24
Peak memory 213528 kb
Host smart-1c138ea9-3dea-4480-8091-a48ad4e6f7bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784758870 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.3784758870
Directory /workspace/22.rv_dm_stress_all/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.1481854256
Short name T234
Test name
Test status
Simulation time 105864550 ps
CPU time 0.84 seconds
Started Aug 17 04:49:58 PM PDT 24
Finished Aug 17 04:49:58 PM PDT 24
Peak memory 205008 kb
Host smart-bae6b82a-6f9c-435d-abd3-27d49646b469
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481854256 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.1481854256
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.1391726250
Short name T310
Test name
Test status
Simulation time 98495220 ps
CPU time 0.85 seconds
Started Aug 17 04:50:01 PM PDT 24
Finished Aug 17 04:50:02 PM PDT 24
Peak memory 204996 kb
Host smart-4cc72450-5dfe-41c5-833f-16dad1fc97d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391726250 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.1391726250
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_stress_all.4259877083
Short name T46
Test name
Test status
Simulation time 5000664502 ps
CPU time 5.72 seconds
Started Aug 17 04:49:55 PM PDT 24
Finished Aug 17 04:50:01 PM PDT 24
Peak memory 213368 kb
Host smart-3f6687a7-521f-41c5-b46d-11c5bdb4a114
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259877083 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.4259877083
Directory /workspace/24.rv_dm_stress_all/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.952957340
Short name T290
Test name
Test status
Simulation time 53131896 ps
CPU time 0.76 seconds
Started Aug 17 04:50:01 PM PDT 24
Finished Aug 17 04:50:02 PM PDT 24
Peak memory 204836 kb
Host smart-55b3a8b2-3f5c-4617-ba0d-4d6f2b676492
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952957340 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.952957340
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_stress_all.2002726520
Short name T240
Test name
Test status
Simulation time 9298335541 ps
CPU time 3.57 seconds
Started Aug 17 04:49:55 PM PDT 24
Finished Aug 17 04:49:59 PM PDT 24
Peak memory 213444 kb
Host smart-2fd8884a-dbec-4a55-9485-ac24de70a1e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002726520 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.2002726520
Directory /workspace/25.rv_dm_stress_all/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.3666278312
Short name T236
Test name
Test status
Simulation time 145861680 ps
CPU time 0.88 seconds
Started Aug 17 04:50:00 PM PDT 24
Finished Aug 17 04:50:01 PM PDT 24
Peak memory 204856 kb
Host smart-f77b79df-0121-42a0-affb-970e1cbc09ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666278312 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.3666278312
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.1853881402
Short name T201
Test name
Test status
Simulation time 139173086 ps
CPU time 0.88 seconds
Started Aug 17 04:49:55 PM PDT 24
Finished Aug 17 04:49:56 PM PDT 24
Peak memory 204900 kb
Host smart-81dbcc65-d2be-4d83-9da8-ac3c38efe3a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853881402 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.1853881402
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.2085282610
Short name T246
Test name
Test status
Simulation time 92093208 ps
CPU time 0.81 seconds
Started Aug 17 04:49:59 PM PDT 24
Finished Aug 17 04:49:59 PM PDT 24
Peak memory 204940 kb
Host smart-b2494999-af71-4d43-ae85-c1218a363338
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085282610 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.2085282610
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_stress_all.689510947
Short name T21
Test name
Test status
Simulation time 10222988514 ps
CPU time 28.3 seconds
Started Aug 17 04:50:09 PM PDT 24
Finished Aug 17 04:50:38 PM PDT 24
Peak memory 205172 kb
Host smart-3e273647-f8f1-4285-bcae-060ffeb85406
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689510947 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.689510947
Directory /workspace/28.rv_dm_stress_all/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.2375938287
Short name T164
Test name
Test status
Simulation time 42796756 ps
CPU time 0.79 seconds
Started Aug 17 04:49:56 PM PDT 24
Finished Aug 17 04:49:57 PM PDT 24
Peak memory 204968 kb
Host smart-548b0b54-534c-4d3d-9288-2167c16ed5ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375938287 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.2375938287
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_stress_all.2153047201
Short name T301
Test name
Test status
Simulation time 12651839007 ps
CPU time 19.55 seconds
Started Aug 17 04:50:02 PM PDT 24
Finished Aug 17 04:50:22 PM PDT 24
Peak memory 205228 kb
Host smart-6e7e666b-0161-4360-8608-f58e2a8c958b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153047201 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.2153047201
Directory /workspace/29.rv_dm_stress_all/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.14179232
Short name T220
Test name
Test status
Simulation time 82364920 ps
CPU time 0.79 seconds
Started Aug 17 04:49:32 PM PDT 24
Finished Aug 17 04:49:33 PM PDT 24
Peak memory 204888 kb
Host smart-cd8aef0c-c7fd-4b8e-bbb9-5ee4d66dd4d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14179232 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.14179232
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.2815573918
Short name T248
Test name
Test status
Simulation time 4956465810 ps
CPU time 4.12 seconds
Started Aug 17 04:49:38 PM PDT 24
Finished Aug 17 04:49:42 PM PDT 24
Peak memory 205736 kb
Host smart-ecb68f18-3dbe-4b10-9e90-faf1bc520748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815573918 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.2815573918
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.2179315560
Short name T254
Test name
Test status
Simulation time 5280689705 ps
CPU time 4.01 seconds
Started Aug 17 04:49:36 PM PDT 24
Finished Aug 17 04:49:40 PM PDT 24
Peak memory 205360 kb
Host smart-01c5993d-984a-4cf2-ab86-fe67725ae7a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179315560 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.2179315560
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.4099362771
Short name T217
Test name
Test status
Simulation time 12475119072 ps
CPU time 9.37 seconds
Started Aug 17 04:49:41 PM PDT 24
Finished Aug 17 04:49:51 PM PDT 24
Peak memory 213604 kb
Host smart-6677f427-1fd4-4eca-a97a-5dfbcf8f40f6
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4099362771 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t
l_access.4099362771
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_halt_resume_whereto.3450208286
Short name T270
Test name
Test status
Simulation time 470152609 ps
CPU time 2.09 seconds
Started Aug 17 04:49:38 PM PDT 24
Finished Aug 17 04:49:40 PM PDT 24
Peak memory 204960 kb
Host smart-406f4fa2-0f93-4c9b-a0c2-cc0467032b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450208286 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_halt_resume_whereto.3450208286
Directory /workspace/3.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.1678474002
Short name T84
Test name
Test status
Simulation time 271012153 ps
CPU time 0.87 seconds
Started Aug 17 04:49:40 PM PDT 24
Finished Aug 17 04:49:40 PM PDT 24
Peak memory 204904 kb
Host smart-4b18021f-54e1-4e38-bd45-2b0f1e9bbf7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678474002 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.1678474002
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.1442285176
Short name T300
Test name
Test status
Simulation time 2602019333 ps
CPU time 4.78 seconds
Started Aug 17 04:49:40 PM PDT 24
Finished Aug 17 04:49:45 PM PDT 24
Peak memory 205392 kb
Host smart-4154cac6-3c52-414e-ada8-a324d6002e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442285176 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.1442285176
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.1072325281
Short name T64
Test name
Test status
Simulation time 454669660 ps
CPU time 1.58 seconds
Started Aug 17 04:49:41 PM PDT 24
Finished Aug 17 04:49:43 PM PDT 24
Peak memory 229032 kb
Host smart-d5b24819-aafa-4102-a6ca-0eb69522f0e8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072325281 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.1072325281
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/3.rv_dm_sparse_lc_gate_fsm.967249868
Short name T60
Test name
Test status
Simulation time 329019306 ps
CPU time 1.62 seconds
Started Aug 17 04:49:46 PM PDT 24
Finished Aug 17 04:49:48 PM PDT 24
Peak memory 213268 kb
Host smart-0aa04a1d-0240-4988-841e-5b77e24c406f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967249868 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sparse_lc_gate_fsm.967249868
Directory /workspace/3.rv_dm_sparse_lc_gate_fsm/latest

Test location /workspace/coverage/default/3.rv_dm_stress_all.3146725595
Short name T13
Test name
Test status
Simulation time 2169409256 ps
CPU time 2.89 seconds
Started Aug 17 04:49:44 PM PDT 24
Finished Aug 17 04:49:47 PM PDT 24
Peak memory 205260 kb
Host smart-d6b9f1f3-e12a-4878-bc6a-b380a4e85251
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146725595 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.3146725595
Directory /workspace/3.rv_dm_stress_all/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.1491132731
Short name T161
Test name
Test status
Simulation time 132099621 ps
CPU time 1.05 seconds
Started Aug 17 04:49:54 PM PDT 24
Finished Aug 17 04:49:56 PM PDT 24
Peak memory 204884 kb
Host smart-b5b4c9d1-ef98-4ce8-aa99-1b9d7b87784d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491132731 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.1491132731
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/30.rv_dm_stress_all.3487821201
Short name T183
Test name
Test status
Simulation time 4172899163 ps
CPU time 12.32 seconds
Started Aug 17 04:50:04 PM PDT 24
Finished Aug 17 04:50:16 PM PDT 24
Peak memory 205520 kb
Host smart-f14119d5-097b-4d76-bf3f-79923269d299
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487821201 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.3487821201
Directory /workspace/30.rv_dm_stress_all/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.1838216891
Short name T296
Test name
Test status
Simulation time 85675992 ps
CPU time 0.76 seconds
Started Aug 17 04:49:55 PM PDT 24
Finished Aug 17 04:49:56 PM PDT 24
Peak memory 205272 kb
Host smart-b3026be2-46db-46bd-98a3-571466963c2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838216891 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.1838216891
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_stress_all.3471321433
Short name T18
Test name
Test status
Simulation time 2754577015 ps
CPU time 7.86 seconds
Started Aug 17 04:49:56 PM PDT 24
Finished Aug 17 04:50:04 PM PDT 24
Peak memory 205220 kb
Host smart-c3704179-8799-4600-a491-b961f2a904f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471321433 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.3471321433
Directory /workspace/31.rv_dm_stress_all/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.1706599745
Short name T210
Test name
Test status
Simulation time 91324457 ps
CPU time 0.72 seconds
Started Aug 17 04:49:57 PM PDT 24
Finished Aug 17 04:49:57 PM PDT 24
Peak memory 204876 kb
Host smart-97e1aa3b-3fb3-439b-9669-f5ca5ded59ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706599745 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.1706599745
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_stress_all.1380934090
Short name T87
Test name
Test status
Simulation time 5839063524 ps
CPU time 8.99 seconds
Started Aug 17 04:49:59 PM PDT 24
Finished Aug 17 04:50:09 PM PDT 24
Peak memory 205256 kb
Host smart-a7344295-0101-4159-aa05-521e39b84419
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380934090 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.1380934090
Directory /workspace/32.rv_dm_stress_all/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.1504604304
Short name T259
Test name
Test status
Simulation time 45253828 ps
CPU time 0.77 seconds
Started Aug 17 04:49:59 PM PDT 24
Finished Aug 17 04:50:00 PM PDT 24
Peak memory 204996 kb
Host smart-7edf1239-9aa6-4171-af0b-eafca8ffa1c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504604304 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.1504604304
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_stress_all.2181675595
Short name T178
Test name
Test status
Simulation time 5800348364 ps
CPU time 11.88 seconds
Started Aug 17 04:50:06 PM PDT 24
Finished Aug 17 04:50:18 PM PDT 24
Peak memory 205260 kb
Host smart-fde5b4d6-fa84-49d3-b9a6-3f95d6995b4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181675595 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.2181675595
Directory /workspace/33.rv_dm_stress_all/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.1380616736
Short name T276
Test name
Test status
Simulation time 133569701 ps
CPU time 0.87 seconds
Started Aug 17 04:49:53 PM PDT 24
Finished Aug 17 04:49:54 PM PDT 24
Peak memory 204900 kb
Host smart-de583a20-f3ad-4c00-a06d-017eccf0ad7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380616736 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.1380616736
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_stress_all.2284084071
Short name T25
Test name
Test status
Simulation time 4883471798 ps
CPU time 3.59 seconds
Started Aug 17 04:49:55 PM PDT 24
Finished Aug 17 04:49:59 PM PDT 24
Peak memory 205280 kb
Host smart-33dcd887-3d71-4e95-b9ad-3f4432b4e647
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284084071 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.2284084071
Directory /workspace/34.rv_dm_stress_all/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.2656413609
Short name T72
Test name
Test status
Simulation time 70270371 ps
CPU time 0.71 seconds
Started Aug 17 04:50:08 PM PDT 24
Finished Aug 17 04:50:09 PM PDT 24
Peak memory 204836 kb
Host smart-9311b277-a761-4b70-be21-1450714efc7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656413609 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.2656413609
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_stress_all.837845899
Short name T298
Test name
Test status
Simulation time 944730175 ps
CPU time 1.41 seconds
Started Aug 17 04:50:00 PM PDT 24
Finished Aug 17 04:50:02 PM PDT 24
Peak memory 205192 kb
Host smart-5f4a4558-dc1b-4f93-ad4b-a70229bab09f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837845899 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.837845899
Directory /workspace/35.rv_dm_stress_all/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.1295812942
Short name T34
Test name
Test status
Simulation time 36954176 ps
CPU time 0.72 seconds
Started Aug 17 04:49:59 PM PDT 24
Finished Aug 17 04:50:00 PM PDT 24
Peak memory 205012 kb
Host smart-d2166d3d-97c9-441a-b130-efdc93b01a12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295812942 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.1295812942
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_stress_all.3544113886
Short name T10
Test name
Test status
Simulation time 2478014531 ps
CPU time 2.54 seconds
Started Aug 17 04:50:02 PM PDT 24
Finished Aug 17 04:50:05 PM PDT 24
Peak memory 205260 kb
Host smart-03a6bd0e-bc28-4576-8554-8d84b823c52a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544113886 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.3544113886
Directory /workspace/36.rv_dm_stress_all/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.3817482598
Short name T77
Test name
Test status
Simulation time 35314794 ps
CPU time 0.77 seconds
Started Aug 17 04:50:00 PM PDT 24
Finished Aug 17 04:50:01 PM PDT 24
Peak memory 204880 kb
Host smart-51f9a7ae-4310-44b7-ab01-8b887001862d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817482598 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.3817482598
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_stress_all.1022493531
Short name T85
Test name
Test status
Simulation time 4564053085 ps
CPU time 6.94 seconds
Started Aug 17 04:50:09 PM PDT 24
Finished Aug 17 04:50:16 PM PDT 24
Peak memory 205204 kb
Host smart-a6090851-72d4-41c3-b035-557f9e138a6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022493531 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.1022493531
Directory /workspace/37.rv_dm_stress_all/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.373898964
Short name T213
Test name
Test status
Simulation time 106934620 ps
CPU time 1.02 seconds
Started Aug 17 04:49:54 PM PDT 24
Finished Aug 17 04:49:55 PM PDT 24
Peak memory 204888 kb
Host smart-e4c4c843-2828-4962-8d07-9806a7034192
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373898964 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.373898964
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.4003385113
Short name T278
Test name
Test status
Simulation time 94623813 ps
CPU time 0.79 seconds
Started Aug 17 04:50:00 PM PDT 24
Finished Aug 17 04:50:01 PM PDT 24
Peak memory 204852 kb
Host smart-4ede4ed3-d9cb-4bd0-89f7-d570753d4ce4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003385113 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.4003385113
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_stress_all.3546004270
Short name T318
Test name
Test status
Simulation time 3899019917 ps
CPU time 1.78 seconds
Started Aug 17 04:49:53 PM PDT 24
Finished Aug 17 04:49:55 PM PDT 24
Peak memory 205332 kb
Host smart-6012830b-cba9-4fbf-b76f-aed6b73e3a36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546004270 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.3546004270
Directory /workspace/39.rv_dm_stress_all/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.4009161740
Short name T247
Test name
Test status
Simulation time 63319857 ps
CPU time 0.72 seconds
Started Aug 17 04:49:50 PM PDT 24
Finished Aug 17 04:49:51 PM PDT 24
Peak memory 204904 kb
Host smart-29a433e1-601e-4ce4-ba81-d5384fe25539
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009161740 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.4009161740
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.4156479443
Short name T257
Test name
Test status
Simulation time 16355943342 ps
CPU time 9.53 seconds
Started Aug 17 04:49:46 PM PDT 24
Finished Aug 17 04:49:56 PM PDT 24
Peak memory 213608 kb
Host smart-c5af3697-f7a4-40fb-b6c1-ba81dd703ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156479443 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.4156479443
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.1795860918
Short name T250
Test name
Test status
Simulation time 8511504412 ps
CPU time 4.4 seconds
Started Aug 17 04:49:42 PM PDT 24
Finished Aug 17 04:49:47 PM PDT 24
Peak memory 214680 kb
Host smart-c3f5d5b8-0099-4ac0-9425-e71cefcd3e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795860918 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.1795860918
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_buffered_enable.4110112280
Short name T324
Test name
Test status
Simulation time 152731753 ps
CPU time 0.96 seconds
Started Aug 17 04:49:41 PM PDT 24
Finished Aug 17 04:49:43 PM PDT 24
Peak memory 226044 kb
Host smart-d276950e-6a78-4eee-a1c7-d30bfa8616ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110112280 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_buffered_enable.4110112280
Directory /workspace/4.rv_dm_buffered_enable/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.944234435
Short name T205
Test name
Test status
Simulation time 1657545240 ps
CPU time 2.63 seconds
Started Aug 17 04:49:49 PM PDT 24
Finished Aug 17 04:49:52 PM PDT 24
Peak memory 213236 kb
Host smart-5d714cee-8ec7-435a-a706-9794e9926f4e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=944234435 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_tl
_access.944234435
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_halt_resume_whereto.4144044369
Short name T45
Test name
Test status
Simulation time 229305734 ps
CPU time 1.02 seconds
Started Aug 17 04:49:41 PM PDT 24
Finished Aug 17 04:49:43 PM PDT 24
Peak memory 204904 kb
Host smart-fc3e7aad-264c-49e8-8093-75ba7f75125d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144044369 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_halt_resume_whereto.4144044369
Directory /workspace/4.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.3628209162
Short name T185
Test name
Test status
Simulation time 105140235 ps
CPU time 0.77 seconds
Started Aug 17 04:49:43 PM PDT 24
Finished Aug 17 04:49:44 PM PDT 24
Peak memory 204920 kb
Host smart-94f8c852-8c18-42dd-9e54-b75486d20d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628209162 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.3628209162
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.1477911600
Short name T262
Test name
Test status
Simulation time 5789118478 ps
CPU time 4.25 seconds
Started Aug 17 04:49:46 PM PDT 24
Finished Aug 17 04:49:50 PM PDT 24
Peak memory 213548 kb
Host smart-daef1e25-3efe-4228-b6e9-7994e4684a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477911600 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.1477911600
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.3999538075
Short name T54
Test name
Test status
Simulation time 535091957 ps
CPU time 2.12 seconds
Started Aug 17 04:49:52 PM PDT 24
Finished Aug 17 04:49:54 PM PDT 24
Peak memory 229308 kb
Host smart-86361c6a-0725-4af4-a456-b6034aa984b5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999538075 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.3999538075
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/4.rv_dm_stress_all.2287561195
Short name T283
Test name
Test status
Simulation time 3899051766 ps
CPU time 4.59 seconds
Started Aug 17 04:49:43 PM PDT 24
Finished Aug 17 04:49:48 PM PDT 24
Peak memory 205280 kb
Host smart-365888b6-4644-4377-b526-3d2d9b9b7738
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287561195 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.2287561195
Directory /workspace/4.rv_dm_stress_all/latest

Test location /workspace/coverage/default/4.rv_dm_stress_all_with_rand_reset.419248791
Short name T43
Test name
Test status
Simulation time 1841901790 ps
CPU time 37.73 seconds
Started Aug 17 04:49:39 PM PDT 24
Finished Aug 17 04:50:17 PM PDT 24
Peak memory 216948 kb
Host smart-4741343a-e8e9-437d-9ea3-6be516313ed8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419248791 -assert nopostp
roc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all_with_rand_reset.419248791
Directory /workspace/4.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.1316126922
Short name T312
Test name
Test status
Simulation time 62785502 ps
CPU time 0.77 seconds
Started Aug 17 04:49:57 PM PDT 24
Finished Aug 17 04:49:58 PM PDT 24
Peak memory 204848 kb
Host smart-f68085d1-572a-4c7d-86a6-6c1ece6211e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316126922 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.1316126922
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/40.rv_dm_stress_all.3704957258
Short name T23
Test name
Test status
Simulation time 6612641992 ps
CPU time 19.05 seconds
Started Aug 17 04:49:58 PM PDT 24
Finished Aug 17 04:50:17 PM PDT 24
Peak memory 205176 kb
Host smart-5dcc52e6-bba5-47b1-859a-bd3ddf87ff0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704957258 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.3704957258
Directory /workspace/40.rv_dm_stress_all/latest

Test location /workspace/coverage/default/41.rv_dm_stress_all.1127027886
Short name T308
Test name
Test status
Simulation time 2561472538 ps
CPU time 7.92 seconds
Started Aug 17 04:50:08 PM PDT 24
Finished Aug 17 04:50:16 PM PDT 24
Peak memory 204584 kb
Host smart-893d3ed4-0e1c-42cf-aeb7-49f9aaacff2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127027886 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.1127027886
Directory /workspace/41.rv_dm_stress_all/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.594033975
Short name T167
Test name
Test status
Simulation time 169425121 ps
CPU time 0.7 seconds
Started Aug 17 04:49:48 PM PDT 24
Finished Aug 17 04:49:49 PM PDT 24
Peak memory 205020 kb
Host smart-8df2f3d9-6fa6-4ccb-ae7f-c83d32e3a329
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594033975 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.594033975
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_stress_all.323554709
Short name T24
Test name
Test status
Simulation time 3191629556 ps
CPU time 6.18 seconds
Started Aug 17 04:49:58 PM PDT 24
Finished Aug 17 04:50:04 PM PDT 24
Peak memory 205236 kb
Host smart-9a7f533b-8196-40d7-9fd8-2b845d9922b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323554709 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.323554709
Directory /workspace/42.rv_dm_stress_all/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.1477863351
Short name T320
Test name
Test status
Simulation time 117431706 ps
CPU time 0.75 seconds
Started Aug 17 04:50:01 PM PDT 24
Finished Aug 17 04:50:01 PM PDT 24
Peak memory 204964 kb
Host smart-b0acd329-b701-4a4f-8b66-c3cec128ba4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477863351 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.1477863351
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_stress_all.3208193653
Short name T294
Test name
Test status
Simulation time 5294578570 ps
CPU time 15.29 seconds
Started Aug 17 04:50:00 PM PDT 24
Finished Aug 17 04:50:15 PM PDT 24
Peak memory 213432 kb
Host smart-e6dd31fa-3384-4002-a507-ef8c21dc0a0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208193653 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.3208193653
Directory /workspace/43.rv_dm_stress_all/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.1142028111
Short name T288
Test name
Test status
Simulation time 62684594 ps
CPU time 0.71 seconds
Started Aug 17 04:49:53 PM PDT 24
Finished Aug 17 04:49:54 PM PDT 24
Peak memory 204912 kb
Host smart-47b3dd43-487c-4de4-8181-7558f7848532
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142028111 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.1142028111
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_stress_all.1863704864
Short name T17
Test name
Test status
Simulation time 1680041142 ps
CPU time 3.45 seconds
Started Aug 17 04:49:56 PM PDT 24
Finished Aug 17 04:49:59 PM PDT 24
Peak memory 213400 kb
Host smart-c0388ef6-cde1-4626-8449-200a45e74bdd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863704864 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.1863704864
Directory /workspace/44.rv_dm_stress_all/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.2428747124
Short name T52
Test name
Test status
Simulation time 75388488 ps
CPU time 0.77 seconds
Started Aug 17 04:50:00 PM PDT 24
Finished Aug 17 04:50:01 PM PDT 24
Peak memory 204848 kb
Host smart-0f5ce998-aa1d-42f0-9b4f-68abefc66c22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428747124 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.2428747124
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_stress_all.2663699102
Short name T173
Test name
Test status
Simulation time 3475647932 ps
CPU time 11.79 seconds
Started Aug 17 04:50:02 PM PDT 24
Finished Aug 17 04:50:14 PM PDT 24
Peak memory 213500 kb
Host smart-7b77adbc-4d00-409e-a0c4-01a9d1de85d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663699102 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.2663699102
Directory /workspace/45.rv_dm_stress_all/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.194441301
Short name T272
Test name
Test status
Simulation time 146412810 ps
CPU time 1.07 seconds
Started Aug 17 04:50:09 PM PDT 24
Finished Aug 17 04:50:10 PM PDT 24
Peak memory 204948 kb
Host smart-56dceeef-6e97-4b29-ac29-1b82999912c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194441301 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.194441301
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_stress_all.3806455262
Short name T253
Test name
Test status
Simulation time 839913573 ps
CPU time 1.56 seconds
Started Aug 17 04:50:02 PM PDT 24
Finished Aug 17 04:50:04 PM PDT 24
Peak memory 205112 kb
Host smart-dc95f4db-8a54-4155-b7a9-85fbb3db5962
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806455262 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.3806455262
Directory /workspace/46.rv_dm_stress_all/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.526193913
Short name T281
Test name
Test status
Simulation time 77780724 ps
CPU time 0.7 seconds
Started Aug 17 04:49:58 PM PDT 24
Finished Aug 17 04:49:59 PM PDT 24
Peak memory 204936 kb
Host smart-3774c7ae-d09a-4297-8e9d-261ca5bc473f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526193913 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.526193913
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_stress_all.2530227108
Short name T174
Test name
Test status
Simulation time 3151712486 ps
CPU time 5.67 seconds
Started Aug 17 04:50:06 PM PDT 24
Finished Aug 17 04:50:12 PM PDT 24
Peak memory 205136 kb
Host smart-3316a481-f2fd-450b-a927-18ef325d6811
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530227108 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.2530227108
Directory /workspace/47.rv_dm_stress_all/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.2224665564
Short name T222
Test name
Test status
Simulation time 69444943 ps
CPU time 0.81 seconds
Started Aug 17 04:49:59 PM PDT 24
Finished Aug 17 04:50:00 PM PDT 24
Peak memory 205000 kb
Host smart-02636f8a-8797-44b7-9871-00bd4d70e5a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224665564 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.2224665564
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_stress_all.2732153131
Short name T299
Test name
Test status
Simulation time 2508976305 ps
CPU time 3.25 seconds
Started Aug 17 04:50:09 PM PDT 24
Finished Aug 17 04:50:13 PM PDT 24
Peak memory 205144 kb
Host smart-985ab2c3-8b60-4211-bcd4-0aa548931c9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732153131 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.2732153131
Directory /workspace/48.rv_dm_stress_all/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.3901346935
Short name T232
Test name
Test status
Simulation time 51583102 ps
CPU time 0.81 seconds
Started Aug 17 04:50:11 PM PDT 24
Finished Aug 17 04:50:12 PM PDT 24
Peak memory 205060 kb
Host smart-366eca86-ad85-4952-b50d-27429bc64754
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901346935 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.3901346935
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_stress_all.2493116292
Short name T20
Test name
Test status
Simulation time 7038101205 ps
CPU time 6.13 seconds
Started Aug 17 04:50:00 PM PDT 24
Finished Aug 17 04:50:07 PM PDT 24
Peak memory 205252 kb
Host smart-f4fd3bc5-c34d-4a22-b449-8459a48392b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493116292 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.2493116292
Directory /workspace/49.rv_dm_stress_all/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.75278162
Short name T305
Test name
Test status
Simulation time 90895187 ps
CPU time 0.72 seconds
Started Aug 17 04:49:49 PM PDT 24
Finished Aug 17 04:49:50 PM PDT 24
Peak memory 204752 kb
Host smart-dd7edde8-7736-46ac-8938-355a55d6ef1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75278162 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.75278162
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.144773635
Short name T110
Test name
Test status
Simulation time 3116852145 ps
CPU time 8.89 seconds
Started Aug 17 04:49:37 PM PDT 24
Finished Aug 17 04:49:46 PM PDT 24
Peak memory 205388 kb
Host smart-d79093af-1b55-456c-8a26-391f3f39e12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144773635 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.144773635
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_buffered_enable.2814149727
Short name T280
Test name
Test status
Simulation time 140770757 ps
CPU time 1.11 seconds
Started Aug 17 04:49:41 PM PDT 24
Finished Aug 17 04:49:43 PM PDT 24
Peak memory 225944 kb
Host smart-382b03ce-195b-46e3-be4f-106106cf6861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814149727 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_buffered_enable.2814149727
Directory /workspace/5.rv_dm_buffered_enable/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.2792955807
Short name T277
Test name
Test status
Simulation time 2776812642 ps
CPU time 8.37 seconds
Started Aug 17 04:49:46 PM PDT 24
Finished Aug 17 04:49:55 PM PDT 24
Peak memory 205356 kb
Host smart-75daa5be-a2eb-4472-ba21-3e231c08f02d
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2792955807 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t
l_access.2792955807
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_halt_resume_whereto.2700719882
Short name T261
Test name
Test status
Simulation time 263635985 ps
CPU time 0.96 seconds
Started Aug 17 04:49:43 PM PDT 24
Finished Aug 17 04:49:44 PM PDT 24
Peak memory 204884 kb
Host smart-a18ca069-f646-4aed-8940-a99262e87b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700719882 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_halt_resume_whereto.2700719882
Directory /workspace/5.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.3950398140
Short name T165
Test name
Test status
Simulation time 5782864589 ps
CPU time 15.4 seconds
Started Aug 17 04:49:44 PM PDT 24
Finished Aug 17 04:49:59 PM PDT 24
Peak memory 213580 kb
Host smart-960b0d59-0a81-4408-88e7-2564e6c87154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950398140 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.3950398140
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_stress_all.29650955
Short name T7
Test name
Test status
Simulation time 1223135942 ps
CPU time 4.24 seconds
Started Aug 17 04:49:46 PM PDT 24
Finished Aug 17 04:49:51 PM PDT 24
Peak memory 205184 kb
Host smart-3e8f0854-52bb-40e2-acd3-b82d8818e3c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29650955 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.29650955
Directory /workspace/5.rv_dm_stress_all/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.3907839703
Short name T307
Test name
Test status
Simulation time 117048242 ps
CPU time 0.77 seconds
Started Aug 17 04:49:47 PM PDT 24
Finished Aug 17 04:49:48 PM PDT 24
Peak memory 204996 kb
Host smart-ef3099b2-194d-4296-acf1-d39fb00fe52c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907839703 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.3907839703
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.882001080
Short name T266
Test name
Test status
Simulation time 11631477729 ps
CPU time 33.16 seconds
Started Aug 17 04:49:39 PM PDT 24
Finished Aug 17 04:50:12 PM PDT 24
Peak memory 205456 kb
Host smart-8b3aa419-2125-4334-aeb5-87cc453c01de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882001080 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.882001080
Directory /workspace/6.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.3346720290
Short name T209
Test name
Test status
Simulation time 10746483024 ps
CPU time 27.44 seconds
Started Aug 17 04:49:35 PM PDT 24
Finished Aug 17 04:50:02 PM PDT 24
Peak memory 213560 kb
Host smart-957dc8af-c5d3-4061-bcba-65ef9a5c2d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346720290 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.3346720290
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_buffered_enable.358332889
Short name T221
Test name
Test status
Simulation time 384959916 ps
CPU time 1.15 seconds
Started Aug 17 04:49:46 PM PDT 24
Finished Aug 17 04:49:47 PM PDT 24
Peak memory 226064 kb
Host smart-e47bf084-b51e-4300-b692-467f128ad29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358332889 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_buffered_enable.358332889
Directory /workspace/6.rv_dm_buffered_enable/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.375356777
Short name T86
Test name
Test status
Simulation time 5934234361 ps
CPU time 8.8 seconds
Started Aug 17 04:49:43 PM PDT 24
Finished Aug 17 04:49:52 PM PDT 24
Peak memory 205340 kb
Host smart-f979cef1-c91f-4b76-99cb-2db0b8c04e3f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=375356777 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_tl
_access.375356777
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_halt_resume_whereto.716317958
Short name T275
Test name
Test status
Simulation time 386603319 ps
CPU time 1.64 seconds
Started Aug 17 04:49:35 PM PDT 24
Finished Aug 17 04:49:37 PM PDT 24
Peak memory 204916 kb
Host smart-b866ce87-94ca-4781-b1fd-b2ca7baab22d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716317958 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_halt_resume_whereto.716317958
Directory /workspace/6.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.3128677782
Short name T204
Test name
Test status
Simulation time 2678678171 ps
CPU time 8.72 seconds
Started Aug 17 04:49:44 PM PDT 24
Finished Aug 17 04:49:52 PM PDT 24
Peak memory 205396 kb
Host smart-7b4e3446-d943-462f-a363-7e674e64c05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128677782 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.3128677782
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_stress_all.966950004
Short name T22
Test name
Test status
Simulation time 2472615454 ps
CPU time 2.62 seconds
Started Aug 17 04:49:39 PM PDT 24
Finished Aug 17 04:49:42 PM PDT 24
Peak memory 213448 kb
Host smart-54f1f2ea-f188-47e1-99a2-81b7b93d2396
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966950004 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.966950004
Directory /workspace/6.rv_dm_stress_all/latest

Test location /workspace/coverage/default/6.rv_dm_stress_all_with_rand_reset.1377943888
Short name T116
Test name
Test status
Simulation time 2060365217 ps
CPU time 30.3 seconds
Started Aug 17 04:49:36 PM PDT 24
Finished Aug 17 04:50:07 PM PDT 24
Peak memory 215392 kb
Host smart-4224677d-d544-4ab2-bf07-2e91cb93b1be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377943888 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all_with_rand_reset.1377943888
Directory /workspace/6.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.2851860710
Short name T322
Test name
Test status
Simulation time 157212487 ps
CPU time 0.77 seconds
Started Aug 17 04:49:49 PM PDT 24
Finished Aug 17 04:49:50 PM PDT 24
Peak memory 204896 kb
Host smart-ebd4dc5a-0571-4da5-844a-d98c4c3c650b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851860710 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.2851860710
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.4241151764
Short name T323
Test name
Test status
Simulation time 37928828015 ps
CPU time 66.1 seconds
Started Aug 17 04:49:42 PM PDT 24
Finished Aug 17 04:50:48 PM PDT 24
Peak memory 217556 kb
Host smart-f59052ba-5486-49a1-aa46-35e278df1c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241151764 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.4241151764
Directory /workspace/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.1944415508
Short name T207
Test name
Test status
Simulation time 2870262161 ps
CPU time 8.78 seconds
Started Aug 17 04:49:48 PM PDT 24
Finished Aug 17 04:49:57 PM PDT 24
Peak memory 205416 kb
Host smart-8e8d63df-5847-4002-b3d5-7a1d9fb8272a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944415508 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.1944415508
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_buffered_enable.2610655453
Short name T50
Test name
Test status
Simulation time 626222285 ps
CPU time 1.45 seconds
Started Aug 17 04:49:54 PM PDT 24
Finished Aug 17 04:49:56 PM PDT 24
Peak memory 224920 kb
Host smart-19099c04-079f-4eb2-aa57-5fe6d7103ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610655453 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_buffered_enable.2610655453
Directory /workspace/7.rv_dm_buffered_enable/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.1830697592
Short name T228
Test name
Test status
Simulation time 9586407214 ps
CPU time 12.12 seconds
Started Aug 17 04:49:44 PM PDT 24
Finished Aug 17 04:49:56 PM PDT 24
Peak memory 213516 kb
Host smart-85ce2b9f-90a6-4162-8637-ac61ca533279
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1830697592 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t
l_access.1830697592
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_halt_resume_whereto.2109644418
Short name T42
Test name
Test status
Simulation time 630146837 ps
CPU time 1.01 seconds
Started Aug 17 04:49:42 PM PDT 24
Finished Aug 17 04:49:43 PM PDT 24
Peak memory 205000 kb
Host smart-15be25b3-ac85-4d32-ade5-7e5430eac476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109644418 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_halt_resume_whereto.2109644418
Directory /workspace/7.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.2000583286
Short name T206
Test name
Test status
Simulation time 6398057754 ps
CPU time 10.2 seconds
Started Aug 17 04:49:47 PM PDT 24
Finished Aug 17 04:49:57 PM PDT 24
Peak memory 213620 kb
Host smart-42738665-e85c-49c7-96d8-dca7cf8fd988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000583286 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.2000583286
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_stress_all.514221691
Short name T186
Test name
Test status
Simulation time 3461524032 ps
CPU time 9.85 seconds
Started Aug 17 04:49:49 PM PDT 24
Finished Aug 17 04:49:59 PM PDT 24
Peak memory 205272 kb
Host smart-c3dc5a51-0631-4dd9-ba9a-dd501f90dce8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514221691 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.514221691
Directory /workspace/7.rv_dm_stress_all/latest

Test location /workspace/coverage/default/7.rv_dm_stress_all_with_rand_reset.3048889156
Short name T117
Test name
Test status
Simulation time 5630600187 ps
CPU time 31.35 seconds
Started Aug 17 04:49:51 PM PDT 24
Finished Aug 17 04:50:22 PM PDT 24
Peak memory 217844 kb
Host smart-20764314-e839-4214-be20-22d196893e06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048889156 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all_with_rand_reset.3048889156
Directory /workspace/7.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.332869410
Short name T163
Test name
Test status
Simulation time 53677999 ps
CPU time 0.73 seconds
Started Aug 17 04:49:55 PM PDT 24
Finished Aug 17 04:49:56 PM PDT 24
Peak memory 204896 kb
Host smart-54da2594-91ef-4fa0-a692-560c734f5270
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332869410 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.332869410
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.1846262944
Short name T306
Test name
Test status
Simulation time 6383305790 ps
CPU time 3.44 seconds
Started Aug 17 04:49:51 PM PDT 24
Finished Aug 17 04:49:54 PM PDT 24
Peak memory 213520 kb
Host smart-60748f20-8478-4f21-95ce-e160688a46af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846262944 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.1846262944
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_buffered_enable.2982494037
Short name T223
Test name
Test status
Simulation time 132579845 ps
CPU time 1.01 seconds
Started Aug 17 04:49:58 PM PDT 24
Finished Aug 17 04:49:59 PM PDT 24
Peak memory 225460 kb
Host smart-7c4f2926-9402-4304-a5d8-3132b1218b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982494037 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_buffered_enable.2982494037
Directory /workspace/8.rv_dm_buffered_enable/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.743978691
Short name T242
Test name
Test status
Simulation time 6036334150 ps
CPU time 19.15 seconds
Started Aug 17 04:49:53 PM PDT 24
Finished Aug 17 04:50:12 PM PDT 24
Peak memory 205420 kb
Host smart-271f30b3-b7f0-4413-be89-c941afbdb486
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=743978691 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_tl
_access.743978691
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.1554847871
Short name T256
Test name
Test status
Simulation time 1502281863 ps
CPU time 3.23 seconds
Started Aug 17 04:49:51 PM PDT 24
Finished Aug 17 04:49:55 PM PDT 24
Peak memory 205236 kb
Host smart-ac781871-050a-4d5a-8a95-e6ad4048a08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554847871 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.1554847871
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_stress_all.160951078
Short name T302
Test name
Test status
Simulation time 5491026338 ps
CPU time 4.74 seconds
Started Aug 17 04:49:52 PM PDT 24
Finished Aug 17 04:49:57 PM PDT 24
Peak memory 213528 kb
Host smart-021867b9-d90d-40f5-847a-ae0eb7c6a3de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160951078 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.160951078
Directory /workspace/8.rv_dm_stress_all/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.1383631242
Short name T73
Test name
Test status
Simulation time 60567493 ps
CPU time 0.72 seconds
Started Aug 17 04:50:02 PM PDT 24
Finished Aug 17 04:50:03 PM PDT 24
Peak memory 204992 kb
Host smart-06f3f6ad-7bf4-4a77-97c2-890f5511dd9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383631242 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.1383631242
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.1094959656
Short name T188
Test name
Test status
Simulation time 2125471333 ps
CPU time 6.56 seconds
Started Aug 17 04:49:43 PM PDT 24
Finished Aug 17 04:49:50 PM PDT 24
Peak memory 205288 kb
Host smart-c011560c-b339-42d0-9a5e-e2c0dd751725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094959656 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.1094959656
Directory /workspace/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_buffered_enable.1012819444
Short name T227
Test name
Test status
Simulation time 527565251 ps
CPU time 1.14 seconds
Started Aug 17 04:49:47 PM PDT 24
Finished Aug 17 04:49:48 PM PDT 24
Peak memory 226144 kb
Host smart-39706e7b-88fd-4e25-956e-3a7193138500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012819444 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_buffered_enable.1012819444
Directory /workspace/9.rv_dm_buffered_enable/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.2254647976
Short name T264
Test name
Test status
Simulation time 6463194081 ps
CPU time 18.5 seconds
Started Aug 17 04:50:01 PM PDT 24
Finished Aug 17 04:50:20 PM PDT 24
Peak memory 213460 kb
Host smart-c382ea86-c7d4-4e7e-a079-19b2922b0312
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2254647976 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t
l_access.2254647976
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.2206627095
Short name T189
Test name
Test status
Simulation time 7076148801 ps
CPU time 5.87 seconds
Started Aug 17 04:49:51 PM PDT 24
Finished Aug 17 04:49:57 PM PDT 24
Peak memory 205424 kb
Host smart-ddb4e577-2688-42eb-b872-c845316009ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206627095 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.2206627095
Directory /workspace/9.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_stress_all.3051611115
Short name T74
Test name
Test status
Simulation time 3499998451 ps
CPU time 8.29 seconds
Started Aug 17 04:49:53 PM PDT 24
Finished Aug 17 04:50:01 PM PDT 24
Peak memory 213440 kb
Host smart-de0fa390-3398-4aea-902c-abd514142d53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051611115 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.3051611115
Directory /workspace/9.rv_dm_stress_all/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%