| | | | | | | |
dm_csrs |
68.87 |
86.28 |
62.67 |
|
|
57.65 |
|
prim_sync_reqack |
79.17 |
100.00 |
66.67 |
|
|
100.00 |
50.00 |
dm_mem |
80.50 |
87.89 |
64.52 |
|
83.33 |
86.25 |
|
prim_alert_sender |
83.33 |
|
|
83.33 |
|
|
|
tlul_lc_gate |
85.83 |
100.00 |
83.33 |
|
100.00 |
95.83 |
50.00 |
dmi_jtag |
87.64 |
94.32 |
90.57 |
|
83.33 |
82.35 |
|
prim_secded_inv_64_57_dec |
89.23 |
|
|
89.23 |
|
|
|
prim_fifo_sync |
90.62 |
100.00 |
62.50 |
|
|
100.00 |
100.00 |
tlul_rsp_intg_gen |
91.67 |
83.33 |
|
|
|
|
100.00 |
tlul_rsp_intg_gen |
100.00 |
|
|
|
|
|
100.00 |
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=0,EnableDataIntgGen=0 ) |
66.67 |
66.67 |
|
|
|
|
|
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=1,EnableDataIntgGen=1 ) |
100.00 |
100.00 |
|
|
|
|
|
prim_fifo_sync_cnt |
93.64 |
100.00 |
90.00 |
|
|
90.91 |
|
rv_dm |
95.55 |
100.00 |
85.11 |
92.63 |
|
100.00 |
100.00 |
prim_fifo_async_simple |
95.83 |
100.00 |
87.50 |
|
|
100.00 |
|
tlul_err_resp |
96.67 |
100.00 |
90.00 |
|
|
100.00 |
|
dmi_jtag_tap |
97.77 |
100.00 |
100.00 |
|
92.50 |
98.57 |
|
tlul_adapter_reg |
98.14 |
98.96 |
95.97 |
|
|
97.62 |
100.00 |
tlul_adapter_reg |
100.00 |
|
|
|
|
|
100.00 |
tlul_adapter_reg ( parameter CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,RegAw=4,RegDw=32,AccessLatency=0,RegBw=4,IW=8,SZW=2 ) |
98.55 |
100.00 |
95.65 |
|
|
100.00 |
|
tlul_adapter_reg ( parameter CmdIntgCheck=1,EnableRspIntgGen=1,EnableDataIntgGen=1,RegAw=12,RegDw=32,AccessLatency=1,RegBw=4,IW=8,SZW=2 ) |
96.48 |
97.92 |
96.30 |
|
|
95.24 |
|
dm_sba |
98.53 |
100.00 |
100.00 |
|
100.00 |
94.12 |
|
tlul_assert |
99.13 |
100.00 |
|
|
|
100.00 |
97.39 |
rv_dm_regs_csr_assert_fpv |
100.00 |
|
|
|
|
|
100.00 |
prim_mubi8_sync |
100.00 |
100.00 |
|
|
|
|
100.00 |
prim_generic_clock_mux2 |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
prim_lc_sync |
100.00 |
100.00 |
|
|
|
|
100.00 |
prim_lc_sync |
100.00 |
|
|
|
|
|
100.00 |
prim_lc_sync ( parameter NumCopies=1,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 ) |
100.00 |
100.00 |
|
|
|
|
|
prim_lc_sync ( parameter NumCopies=2,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 ) |
100.00 |
100.00 |
|
|
|
|
|
prim_lc_sync ( parameter NumCopies=3,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 ) |
100.00 |
100.00 |
|
|
|
|
|
prim_lc_sync ( parameter NumCopies=5,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 ) |
100.00 |
100.00 |
|
|
|
|
|
tlul_data_integ_dec |
100.00 |
100.00 |
|
|
|
|
|
tlul_rsp_intg_chk |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
prim_sparse_fsm_flop |
100.00 |
100.00 |
|
|
|
|
100.00 |
tlul_cmd_intg_chk |
100.00 |
100.00 |
|
|
|
|
100.00 |
tlul_cmd_intg_gen |
100.00 |
100.00 |
|
|
|
|
100.00 |
prim_generic_and2 |
100.00 |
100.00 |
|
|
|
|
|
prim_onehot_check |
100.00 |
|
|
100.00 |
|
|
|
rv_dm_enable_checker |
100.00 |
100.00 |
|
|
|
|
100.00 |
prim_subreg |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
prim_subreg |
100.00 |
100.00 |
|
|
|
100.00 |
|
prim_subreg ( parameter DW=1,SwAccess=5,RESVAL=1,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg ( parameter DW=32,SwAccess=0,RESVAL=1768515945,Mubi=1 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_secded_inv_39_32_dec |
100.00 |
|
|
100.00 |
|
|
|
prim_generic_buf |
100.00 |
100.00 |
|
|
|
|
|
dm_top |
100.00 |
100.00 |
|
|
|
|
|
tlul_adapter_host |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
prim_subreg_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
prim_subreg_arb |
100.00 |
|
|
|
|
100.00 |
|
prim_subreg_arb ( parameter DW=1,SwAccess=5,Mubi=0 ) |
100.00 |
100.00 |
100.00 |
|
|
|
|
prim_subreg_arb ( parameter DW=32,SwAccess=0,Mubi=1 ) |
100.00 |
100.00 |
100.00 |
|
|
|
|
rv_dm_regs_reg_top |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
prim_subreg_ext |
100.00 |
100.00 |
|
|
|
|
|
prim_mubi32_sync |
100.00 |
100.00 |
|
|
|
|
100.00 |
prim_secded_inv_39_32_enc |
100.00 |
100.00 |
|
|
|
|
|
tlul_err |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
debug_rom |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
prim_secded_inv_64_57_enc |
100.00 |
100.00 |
|
|
|
|
|
dmi_cdc |
100.00 |
100.00 |
|
|
|
100.00 |
|
prim_generic_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
tlul_data_integ_enc |
|
|
|
|
|
|
|
prim_reg_we_check |
|
|
|
|
|
|
|
prim_clock_mux2 |
|
|
|
|
|
|
|
prim_blanker |
|
|
|
|
|
|
|
prim_buf |
|
|
|
|
|
|
|
prim_generic_flop_2sync |
|
|
|
|
|
|
|
prim_generic_clock_inv |
|
|
|
|
|
|
|
prim_clock_inv |
|
|
|
|
|
|
|
prim_flop |
|
|
|
|
|
|
|
prim_flop_2sync |
|
|
|
|
|
|
|
tb |
|
|
|
|
|
|
|
prim_and2 |
|
|
|
|
|
|
|
prim_sec_anchor_buf |
|
|
|
|
|
|
|