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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
87.82 96.32 89.53 92.10 92.00 90.44 98.21 56.10


Total test records in report: 483
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T314 /workspace/coverage/default/7.rv_dm_stress_all.1200719812 Aug 18 04:39:28 PM PDT 24 Aug 18 04:39:33 PM PDT 24 2094982805 ps
T171 /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.388477353 Aug 18 04:39:33 PM PDT 24 Aug 18 04:39:53 PM PDT 24 17855976837 ps
T315 /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.3036585479 Aug 18 04:39:11 PM PDT 24 Aug 18 04:39:13 PM PDT 24 671892833 ps
T316 /workspace/coverage/default/12.rv_dm_alert_test.850632912 Aug 18 04:39:39 PM PDT 24 Aug 18 04:39:40 PM PDT 24 129058635 ps
T317 /workspace/coverage/default/9.rv_dm_alert_test.3891177382 Aug 18 04:39:33 PM PDT 24 Aug 18 04:39:34 PM PDT 24 29618889 ps
T318 /workspace/coverage/default/1.rv_dm_smoke.2282506945 Aug 18 04:38:57 PM PDT 24 Aug 18 04:38:59 PM PDT 24 701243341 ps
T319 /workspace/coverage/default/21.rv_dm_alert_test.2214152419 Aug 18 04:39:45 PM PDT 24 Aug 18 04:39:46 PM PDT 24 154257940 ps
T320 /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.3576823486 Aug 18 04:39:42 PM PDT 24 Aug 18 04:40:52 PM PDT 24 47853051063 ps
T321 /workspace/coverage/default/1.rv_dm_halt_resume_whereto.2382859186 Aug 18 04:38:57 PM PDT 24 Aug 18 04:38:59 PM PDT 24 303162787 ps
T322 /workspace/coverage/default/1.rv_dm_sba_tl_access.2368099641 Aug 18 04:39:00 PM PDT 24 Aug 18 04:39:04 PM PDT 24 3869326870 ps
T323 /workspace/coverage/default/42.rv_dm_stress_all.3436397837 Aug 18 04:39:50 PM PDT 24 Aug 18 04:39:52 PM PDT 24 1095331073 ps
T324 /workspace/coverage/default/39.rv_dm_stress_all.1779993276 Aug 18 04:39:48 PM PDT 24 Aug 18 04:40:01 PM PDT 24 4148429795 ps
T325 /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.618029548 Aug 18 04:38:50 PM PDT 24 Aug 18 04:38:57 PM PDT 24 2139969674 ps
T101 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3750893761 Aug 18 04:35:12 PM PDT 24 Aug 18 04:35:16 PM PDT 24 112916789 ps
T102 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.703266943 Aug 18 04:35:03 PM PDT 24 Aug 18 04:35:42 PM PDT 24 14129364924 ps
T149 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.3149250939 Aug 18 04:35:05 PM PDT 24 Aug 18 04:35:32 PM PDT 24 5092562646 ps
T326 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.621093350 Aug 18 04:35:03 PM PDT 24 Aug 18 04:35:04 PM PDT 24 52083123 ps
T88 /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.563561548 Aug 18 04:35:07 PM PDT 24 Aug 18 04:35:58 PM PDT 24 2085864791 ps
T327 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.1653162626 Aug 18 04:35:12 PM PDT 24 Aug 18 04:35:13 PM PDT 24 112206387 ps
T103 /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.3016100003 Aug 18 04:35:22 PM PDT 24 Aug 18 04:35:28 PM PDT 24 486433203 ps
T104 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.4018575538 Aug 18 04:35:36 PM PDT 24 Aug 18 04:35:40 PM PDT 24 1027176534 ps
T328 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.1418592441 Aug 18 04:35:33 PM PDT 24 Aug 18 04:35:36 PM PDT 24 2416295453 ps
T105 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.2849652337 Aug 18 04:35:31 PM PDT 24 Aug 18 04:35:39 PM PDT 24 175519595 ps
T329 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.1309212184 Aug 18 04:35:33 PM PDT 24 Aug 18 04:35:40 PM PDT 24 2463736310 ps
T330 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.3911415357 Aug 18 04:35:27 PM PDT 24 Aug 18 04:35:32 PM PDT 24 531288771 ps
T138 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.2377008790 Aug 18 04:35:22 PM PDT 24 Aug 18 04:35:26 PM PDT 24 326397306 ps
T331 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.4109801933 Aug 18 04:35:22 PM PDT 24 Aug 18 04:35:29 PM PDT 24 5030367852 ps
T92 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2377286096 Aug 18 04:35:28 PM PDT 24 Aug 18 04:35:31 PM PDT 24 1138083250 ps
T106 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.2975166332 Aug 18 04:35:12 PM PDT 24 Aug 18 04:36:20 PM PDT 24 1217131353 ps
T332 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.1936969439 Aug 18 04:35:29 PM PDT 24 Aug 18 04:35:47 PM PDT 24 13356419433 ps
T150 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.581838681 Aug 18 04:35:23 PM PDT 24 Aug 18 04:35:45 PM PDT 24 2540269477 ps
T107 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.2503178370 Aug 18 04:35:20 PM PDT 24 Aug 18 04:35:22 PM PDT 24 214886854 ps
T108 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3917300734 Aug 18 04:34:56 PM PDT 24 Aug 18 04:35:28 PM PDT 24 2107942455 ps
T83 /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.1881204860 Aug 18 04:35:20 PM PDT 24 Aug 18 04:36:19 PM PDT 24 5038762090 ps
T93 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.583133166 Aug 18 04:35:00 PM PDT 24 Aug 18 04:35:01 PM PDT 24 420658130 ps
T333 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2314292705 Aug 18 04:35:09 PM PDT 24 Aug 18 04:35:14 PM PDT 24 74181404 ps
T86 /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.4162995481 Aug 18 04:35:12 PM PDT 24 Aug 18 04:35:57 PM PDT 24 2646342728 ps
T94 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.2353261814 Aug 18 04:34:55 PM PDT 24 Aug 18 04:34:56 PM PDT 24 200624917 ps
T109 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.4040695845 Aug 18 04:35:30 PM PDT 24 Aug 18 04:35:31 PM PDT 24 35606449 ps
T111 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2672910484 Aug 18 04:34:54 PM PDT 24 Aug 18 04:35:01 PM PDT 24 6797268717 ps
T334 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.1019932085 Aug 18 04:35:19 PM PDT 24 Aug 18 04:35:33 PM PDT 24 4676199103 ps
T335 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.1561571285 Aug 18 04:35:35 PM PDT 24 Aug 18 04:35:36 PM PDT 24 194170237 ps
T110 /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.4279668453 Aug 18 04:35:36 PM PDT 24 Aug 18 04:35:40 PM PDT 24 201668834 ps
T115 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.2865245728 Aug 18 04:35:21 PM PDT 24 Aug 18 04:35:29 PM PDT 24 806526368 ps
T336 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.2540226538 Aug 18 04:35:08 PM PDT 24 Aug 18 04:35:09 PM PDT 24 60691182 ps
T116 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.3639169111 Aug 18 04:35:20 PM PDT 24 Aug 18 04:35:22 PM PDT 24 163706639 ps
T337 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2693507425 Aug 18 04:35:14 PM PDT 24 Aug 18 04:35:17 PM PDT 24 139573712 ps
T139 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.3266396672 Aug 18 04:35:19 PM PDT 24 Aug 18 04:35:40 PM PDT 24 2131774755 ps
T338 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.1575286536 Aug 18 04:35:07 PM PDT 24 Aug 18 04:35:10 PM PDT 24 100650153 ps
T117 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.1167799430 Aug 18 04:35:11 PM PDT 24 Aug 18 04:35:38 PM PDT 24 757496782 ps
T118 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.223836295 Aug 18 04:35:12 PM PDT 24 Aug 18 04:35:15 PM PDT 24 313444485 ps
T339 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.4085629444 Aug 18 04:35:30 PM PDT 24 Aug 18 04:35:33 PM PDT 24 149585872 ps
T80 /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.3707725047 Aug 18 04:35:12 PM PDT 24 Aug 18 04:35:32 PM PDT 24 22141253784 ps
T55 /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.1386674755 Aug 18 04:35:23 PM PDT 24 Aug 18 04:36:53 PM PDT 24 11101109940 ps
T340 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.578449369 Aug 18 04:35:28 PM PDT 24 Aug 18 04:35:30 PM PDT 24 55343990 ps
T81 /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.1915586552 Aug 18 04:35:13 PM PDT 24 Aug 18 04:36:22 PM PDT 24 18816847369 ps
T119 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.4064000695 Aug 18 04:35:08 PM PDT 24 Aug 18 04:35:10 PM PDT 24 82581972 ps
T126 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.21953711 Aug 18 04:35:22 PM PDT 24 Aug 18 04:35:24 PM PDT 24 81485696 ps
T341 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.47982419 Aug 18 04:34:55 PM PDT 24 Aug 18 04:35:09 PM PDT 24 8481714374 ps
T127 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.4006432120 Aug 18 04:34:56 PM PDT 24 Aug 18 04:35:29 PM PDT 24 17220540817 ps
T140 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.3993398489 Aug 18 04:35:22 PM PDT 24 Aug 18 04:35:25 PM PDT 24 269325902 ps
T141 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3364051618 Aug 18 04:35:34 PM PDT 24 Aug 18 04:35:57 PM PDT 24 5619763669 ps
T342 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.2413775548 Aug 18 04:35:24 PM PDT 24 Aug 18 04:35:49 PM PDT 24 9485286578 ps
T91 /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.785484077 Aug 18 04:35:21 PM PDT 24 Aug 18 04:35:24 PM PDT 24 84050036 ps
T343 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.1413357446 Aug 18 04:35:36 PM PDT 24 Aug 18 04:35:39 PM PDT 24 74913789 ps
T344 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.2658976706 Aug 18 04:35:29 PM PDT 24 Aug 18 04:35:33 PM PDT 24 215071074 ps
T134 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.3155633515 Aug 18 04:35:20 PM PDT 24 Aug 18 04:35:24 PM PDT 24 395842236 ps
T89 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.3234175307 Aug 18 04:35:22 PM PDT 24 Aug 18 04:35:26 PM PDT 24 103151587 ps
T120 /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.1146699019 Aug 18 04:35:28 PM PDT 24 Aug 18 04:35:33 PM PDT 24 247216114 ps
T345 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.4200185367 Aug 18 04:35:11 PM PDT 24 Aug 18 04:35:26 PM PDT 24 15549691760 ps
T181 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.1411102456 Aug 18 04:35:20 PM PDT 24 Aug 18 04:35:32 PM PDT 24 2928908147 ps
T346 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.1259917365 Aug 18 04:35:19 PM PDT 24 Aug 18 04:36:04 PM PDT 24 21071005189 ps
T347 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.1709045356 Aug 18 04:35:14 PM PDT 24 Aug 18 04:35:17 PM PDT 24 2369443250 ps
T348 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3106483979 Aug 18 04:35:00 PM PDT 24 Aug 18 04:35:03 PM PDT 24 1081119168 ps
T349 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.4050057278 Aug 18 04:35:20 PM PDT 24 Aug 18 04:35:34 PM PDT 24 8814522280 ps
T350 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.3151888346 Aug 18 04:35:29 PM PDT 24 Aug 18 04:35:31 PM PDT 24 159427485 ps
T135 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.3508782654 Aug 18 04:35:06 PM PDT 24 Aug 18 04:35:13 PM PDT 24 419174556 ps
T351 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.3833047365 Aug 18 04:35:24 PM PDT 24 Aug 18 04:35:26 PM PDT 24 681055186 ps
T128 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.3647946147 Aug 18 04:35:05 PM PDT 24 Aug 18 04:35:07 PM PDT 24 148741362 ps
T352 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.3497813868 Aug 18 04:35:22 PM PDT 24 Aug 18 04:35:26 PM PDT 24 243701552 ps
T353 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.3186678881 Aug 18 04:35:26 PM PDT 24 Aug 18 04:35:27 PM PDT 24 248268900 ps
T354 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.3845548953 Aug 18 04:35:11 PM PDT 24 Aug 18 04:35:13 PM PDT 24 485296054 ps
T355 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3664511578 Aug 18 04:35:35 PM PDT 24 Aug 18 04:35:37 PM PDT 24 762883572 ps
T356 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.1133837046 Aug 18 04:35:11 PM PDT 24 Aug 18 04:35:15 PM PDT 24 1707467994 ps
T112 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.2242384727 Aug 18 04:35:04 PM PDT 24 Aug 18 04:35:17 PM PDT 24 17203477484 ps
T357 /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.956591553 Aug 18 04:35:21 PM PDT 24 Aug 18 04:35:25 PM PDT 24 298679380 ps
T358 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.3583267076 Aug 18 04:35:04 PM PDT 24 Aug 18 04:35:05 PM PDT 24 36102485 ps
T359 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1142418522 Aug 18 04:35:13 PM PDT 24 Aug 18 04:35:53 PM PDT 24 21319618428 ps
T129 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.338050421 Aug 18 04:35:26 PM PDT 24 Aug 18 04:35:28 PM PDT 24 188108011 ps
T360 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.172808954 Aug 18 04:35:04 PM PDT 24 Aug 18 04:35:05 PM PDT 24 249651643 ps
T361 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.2764955129 Aug 18 04:35:18 PM PDT 24 Aug 18 04:35:28 PM PDT 24 13840695131 ps
T362 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.2078773259 Aug 18 04:35:35 PM PDT 24 Aug 18 04:35:37 PM PDT 24 53914681 ps
T363 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.656050854 Aug 18 04:35:30 PM PDT 24 Aug 18 04:35:32 PM PDT 24 1587917892 ps
T364 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.507477509 Aug 18 04:35:12 PM PDT 24 Aug 18 04:35:18 PM PDT 24 116823640 ps
T365 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2981339025 Aug 18 04:35:04 PM PDT 24 Aug 18 04:35:55 PM PDT 24 18121152314 ps
T179 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3846361258 Aug 18 04:35:26 PM PDT 24 Aug 18 04:35:38 PM PDT 24 1148603635 ps
T366 /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.330117126 Aug 18 04:35:24 PM PDT 24 Aug 18 04:36:00 PM PDT 24 4185741008 ps
T367 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1445825833 Aug 18 04:35:02 PM PDT 24 Aug 18 04:40:57 PM PDT 24 139936038588 ps
T368 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.433420679 Aug 18 04:35:23 PM PDT 24 Aug 18 04:35:29 PM PDT 24 6469225394 ps
T369 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.1676516411 Aug 18 04:35:03 PM PDT 24 Aug 18 04:35:05 PM PDT 24 150585820 ps
T370 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.3395756311 Aug 18 04:35:14 PM PDT 24 Aug 18 04:35:48 PM PDT 24 43909436270 ps
T371 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.4180961278 Aug 18 04:35:31 PM PDT 24 Aug 18 04:35:51 PM PDT 24 2572301625 ps
T372 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2324690530 Aug 18 04:35:12 PM PDT 24 Aug 18 04:35:23 PM PDT 24 3489095255 ps
T373 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.1000112657 Aug 18 04:35:08 PM PDT 24 Aug 18 04:35:14 PM PDT 24 413067409 ps
T374 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.883256592 Aug 18 04:35:13 PM PDT 24 Aug 18 04:35:14 PM PDT 24 230574575 ps
T375 /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.682514315 Aug 18 04:35:24 PM PDT 24 Aug 18 04:35:28 PM PDT 24 165573220 ps
T376 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.3383939400 Aug 18 04:35:19 PM PDT 24 Aug 18 04:35:22 PM PDT 24 674190447 ps
T377 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.964312775 Aug 18 04:35:24 PM PDT 24 Aug 18 04:35:27 PM PDT 24 162937515 ps
T378 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.2471351807 Aug 18 04:35:05 PM PDT 24 Aug 18 04:35:07 PM PDT 24 178722062 ps
T136 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.2862989813 Aug 18 04:35:24 PM PDT 24 Aug 18 04:35:28 PM PDT 24 377206667 ps
T379 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.1843047875 Aug 18 04:34:57 PM PDT 24 Aug 18 04:35:20 PM PDT 24 11785231290 ps
T380 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.181253990 Aug 18 04:35:13 PM PDT 24 Aug 18 04:36:09 PM PDT 24 1845039327 ps
T381 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.1348826469 Aug 18 04:35:36 PM PDT 24 Aug 18 04:35:51 PM PDT 24 5014915508 ps
T382 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.4206691621 Aug 18 04:35:14 PM PDT 24 Aug 18 04:35:17 PM PDT 24 985341300 ps
T383 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.4222332512 Aug 18 04:35:31 PM PDT 24 Aug 18 04:35:33 PM PDT 24 2703879605 ps
T384 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.1338152882 Aug 18 04:35:11 PM PDT 24 Aug 18 04:35:12 PM PDT 24 67785885 ps
T385 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.2556794454 Aug 18 04:35:12 PM PDT 24 Aug 18 04:35:16 PM PDT 24 5973565216 ps
T386 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.4250959319 Aug 18 04:35:13 PM PDT 24 Aug 18 04:35:16 PM PDT 24 2766458073 ps
T90 /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.3390564381 Aug 18 04:35:03 PM PDT 24 Aug 18 04:36:19 PM PDT 24 4759300289 ps
T387 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2244031454 Aug 18 04:35:10 PM PDT 24 Aug 18 04:35:16 PM PDT 24 5022256271 ps
T388 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.234889871 Aug 18 04:35:22 PM PDT 24 Aug 18 04:35:29 PM PDT 24 347125844 ps
T389 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2119091030 Aug 18 04:35:03 PM PDT 24 Aug 18 04:35:05 PM PDT 24 60194707 ps
T137 /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.1077342660 Aug 18 04:35:31 PM PDT 24 Aug 18 04:35:38 PM PDT 24 1604477301 ps
T390 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.1178898132 Aug 18 04:35:29 PM PDT 24 Aug 18 04:35:32 PM PDT 24 295153952 ps
T121 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.3010323240 Aug 18 04:35:22 PM PDT 24 Aug 18 04:35:30 PM PDT 24 898447082 ps
T391 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.3946118119 Aug 18 04:35:36 PM PDT 24 Aug 18 04:35:45 PM PDT 24 1216184544 ps
T392 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1178151111 Aug 18 04:35:00 PM PDT 24 Aug 18 04:35:17 PM PDT 24 25929093816 ps
T393 /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.2098548238 Aug 18 04:35:21 PM PDT 24 Aug 18 04:35:24 PM PDT 24 123959663 ps
T394 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.197742890 Aug 18 04:35:10 PM PDT 24 Aug 18 04:35:12 PM PDT 24 380808881 ps
T395 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1444533401 Aug 18 04:35:04 PM PDT 24 Aug 18 04:35:06 PM PDT 24 2099396498 ps
T396 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.3506275606 Aug 18 04:35:12 PM PDT 24 Aug 18 04:37:42 PM PDT 24 53178109724 ps
T397 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.692814753 Aug 18 04:35:11 PM PDT 24 Aug 18 04:35:15 PM PDT 24 309638963 ps
T398 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.574768382 Aug 18 04:35:06 PM PDT 24 Aug 18 04:35:14 PM PDT 24 5254301025 ps
T399 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.2288068817 Aug 18 04:35:33 PM PDT 24 Aug 18 04:35:35 PM PDT 24 1149443757 ps
T400 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.335756728 Aug 18 04:34:55 PM PDT 24 Aug 18 04:34:56 PM PDT 24 39002199 ps
T401 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.276363966 Aug 18 04:35:30 PM PDT 24 Aug 18 04:35:35 PM PDT 24 5948874642 ps
T402 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.3970415583 Aug 18 04:35:07 PM PDT 24 Aug 18 04:35:15 PM PDT 24 408099377 ps
T122 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.1453780507 Aug 18 04:35:22 PM PDT 24 Aug 18 04:35:31 PM PDT 24 1115254944 ps
T180 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.2227145986 Aug 18 04:35:22 PM PDT 24 Aug 18 04:35:31 PM PDT 24 1235117508 ps
T403 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.3451294159 Aug 18 04:35:13 PM PDT 24 Aug 18 04:35:14 PM PDT 24 28184022 ps
T185 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.125209213 Aug 18 04:34:57 PM PDT 24 Aug 18 04:35:16 PM PDT 24 2337642311 ps
T131 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.688621095 Aug 18 04:35:31 PM PDT 24 Aug 18 04:35:33 PM PDT 24 119794760 ps
T404 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1499566065 Aug 18 04:34:57 PM PDT 24 Aug 18 04:34:58 PM PDT 24 30471403 ps
T182 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.103045009 Aug 18 04:35:12 PM PDT 24 Aug 18 04:35:29 PM PDT 24 2338299186 ps
T405 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.1884718725 Aug 18 04:35:31 PM PDT 24 Aug 18 04:35:47 PM PDT 24 7526611661 ps
T406 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.2699180331 Aug 18 04:35:32 PM PDT 24 Aug 18 04:35:46 PM PDT 24 14509271989 ps
T407 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.4100216934 Aug 18 04:35:31 PM PDT 24 Aug 18 04:35:53 PM PDT 24 27987991807 ps
T408 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.804669396 Aug 18 04:35:02 PM PDT 24 Aug 18 04:35:54 PM PDT 24 36768162568 ps
T409 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.2411447802 Aug 18 04:35:32 PM PDT 24 Aug 18 04:35:43 PM PDT 24 764507033 ps
T113 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.4172449951 Aug 18 04:35:11 PM PDT 24 Aug 18 04:35:18 PM PDT 24 2440376737 ps
T410 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.3017805805 Aug 18 04:34:59 PM PDT 24 Aug 18 04:35:27 PM PDT 24 2872975964 ps
T411 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.1758717370 Aug 18 04:35:23 PM PDT 24 Aug 18 04:35:27 PM PDT 24 192874458 ps
T132 /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.3877078759 Aug 18 04:35:05 PM PDT 24 Aug 18 04:35:07 PM PDT 24 207345329 ps
T412 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.4150964951 Aug 18 04:35:19 PM PDT 24 Aug 18 04:35:20 PM PDT 24 178362164 ps
T413 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.221119280 Aug 18 04:35:29 PM PDT 24 Aug 18 04:35:34 PM PDT 24 327078072 ps
T414 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.2052192398 Aug 18 04:35:26 PM PDT 24 Aug 18 04:35:29 PM PDT 24 81276549 ps
T415 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.1493322013 Aug 18 04:35:12 PM PDT 24 Aug 18 04:35:13 PM PDT 24 37695870 ps
T416 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.1102785219 Aug 18 04:35:20 PM PDT 24 Aug 18 04:35:24 PM PDT 24 214657931 ps
T417 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.3196832879 Aug 18 04:35:21 PM PDT 24 Aug 18 04:35:24 PM PDT 24 5925747793 ps
T418 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.4185866184 Aug 18 04:35:24 PM PDT 24 Aug 18 04:35:26 PM PDT 24 230614410 ps
T133 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.2534208530 Aug 18 04:35:14 PM PDT 24 Aug 18 04:35:16 PM PDT 24 122367091 ps
T419 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1498738343 Aug 18 04:34:56 PM PDT 24 Aug 18 04:34:58 PM PDT 24 108159913 ps
T420 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.1882474037 Aug 18 04:35:13 PM PDT 24 Aug 18 04:35:23 PM PDT 24 24983917255 ps
T421 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.3424364144 Aug 18 04:34:56 PM PDT 24 Aug 18 04:34:58 PM PDT 24 229554702 ps
T422 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1001127590 Aug 18 04:35:26 PM PDT 24 Aug 18 04:35:30 PM PDT 24 184492669 ps
T423 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.2059187220 Aug 18 04:35:12 PM PDT 24 Aug 18 04:35:13 PM PDT 24 58902870 ps
T424 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.1461627449 Aug 18 04:35:02 PM PDT 24 Aug 18 04:35:04 PM PDT 24 542808925 ps
T425 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.3327964005 Aug 18 04:35:21 PM PDT 24 Aug 18 04:37:37 PM PDT 24 99280321879 ps
T426 /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.129553014 Aug 18 04:34:56 PM PDT 24 Aug 18 04:36:59 PM PDT 24 9346511349 ps
T427 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.964687175 Aug 18 04:35:31 PM PDT 24 Aug 18 04:35:38 PM PDT 24 4876478704 ps
T183 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.4228616521 Aug 18 04:35:12 PM PDT 24 Aug 18 04:35:32 PM PDT 24 2730570355 ps
T428 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.2450674364 Aug 18 04:35:26 PM PDT 24 Aug 18 04:35:31 PM PDT 24 259931336 ps
T429 /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.1304651656 Aug 18 04:35:21 PM PDT 24 Aug 18 04:35:23 PM PDT 24 81808074 ps
T430 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.730070227 Aug 18 04:35:21 PM PDT 24 Aug 18 04:35:24 PM PDT 24 1163612429 ps
T431 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.3828341426 Aug 18 04:35:30 PM PDT 24 Aug 18 04:35:40 PM PDT 24 20509253855 ps
T432 /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.1612908341 Aug 18 04:35:22 PM PDT 24 Aug 18 04:35:24 PM PDT 24 119522917 ps
T433 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.643322484 Aug 18 04:35:13 PM PDT 24 Aug 18 04:35:49 PM PDT 24 2540853674 ps
T434 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3728297398 Aug 18 04:34:57 PM PDT 24 Aug 18 04:34:58 PM PDT 24 139700597 ps
T435 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.2378333012 Aug 18 04:35:19 PM PDT 24 Aug 18 04:35:21 PM PDT 24 43499555 ps
T436 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.228165511 Aug 18 04:35:10 PM PDT 24 Aug 18 04:35:18 PM PDT 24 898958607 ps
T123 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.808281886 Aug 18 04:35:28 PM PDT 24 Aug 18 04:35:35 PM PDT 24 438018027 ps
T437 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.380253726 Aug 18 04:35:31 PM PDT 24 Aug 18 04:35:35 PM PDT 24 213890327 ps
T438 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.1927850594 Aug 18 04:35:20 PM PDT 24 Aug 18 04:35:23 PM PDT 24 5909507201 ps
T439 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.3340726845 Aug 18 04:35:22 PM PDT 24 Aug 18 04:35:47 PM PDT 24 5738070454 ps
T440 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3906080301 Aug 18 04:35:04 PM PDT 24 Aug 18 04:35:06 PM PDT 24 443086453 ps
T441 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.2984278631 Aug 18 04:35:06 PM PDT 24 Aug 18 04:35:07 PM PDT 24 193370366 ps
T442 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.629537405 Aug 18 04:35:35 PM PDT 24 Aug 18 04:35:38 PM PDT 24 495639181 ps
T443 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.730680800 Aug 18 04:34:57 PM PDT 24 Aug 18 04:35:22 PM PDT 24 61497767429 ps
T444 /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.845317692 Aug 18 04:35:36 PM PDT 24 Aug 18 04:35:37 PM PDT 24 149681134 ps
T445 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.1012773820 Aug 18 04:35:12 PM PDT 24 Aug 18 04:35:23 PM PDT 24 3956414542 ps
T446 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.3153384486 Aug 18 04:35:31 PM PDT 24 Aug 18 04:35:34 PM PDT 24 105484961 ps
T447 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.3730414766 Aug 18 04:35:22 PM PDT 24 Aug 18 04:35:23 PM PDT 24 133768095 ps
T448 /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.1728423901 Aug 18 04:35:15 PM PDT 24 Aug 18 04:35:17 PM PDT 24 246275739 ps
T449 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.4201989599 Aug 18 04:35:12 PM PDT 24 Aug 18 04:35:22 PM PDT 24 8281567340 ps
T450 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.1830257584 Aug 18 04:35:12 PM PDT 24 Aug 18 04:35:14 PM PDT 24 150902234 ps
T451 /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.1298671563 Aug 18 04:35:19 PM PDT 24 Aug 18 04:35:48 PM PDT 24 3687074339 ps
T452 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.4260657727 Aug 18 04:35:31 PM PDT 24 Aug 18 04:35:55 PM PDT 24 2935806582 ps
T453 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2695819490 Aug 18 04:35:31 PM PDT 24 Aug 18 04:35:33 PM PDT 24 511685556 ps
T184 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.3049933267 Aug 18 04:35:05 PM PDT 24 Aug 18 04:35:16 PM PDT 24 2082735772 ps
T454 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.3328060129 Aug 18 04:35:29 PM PDT 24 Aug 18 04:35:39 PM PDT 24 2121300668 ps
T455 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.163571316 Aug 18 04:35:28 PM PDT 24 Aug 18 04:35:30 PM PDT 24 172795447 ps
T456 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.2384858465 Aug 18 04:35:20 PM PDT 24 Aug 18 04:35:30 PM PDT 24 2973349620 ps
T457 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.3177685649 Aug 18 04:35:03 PM PDT 24 Aug 18 04:35:34 PM PDT 24 3476494130 ps
T458 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.652577962 Aug 18 04:35:34 PM PDT 24 Aug 18 04:35:35 PM PDT 24 331530072 ps
T459 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.942145001 Aug 18 04:35:26 PM PDT 24 Aug 18 04:35:28 PM PDT 24 101835433 ps
T460 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.1260419621 Aug 18 04:35:35 PM PDT 24 Aug 18 04:35:37 PM PDT 24 550837719 ps
T461 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.3674747033 Aug 18 04:35:38 PM PDT 24 Aug 18 04:35:40 PM PDT 24 65736897 ps
T462 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.2386343891 Aug 18 04:35:31 PM PDT 24 Aug 18 04:35:32 PM PDT 24 260047732 ps
T463 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.3737390443 Aug 18 04:34:54 PM PDT 24 Aug 18 04:34:56 PM PDT 24 446502367 ps
T464 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.2450301698 Aug 18 04:35:12 PM PDT 24 Aug 18 04:35:19 PM PDT 24 8359178898 ps
T465 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.2523109769 Aug 18 04:34:56 PM PDT 24 Aug 18 04:34:59 PM PDT 24 179117149 ps
T466 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.3216186020 Aug 18 04:35:20 PM PDT 24 Aug 18 04:36:04 PM PDT 24 14772522862 ps
T467 /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3343828643 Aug 18 04:35:06 PM PDT 24 Aug 18 04:35:10 PM PDT 24 244928335 ps
T468 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.663040548 Aug 18 04:34:57 PM PDT 24 Aug 18 04:34:58 PM PDT 24 295605834 ps
T469 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.2857618524 Aug 18 04:35:27 PM PDT 24 Aug 18 04:35:28 PM PDT 24 96307948 ps
T470 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.1885035252 Aug 18 04:35:21 PM PDT 24 Aug 18 04:35:23 PM PDT 24 172360518 ps
T471 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.2675763086 Aug 18 04:35:21 PM PDT 24 Aug 18 04:35:26 PM PDT 24 2813468375 ps
T472 /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.2030661291 Aug 18 04:35:24 PM PDT 24 Aug 18 04:35:28 PM PDT 24 954202575 ps
T114 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.1495176919 Aug 18 04:35:05 PM PDT 24 Aug 18 04:35:14 PM PDT 24 11645939555 ps
T124 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.1888485788 Aug 18 04:35:13 PM PDT 24 Aug 18 04:35:16 PM PDT 24 922897707 ps
T130 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.2423744922 Aug 18 04:34:56 PM PDT 24 Aug 18 04:34:58 PM PDT 24 664966709 ps
T473 /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.1744796187 Aug 18 04:35:34 PM PDT 24 Aug 18 04:35:43 PM PDT 24 694748473 ps
T474 /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.3834664847 Aug 18 04:35:29 PM PDT 24 Aug 18 04:35:32 PM PDT 24 516503409 ps
T475 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.2539003377 Aug 18 04:35:27 PM PDT 24 Aug 18 04:35:32 PM PDT 24 119669100 ps
T476 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2326376843 Aug 18 04:35:24 PM PDT 24 Aug 18 04:35:27 PM PDT 24 2880543288 ps
T477 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.2619060402 Aug 18 04:35:07 PM PDT 24 Aug 18 04:35:08 PM PDT 24 951175216 ps
T478 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.3879736438 Aug 18 04:34:59 PM PDT 24 Aug 18 04:35:00 PM PDT 24 454825595 ps
T479 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3124012312 Aug 18 04:35:34 PM PDT 24 Aug 18 04:35:36 PM PDT 24 2516514026 ps
T125 /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.3438397627 Aug 18 04:34:57 PM PDT 24 Aug 18 04:35:00 PM PDT 24 394700357 ps
T480 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2472549119 Aug 18 04:35:12 PM PDT 24 Aug 18 04:35:14 PM PDT 24 404442841 ps
T481 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.608978278 Aug 18 04:35:25 PM PDT 24 Aug 18 04:35:34 PM PDT 24 698398546 ps
T482 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.2288857138 Aug 18 04:35:22 PM PDT 24 Aug 18 04:35:24 PM PDT 24 196277918 ps
T483 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.2060272237 Aug 18 04:35:19 PM PDT 24 Aug 18 04:35:20 PM PDT 24 215173621 ps

Test location /workspace/coverage/default/32.rv_dm_stress_all.1861462427
Short name T4
Test name
Test status
Simulation time 4364777407 ps
CPU time 12.47 seconds
Started Aug 18 04:39:45 PM PDT 24
Finished Aug 18 04:39:57 PM PDT 24
Peak memory 205180 kb
Host smart-4c6150c1-4ae6-4ee2-a428-8c6aaf3e59f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861462427 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.1861462427
Directory /workspace/32.rv_dm_stress_all/latest

Test location /workspace/coverage/default/6.rv_dm_stress_all_with_rand_reset.3932347860
Short name T13
Test name
Test status
Simulation time 15308444830 ps
CPU time 87.04 seconds
Started Aug 18 04:39:22 PM PDT 24
Finished Aug 18 04:40:50 PM PDT 24
Peak memory 216068 kb
Host smart-f8b9da2c-0cca-4ce8-bdb7-db1b0e877271
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932347860 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all_with_rand_reset.3932347860
Directory /workspace/6.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.547404156
Short name T65
Test name
Test status
Simulation time 4042352351 ps
CPU time 3.91 seconds
Started Aug 18 04:39:41 PM PDT 24
Finished Aug 18 04:39:45 PM PDT 24
Peak memory 213572 kb
Host smart-162a463e-742e-46e7-9699-b619d9baa954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547404156 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.547404156
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_stress_all_with_rand_reset.3146672403
Short name T19
Test name
Test status
Simulation time 17968434151 ps
CPU time 71.57 seconds
Started Aug 18 04:39:31 PM PDT 24
Finished Aug 18 04:40:42 PM PDT 24
Peak memory 229848 kb
Host smart-daf5af03-b7d7-45cb-8592-050128b851ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146672403 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all_with_rand_reset.3146672403
Directory /workspace/9.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.581838681
Short name T150
Test name
Test status
Simulation time 2540269477 ps
CPU time 21.81 seconds
Started Aug 18 04:35:23 PM PDT 24
Finished Aug 18 04:35:45 PM PDT 24
Peak memory 214080 kb
Host smart-06e1c91f-5c8f-4363-9838-be84c5ce7e7e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581838681 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.581838681
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.4162995481
Short name T86
Test name
Test status
Simulation time 2646342728 ps
CPU time 44.73 seconds
Started Aug 18 04:35:12 PM PDT 24
Finished Aug 18 04:35:57 PM PDT 24
Peak memory 213760 kb
Host smart-92d2ad5b-bb95-43e5-a244-df800d8a101e
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162995481 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.4162995481
Directory /workspace/5.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.3323433837
Short name T26
Test name
Test status
Simulation time 93378669622 ps
CPU time 163.58 seconds
Started Aug 18 04:39:33 PM PDT 24
Finished Aug 18 04:42:17 PM PDT 24
Peak memory 205128 kb
Host smart-539f08e7-a248-4189-bca9-9b25c8884e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323433837 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.3323433837
Directory /workspace/8.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.958140383
Short name T78
Test name
Test status
Simulation time 8010619572 ps
CPU time 4.06 seconds
Started Aug 18 04:38:50 PM PDT 24
Finished Aug 18 04:38:54 PM PDT 24
Peak memory 205112 kb
Host smart-14b4b0c0-8490-4ac7-95de-46516e02c378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958140383 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.958140383
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/2.rv_dm_buffered_enable.1561743366
Short name T27
Test name
Test status
Simulation time 155614303 ps
CPU time 1.12 seconds
Started Aug 18 04:39:06 PM PDT 24
Finished Aug 18 04:39:07 PM PDT 24
Peak memory 226136 kb
Host smart-ed0be8a6-8f43-46f8-b18f-bdba069c47bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561743366 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_buffered_enable.1561743366
Directory /workspace/2.rv_dm_buffered_enable/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.1386674755
Short name T55
Test name
Test status
Simulation time 11101109940 ps
CPU time 89.93 seconds
Started Aug 18 04:35:23 PM PDT 24
Finished Aug 18 04:36:53 PM PDT 24
Peak memory 219044 kb
Host smart-f2be8321-1916-42f7-a051-4ee1fe34062d
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386674755 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.1386674755
Directory /workspace/7.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/0.rv_dm_scanmode.3716818949
Short name T79
Test name
Test status
Simulation time 34777170 ps
CPU time 0.66 seconds
Started Aug 18 04:39:02 PM PDT 24
Finished Aug 18 04:39:03 PM PDT 24
Peak memory 204956 kb
Host smart-a8f9d04e-5525-48e5-91e0-5754bdb6ede8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716818949 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_scanmode_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_scanmode.3716818949
Directory /workspace/0.rv_dm_scanmode/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.525316781
Short name T34
Test name
Test status
Simulation time 1381743953 ps
CPU time 2.89 seconds
Started Aug 18 04:38:58 PM PDT 24
Finished Aug 18 04:39:01 PM PDT 24
Peak memory 229312 kb
Host smart-8cdfe6ac-b664-4033-a34f-076a674b91d5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525316781 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.525316781
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.3210277604
Short name T7
Test name
Test status
Simulation time 149713350 ps
CPU time 0.92 seconds
Started Aug 18 04:39:03 PM PDT 24
Finished Aug 18 04:39:04 PM PDT 24
Peak memory 204908 kb
Host smart-00546823-6850-48ec-acf8-a903019dfe40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210277604 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.3210277604
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.4018575538
Short name T104
Test name
Test status
Simulation time 1027176534 ps
CPU time 4.34 seconds
Started Aug 18 04:35:36 PM PDT 24
Finished Aug 18 04:35:40 PM PDT 24
Peak memory 205540 kb
Host smart-0df4f7bf-d455-4e91-addd-09d3de3afee6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018575538 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.4018575538
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.785484077
Short name T91
Test name
Test status
Simulation time 84050036 ps
CPU time 2.82 seconds
Started Aug 18 04:35:21 PM PDT 24
Finished Aug 18 04:35:24 PM PDT 24
Peak memory 217792 kb
Host smart-a0d19346-4353-41cb-8202-f0be1ba241f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785484077 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.785484077
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/46.rv_dm_stress_all.496562487
Short name T53
Test name
Test status
Simulation time 4095695000 ps
CPU time 2.72 seconds
Started Aug 18 04:39:51 PM PDT 24
Finished Aug 18 04:39:53 PM PDT 24
Peak memory 205288 kb
Host smart-0ef83939-9e0f-4790-862b-8308134c42a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496562487 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.496562487
Directory /workspace/46.rv_dm_stress_all/latest

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.388477353
Short name T171
Test name
Test status
Simulation time 17855976837 ps
CPU time 20.13 seconds
Started Aug 18 04:39:33 PM PDT 24
Finished Aug 18 04:39:53 PM PDT 24
Peak memory 213496 kb
Host smart-be75e027-bf89-45d0-bcea-f2cba98c3b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388477353 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.388477353
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.2503178370
Short name T107
Test name
Test status
Simulation time 214886854 ps
CPU time 2.35 seconds
Started Aug 18 04:35:20 PM PDT 24
Finished Aug 18 04:35:22 PM PDT 24
Peak memory 219400 kb
Host smart-bf42ca77-9955-49b9-bab3-ce5221849907
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503178370 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.2503178370
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.2904633038
Short name T40
Test name
Test status
Simulation time 72543695 ps
CPU time 0.77 seconds
Started Aug 18 04:38:59 PM PDT 24
Finished Aug 18 04:39:00 PM PDT 24
Peak memory 213168 kb
Host smart-e56efb30-03e0-457a-993f-927bacd50cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904633038 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.2904633038
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.794600903
Short name T155
Test name
Test status
Simulation time 8177148384 ps
CPU time 17.5 seconds
Started Aug 18 04:39:43 PM PDT 24
Finished Aug 18 04:40:01 PM PDT 24
Peak memory 213644 kb
Host smart-ee13e40f-e148-4a81-94cb-9f1d637f523e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794600903 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.794600903
Directory /workspace/13.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.2782537019
Short name T205
Test name
Test status
Simulation time 32184744 ps
CPU time 0.79 seconds
Started Aug 18 04:39:39 PM PDT 24
Finished Aug 18 04:39:40 PM PDT 24
Peak memory 205012 kb
Host smart-8fbd53f0-ece1-4056-99ac-5b1c7b66335c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782537019 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.2782537019
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.4228616521
Short name T183
Test name
Test status
Simulation time 2730570355 ps
CPU time 20.12 seconds
Started Aug 18 04:35:12 PM PDT 24
Finished Aug 18 04:35:32 PM PDT 24
Peak memory 213756 kb
Host smart-c2cdc6fd-1a26-4213-a9da-97b0cb54adbd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228616521 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.4228616521
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_stress_all.3444940288
Short name T48
Test name
Test status
Simulation time 2802216684 ps
CPU time 5.15 seconds
Started Aug 18 04:38:57 PM PDT 24
Finished Aug 18 04:39:03 PM PDT 24
Peak memory 205228 kb
Host smart-cf5fdca3-5fb6-4020-870d-426c7f10c6f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444940288 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.3444940288
Directory /workspace/0.rv_dm_stress_all/latest

Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.2381414543
Short name T174
Test name
Test status
Simulation time 1330048850 ps
CPU time 4.14 seconds
Started Aug 18 04:39:24 PM PDT 24
Finished Aug 18 04:39:28 PM PDT 24
Peak memory 213756 kb
Host smart-584a3d1e-e362-4bd2-83d3-24f3993599c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381414543 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.2381414543
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/38.rv_dm_stress_all.2927173870
Short name T161
Test name
Test status
Simulation time 3907205022 ps
CPU time 3.65 seconds
Started Aug 18 04:39:47 PM PDT 24
Finished Aug 18 04:39:51 PM PDT 24
Peak memory 205232 kb
Host smart-306a4873-4357-47d4-bf69-d587fafbee0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927173870 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.2927173870
Directory /workspace/38.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_sba_debug_disabled.2414476070
Short name T77
Test name
Test status
Simulation time 3626848177 ps
CPU time 5.62 seconds
Started Aug 18 04:39:06 PM PDT 24
Finished Aug 18 04:39:12 PM PDT 24
Peak memory 205168 kb
Host smart-9ba7e916-4871-4e62-919b-a579b8793d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414476070 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.2414476070
Directory /workspace/0.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3846361258
Short name T179
Test name
Test status
Simulation time 1148603635 ps
CPU time 11.73 seconds
Started Aug 18 04:35:26 PM PDT 24
Finished Aug 18 04:35:38 PM PDT 24
Peak memory 221740 kb
Host smart-101cb00d-f792-4007-991c-5ee4e1fd55ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846361258 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.3
846361258
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/14.rv_dm_stress_all.3183421192
Short name T157
Test name
Test status
Simulation time 3052350732 ps
CPU time 10.09 seconds
Started Aug 18 04:39:40 PM PDT 24
Finished Aug 18 04:39:50 PM PDT 24
Peak memory 205208 kb
Host smart-d81c3a14-805a-49f4-af58-a924aed6bf15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183421192 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.3183421192
Directory /workspace/14.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.47982419
Short name T341
Test name
Test status
Simulation time 8481714374 ps
CPU time 14.01 seconds
Started Aug 18 04:34:55 PM PDT 24
Finished Aug 18 04:35:09 PM PDT 24
Peak memory 205412 kb
Host smart-9b9e0e8e-fce2-42fb-a2e3-26d499edad4e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47982419 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_
bit_bash.47982419
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2672910484
Short name T111
Test name
Test status
Simulation time 6797268717 ps
CPU time 6.79 seconds
Started Aug 18 04:34:54 PM PDT 24
Finished Aug 18 04:35:01 PM PDT 24
Peak memory 205536 kb
Host smart-a68ab87f-b671-4d01-9399-02b2a644ebc4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672910484 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_hw_reset.2672910484
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.1867316169
Short name T37
Test name
Test status
Simulation time 461588291 ps
CPU time 0.96 seconds
Started Aug 18 04:38:58 PM PDT 24
Finished Aug 18 04:38:59 PM PDT 24
Peak memory 205012 kb
Host smart-4097ed36-788f-4e5c-8a7d-099cfc97df8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867316169 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.1867316169
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3364051618
Short name T141
Test name
Test status
Simulation time 5619763669 ps
CPU time 22.97 seconds
Started Aug 18 04:35:34 PM PDT 24
Finished Aug 18 04:35:57 PM PDT 24
Peak memory 221804 kb
Host smart-1ea776e7-9a89-462c-b1f6-f7a45a34bff7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364051618 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.3
364051618
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.3049933267
Short name T184
Test name
Test status
Simulation time 2082735772 ps
CPU time 9.9 seconds
Started Aug 18 04:35:05 PM PDT 24
Finished Aug 18 04:35:16 PM PDT 24
Peak memory 213668 kb
Host smart-adb24072-3fc6-4375-9084-0e7389878c6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049933267 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.3049933267
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.3704413897
Short name T273
Test name
Test status
Simulation time 595714671 ps
CPU time 1.12 seconds
Started Aug 18 04:39:05 PM PDT 24
Finished Aug 18 04:39:06 PM PDT 24
Peak memory 204868 kb
Host smart-13ffdeff-b23d-49a3-b9ed-947d794c68c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704413897 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.3704413897
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/18.rv_dm_stress_all.2509084999
Short name T162
Test name
Test status
Simulation time 4721144143 ps
CPU time 12.48 seconds
Started Aug 18 04:39:42 PM PDT 24
Finished Aug 18 04:39:55 PM PDT 24
Peak memory 205248 kb
Host smart-c53a8e0f-b61e-4183-924c-939c03daa476
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509084999 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.2509084999
Directory /workspace/18.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_sparse_lc_gate_fsm.630540358
Short name T56
Test name
Test status
Simulation time 210839991 ps
CPU time 0.92 seconds
Started Aug 18 04:38:59 PM PDT 24
Finished Aug 18 04:39:00 PM PDT 24
Peak memory 213276 kb
Host smart-4597c85e-4ce0-4060-9a48-a19df858b077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630540358 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sparse_lc_gate_fsm.630540358
Directory /workspace/0.rv_dm_sparse_lc_gate_fsm/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3917300734
Short name T108
Test name
Test status
Simulation time 2107942455 ps
CPU time 31.44 seconds
Started Aug 18 04:34:56 PM PDT 24
Finished Aug 18 04:35:28 PM PDT 24
Peak memory 205520 kb
Host smart-846d9330-cedf-4433-9be1-7ef22ced9a9e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917300734 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.3917300734
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.3017805805
Short name T410
Test name
Test status
Simulation time 2872975964 ps
CPU time 27.84 seconds
Started Aug 18 04:34:59 PM PDT 24
Finished Aug 18 04:35:27 PM PDT 24
Peak memory 205620 kb
Host smart-cb047c6e-328c-4e49-8c93-9ff78a4ad7d2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017805805 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.3017805805
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.2423744922
Short name T130
Test name
Test status
Simulation time 664966709 ps
CPU time 2.48 seconds
Started Aug 18 04:34:56 PM PDT 24
Finished Aug 18 04:34:58 PM PDT 24
Peak memory 213600 kb
Host smart-b121af14-d854-48aa-a092-e88f7b4472cb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423744922 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.2423744922
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1498738343
Short name T419
Test name
Test status
Simulation time 108159913 ps
CPU time 2.28 seconds
Started Aug 18 04:34:56 PM PDT 24
Finished Aug 18 04:34:58 PM PDT 24
Peak memory 213744 kb
Host smart-2d92ed62-b0fb-459b-af96-59e94e655fd1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498738343 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.1498738343
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.3424364144
Short name T421
Test name
Test status
Simulation time 229554702 ps
CPU time 1.69 seconds
Started Aug 18 04:34:56 PM PDT 24
Finished Aug 18 04:34:58 PM PDT 24
Peak memory 213684 kb
Host smart-3542a864-a31d-46a2-995f-b37013b9d825
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424364144 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.3424364144
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.730680800
Short name T443
Test name
Test status
Simulation time 61497767429 ps
CPU time 24.62 seconds
Started Aug 18 04:34:57 PM PDT 24
Finished Aug 18 04:35:22 PM PDT 24
Peak memory 205544 kb
Host smart-0c6a11bd-474c-487f-8e68-1491a38f036e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730680800 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr
_aliasing.730680800
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1178151111
Short name T392
Test name
Test status
Simulation time 25929093816 ps
CPU time 16.51 seconds
Started Aug 18 04:35:00 PM PDT 24
Finished Aug 18 04:35:17 PM PDT 24
Peak memory 205384 kb
Host smart-f21db58b-c237-4a27-9799-8a5486094c7e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178151111 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
rv_dm_jtag_dmi_csr_bit_bash.1178151111
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3106483979
Short name T348
Test name
Test status
Simulation time 1081119168 ps
CPU time 3.21 seconds
Started Aug 18 04:35:00 PM PDT 24
Finished Aug 18 04:35:03 PM PDT 24
Peak memory 205272 kb
Host smart-dcf8c5fe-1e22-41c0-b38f-4e42438d76ef
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106483979 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.3
106483979
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.3737390443
Short name T463
Test name
Test status
Simulation time 446502367 ps
CPU time 1.01 seconds
Started Aug 18 04:34:54 PM PDT 24
Finished Aug 18 04:34:56 PM PDT 24
Peak memory 205132 kb
Host smart-fd11c022-55f1-4162-937b-3f526e4e8c7b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737390443 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.3737390443
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3728297398
Short name T434
Test name
Test status
Simulation time 139700597 ps
CPU time 0.96 seconds
Started Aug 18 04:34:57 PM PDT 24
Finished Aug 18 04:34:58 PM PDT 24
Peak memory 205136 kb
Host smart-0fef634a-0761-4c0b-88a3-bc5832246236
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728297398 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.3728297398
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.2353261814
Short name T94
Test name
Test status
Simulation time 200624917 ps
CPU time 1.21 seconds
Started Aug 18 04:34:55 PM PDT 24
Finished Aug 18 04:34:56 PM PDT 24
Peak memory 205260 kb
Host smart-b0e903f5-df89-489a-9692-e65f3ea0aa41
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353261814 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.2
353261814
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1499566065
Short name T404
Test name
Test status
Simulation time 30471403 ps
CPU time 0.75 seconds
Started Aug 18 04:34:57 PM PDT 24
Finished Aug 18 04:34:58 PM PDT 24
Peak memory 205020 kb
Host smart-a4f4921e-5840-43c7-8e5b-320087a1fb69
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499566065 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.1499566065
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.335756728
Short name T400
Test name
Test status
Simulation time 39002199 ps
CPU time 0.69 seconds
Started Aug 18 04:34:55 PM PDT 24
Finished Aug 18 04:34:56 PM PDT 24
Peak memory 205076 kb
Host smart-807998f7-f184-4a9e-82f2-598d38dfe2a3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335756728 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.335756728
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.3438397627
Short name T125
Test name
Test status
Simulation time 394700357 ps
CPU time 3.57 seconds
Started Aug 18 04:34:57 PM PDT 24
Finished Aug 18 04:35:00 PM PDT 24
Peak memory 205548 kb
Host smart-946f8458-a8fd-4888-92e7-837c85b1b108
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438397627 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.3438397627
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.129553014
Short name T426
Test name
Test status
Simulation time 9346511349 ps
CPU time 123.45 seconds
Started Aug 18 04:34:56 PM PDT 24
Finished Aug 18 04:36:59 PM PDT 24
Peak memory 218964 kb
Host smart-165b0176-913c-4725-811a-fc02ea03518c
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129553014 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.129553014
Directory /workspace/0.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.2523109769
Short name T465
Test name
Test status
Simulation time 179117149 ps
CPU time 2.6 seconds
Started Aug 18 04:34:56 PM PDT 24
Finished Aug 18 04:34:59 PM PDT 24
Peak memory 213568 kb
Host smart-68ea667f-e6e0-445f-9330-4014a7372a3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523109769 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.2523109769
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.125209213
Short name T185
Test name
Test status
Simulation time 2337642311 ps
CPU time 19.01 seconds
Started Aug 18 04:34:57 PM PDT 24
Finished Aug 18 04:35:16 PM PDT 24
Peak memory 219864 kb
Host smart-3807cf4b-f58f-4625-9ec8-1419a24279f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125209213 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.125209213
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.4006432120
Short name T127
Test name
Test status
Simulation time 17220540817 ps
CPU time 32.31 seconds
Started Aug 18 04:34:56 PM PDT 24
Finished Aug 18 04:35:29 PM PDT 24
Peak memory 205436 kb
Host smart-f03c4270-86c2-41d2-8e5e-6302e286d184
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006432120 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.4006432120
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.703266943
Short name T102
Test name
Test status
Simulation time 14129364924 ps
CPU time 38.41 seconds
Started Aug 18 04:35:03 PM PDT 24
Finished Aug 18 04:35:42 PM PDT 24
Peak memory 213708 kb
Host smart-68596cbe-c0ba-4b3d-90d6-cfc860cbd262
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703266943 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.703266943
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.3647946147
Short name T128
Test name
Test status
Simulation time 148741362 ps
CPU time 1.54 seconds
Started Aug 18 04:35:05 PM PDT 24
Finished Aug 18 04:35:07 PM PDT 24
Peak memory 213808 kb
Host smart-cc257a2b-bba3-4cc8-8e6e-ff648de0bcdc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647946147 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.3647946147
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.2471351807
Short name T378
Test name
Test status
Simulation time 178722062 ps
CPU time 2.08 seconds
Started Aug 18 04:35:05 PM PDT 24
Finished Aug 18 04:35:07 PM PDT 24
Peak memory 217564 kb
Host smart-62b5fd23-c8a3-482c-b246-f1e7d363adb7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471351807 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.2471351807
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.3877078759
Short name T132
Test name
Test status
Simulation time 207345329 ps
CPU time 1.52 seconds
Started Aug 18 04:35:05 PM PDT 24
Finished Aug 18 04:35:07 PM PDT 24
Peak memory 218816 kb
Host smart-de7d97f1-6674-4ac4-97dd-972b1806dcbd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877078759 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.3877078759
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1445825833
Short name T367
Test name
Test status
Simulation time 139936038588 ps
CPU time 355.64 seconds
Started Aug 18 04:35:02 PM PDT 24
Finished Aug 18 04:40:57 PM PDT 24
Peak memory 205376 kb
Host smart-c234a60d-e5fa-4012-9f5a-52c227295a4d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445825833 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_aliasing.1445825833
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.804669396
Short name T408
Test name
Test status
Simulation time 36768162568 ps
CPU time 51.66 seconds
Started Aug 18 04:35:02 PM PDT 24
Finished Aug 18 04:35:54 PM PDT 24
Peak memory 205336 kb
Host smart-1bca2b21-8ebe-4dc6-9832-a852985bd9b1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804669396 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.r
v_dm_jtag_dmi_csr_bit_bash.804669396
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.2242384727
Short name T112
Test name
Test status
Simulation time 17203477484 ps
CPU time 13.1 seconds
Started Aug 18 04:35:04 PM PDT 24
Finished Aug 18 04:35:17 PM PDT 24
Peak memory 205408 kb
Host smart-7bda3239-98d3-42c9-a873-f7490f4006d0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242384727 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.2242384727
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1444533401
Short name T395
Test name
Test status
Simulation time 2099396498 ps
CPU time 2.27 seconds
Started Aug 18 04:35:04 PM PDT 24
Finished Aug 18 04:35:06 PM PDT 24
Peak memory 205252 kb
Host smart-53838cbe-fd6a-4604-8085-28cb38227198
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444533401 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.1
444533401
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.3879736438
Short name T478
Test name
Test status
Simulation time 454825595 ps
CPU time 0.95 seconds
Started Aug 18 04:34:59 PM PDT 24
Finished Aug 18 04:35:00 PM PDT 24
Peak memory 205136 kb
Host smart-bf2b7b24-fe74-49ee-ba44-4ef1495223a3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879736438 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_aliasing.3879736438
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.1843047875
Short name T379
Test name
Test status
Simulation time 11785231290 ps
CPU time 22.29 seconds
Started Aug 18 04:34:57 PM PDT 24
Finished Aug 18 04:35:20 PM PDT 24
Peak memory 205420 kb
Host smart-b885eb45-7a1b-4902-b865-17d158f9379c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843047875 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_bit_bash.1843047875
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.583133166
Short name T93
Test name
Test status
Simulation time 420658130 ps
CPU time 0.75 seconds
Started Aug 18 04:35:00 PM PDT 24
Finished Aug 18 04:35:01 PM PDT 24
Peak memory 205140 kb
Host smart-bd629309-f87c-4dcf-8625-5cd9026fe303
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583133166 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr
_hw_reset.583133166
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.663040548
Short name T468
Test name
Test status
Simulation time 295605834 ps
CPU time 0.87 seconds
Started Aug 18 04:34:57 PM PDT 24
Finished Aug 18 04:34:58 PM PDT 24
Peak memory 205160 kb
Host smart-e5806642-09d8-4bf9-a562-936a0f134bac
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663040548 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.663040548
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.621093350
Short name T326
Test name
Test status
Simulation time 52083123 ps
CPU time 0.71 seconds
Started Aug 18 04:35:03 PM PDT 24
Finished Aug 18 04:35:04 PM PDT 24
Peak memory 205064 kb
Host smart-30fcdd01-c217-4bce-84b1-c4d3b384d3a6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621093350 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_part
ial_access.621093350
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.3583267076
Short name T358
Test name
Test status
Simulation time 36102485 ps
CPU time 0.71 seconds
Started Aug 18 04:35:04 PM PDT 24
Finished Aug 18 04:35:05 PM PDT 24
Peak memory 205168 kb
Host smart-20dc26f0-df15-4e7d-99b5-9e173b7865c6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583267076 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.3583267076
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.3970415583
Short name T402
Test name
Test status
Simulation time 408099377 ps
CPU time 7.54 seconds
Started Aug 18 04:35:07 PM PDT 24
Finished Aug 18 04:35:15 PM PDT 24
Peak memory 205524 kb
Host smart-7de502d9-9af5-4d37-92a5-dfed0da7c886
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970415583 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_
csr_outstanding.3970415583
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.3390564381
Short name T90
Test name
Test status
Simulation time 4759300289 ps
CPU time 75.53 seconds
Started Aug 18 04:35:03 PM PDT 24
Finished Aug 18 04:36:19 PM PDT 24
Peak memory 213880 kb
Host smart-7b98f31c-e6e7-4b38-b8e2-d1d7427b13c8
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390564381 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.3390564381
Directory /workspace/1.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.1000112657
Short name T373
Test name
Test status
Simulation time 413067409 ps
CPU time 5.31 seconds
Started Aug 18 04:35:08 PM PDT 24
Finished Aug 18 04:35:14 PM PDT 24
Peak memory 213580 kb
Host smart-f20daaae-c4da-413d-b160-b1af24c78a67
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000112657 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.1000112657
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.3149250939
Short name T149
Test name
Test status
Simulation time 5092562646 ps
CPU time 26.96 seconds
Started Aug 18 04:35:05 PM PDT 24
Finished Aug 18 04:35:32 PM PDT 24
Peak memory 221896 kb
Host smart-b2657f28-49e4-4141-8a62-0b92c16cc295
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149250939 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.3149250939
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.956591553
Short name T357
Test name
Test status
Simulation time 298679380 ps
CPU time 3.02 seconds
Started Aug 18 04:35:21 PM PDT 24
Finished Aug 18 04:35:25 PM PDT 24
Peak memory 217600 kb
Host smart-49dbfdaa-91a8-4c90-a30c-ca82870c3fbe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956591553 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.956591553
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.2060272237
Short name T483
Test name
Test status
Simulation time 215173621 ps
CPU time 1.62 seconds
Started Aug 18 04:35:19 PM PDT 24
Finished Aug 18 04:35:20 PM PDT 24
Peak memory 213460 kb
Host smart-46ba5725-11bf-4c3e-adb2-f6d62bc3b5aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060272237 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.2060272237
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.1927850594
Short name T438
Test name
Test status
Simulation time 5909507201 ps
CPU time 2.64 seconds
Started Aug 18 04:35:20 PM PDT 24
Finished Aug 18 04:35:23 PM PDT 24
Peak memory 205360 kb
Host smart-c429da8f-f9c0-4d61-8458-82e2c3bf7ef8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927850594 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.rv_dm_jtag_dmi_csr_bit_bash.1927850594
Directory /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.433420679
Short name T368
Test name
Test status
Simulation time 6469225394 ps
CPU time 5.41 seconds
Started Aug 18 04:35:23 PM PDT 24
Finished Aug 18 04:35:29 PM PDT 24
Peak memory 205428 kb
Host smart-74c1115a-cea3-44ae-b5df-3310e405430e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433420679 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.433420679
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.3730414766
Short name T447
Test name
Test status
Simulation time 133768095 ps
CPU time 0.82 seconds
Started Aug 18 04:35:22 PM PDT 24
Finished Aug 18 04:35:23 PM PDT 24
Peak memory 204796 kb
Host smart-f5ac094e-8cf3-44ee-b63b-340f9d622ca0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730414766 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
3730414766
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.3010323240
Short name T121
Test name
Test status
Simulation time 898447082 ps
CPU time 7.11 seconds
Started Aug 18 04:35:22 PM PDT 24
Finished Aug 18 04:35:30 PM PDT 24
Peak memory 205352 kb
Host smart-b98fdbcb-de7e-4f49-baab-1e317c0df025
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010323240 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same
_csr_outstanding.3010323240
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.1102785219
Short name T416
Test name
Test status
Simulation time 214657931 ps
CPU time 3.96 seconds
Started Aug 18 04:35:20 PM PDT 24
Finished Aug 18 04:35:24 PM PDT 24
Peak memory 213760 kb
Host smart-79607ce6-ca7e-4236-8dff-bea5482bfe80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102785219 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.1102785219
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.2227145986
Short name T180
Test name
Test status
Simulation time 1235117508 ps
CPU time 9.12 seconds
Started Aug 18 04:35:22 PM PDT 24
Finished Aug 18 04:35:31 PM PDT 24
Peak memory 213668 kb
Host smart-ef1e9757-e8a2-454a-92ab-014786cd5732
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227145986 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.2
227145986
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1001127590
Short name T422
Test name
Test status
Simulation time 184492669 ps
CPU time 3.1 seconds
Started Aug 18 04:35:26 PM PDT 24
Finished Aug 18 04:35:30 PM PDT 24
Peak memory 221600 kb
Host smart-9625394b-f944-4c1a-a57d-b0fc1261f7b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001127590 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.1001127590
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.4185866184
Short name T418
Test name
Test status
Simulation time 230614410 ps
CPU time 1.69 seconds
Started Aug 18 04:35:24 PM PDT 24
Finished Aug 18 04:35:26 PM PDT 24
Peak memory 219160 kb
Host smart-8e0d8691-6d35-40c8-8d53-eb4eba891d58
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185866184 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.4185866184
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.2413775548
Short name T342
Test name
Test status
Simulation time 9485286578 ps
CPU time 24.67 seconds
Started Aug 18 04:35:24 PM PDT 24
Finished Aug 18 04:35:49 PM PDT 24
Peak memory 205348 kb
Host smart-a07277f0-4bb6-402a-9c9f-c53ede1003f7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413775548 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.rv_dm_jtag_dmi_csr_bit_bash.2413775548
Directory /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.4109801933
Short name T331
Test name
Test status
Simulation time 5030367852 ps
CPU time 7.07 seconds
Started Aug 18 04:35:22 PM PDT 24
Finished Aug 18 04:35:29 PM PDT 24
Peak memory 205424 kb
Host smart-79118902-54a8-4640-9635-86480e0f59e5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109801933 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
4109801933
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.3383939400
Short name T376
Test name
Test status
Simulation time 674190447 ps
CPU time 2.33 seconds
Started Aug 18 04:35:19 PM PDT 24
Finished Aug 18 04:35:22 PM PDT 24
Peak memory 205164 kb
Host smart-d2ad43dd-7832-4cdc-8c30-cc480ee829e2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383939400 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.
3383939400
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.2865245728
Short name T115
Test name
Test status
Simulation time 806526368 ps
CPU time 8.31 seconds
Started Aug 18 04:35:21 PM PDT 24
Finished Aug 18 04:35:29 PM PDT 24
Peak memory 205484 kb
Host smart-90e4f4f7-fd31-4ff3-8121-52060017d18b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865245728 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same
_csr_outstanding.2865245728
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.2450674364
Short name T428
Test name
Test status
Simulation time 259931336 ps
CPU time 4.89 seconds
Started Aug 18 04:35:26 PM PDT 24
Finished Aug 18 04:35:31 PM PDT 24
Peak memory 213660 kb
Host smart-c2bcdc7a-3f03-4c96-bf80-f61eeab2f4b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450674364 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.2450674364
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.1612908341
Short name T432
Test name
Test status
Simulation time 119522917 ps
CPU time 1.87 seconds
Started Aug 18 04:35:22 PM PDT 24
Finished Aug 18 04:35:24 PM PDT 24
Peak memory 214900 kb
Host smart-ea876a2d-e335-479f-9c6c-eb1870e2f095
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612908341 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.1612908341
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.1304651656
Short name T429
Test name
Test status
Simulation time 81808074 ps
CPU time 2.16 seconds
Started Aug 18 04:35:21 PM PDT 24
Finished Aug 18 04:35:23 PM PDT 24
Peak memory 219000 kb
Host smart-3cea1a2a-27e8-42f8-9a8b-c78ee69f61fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304651656 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.1304651656
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.3216186020
Short name T466
Test name
Test status
Simulation time 14772522862 ps
CPU time 43.36 seconds
Started Aug 18 04:35:20 PM PDT 24
Finished Aug 18 04:36:04 PM PDT 24
Peak memory 205352 kb
Host smart-38525d28-3a3a-4620-9541-496191131332
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216186020 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.rv_dm_jtag_dmi_csr_bit_bash.3216186020
Directory /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.2675763086
Short name T471
Test name
Test status
Simulation time 2813468375 ps
CPU time 4.72 seconds
Started Aug 18 04:35:21 PM PDT 24
Finished Aug 18 04:35:26 PM PDT 24
Peak memory 205356 kb
Host smart-e6fe523b-89e9-4a71-899f-91e6f619ddb8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675763086 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.
2675763086
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.1885035252
Short name T470
Test name
Test status
Simulation time 172360518 ps
CPU time 1.14 seconds
Started Aug 18 04:35:21 PM PDT 24
Finished Aug 18 04:35:23 PM PDT 24
Peak memory 205268 kb
Host smart-0f5f34c1-d36d-4ac0-95ea-0a6d81cc5db5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885035252 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
1885035252
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.2030661291
Short name T472
Test name
Test status
Simulation time 954202575 ps
CPU time 4.23 seconds
Started Aug 18 04:35:24 PM PDT 24
Finished Aug 18 04:35:28 PM PDT 24
Peak memory 205444 kb
Host smart-d2cebb94-9b86-437b-83f2-c06ea13c2298
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030661291 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.2030661291
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.3497813868
Short name T352
Test name
Test status
Simulation time 243701552 ps
CPU time 4 seconds
Started Aug 18 04:35:22 PM PDT 24
Finished Aug 18 04:35:26 PM PDT 24
Peak memory 213652 kb
Host smart-3c33a9da-8e98-4753-a75e-30a9bb7b5e2e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497813868 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.3497813868
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.2052192398
Short name T414
Test name
Test status
Simulation time 81276549 ps
CPU time 2.88 seconds
Started Aug 18 04:35:26 PM PDT 24
Finished Aug 18 04:35:29 PM PDT 24
Peak memory 218852 kb
Host smart-ce1d9f61-c5a1-4fee-9a4e-b4e24199d10b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052192398 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.2052192398
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.845317692
Short name T444
Test name
Test status
Simulation time 149681134 ps
CPU time 1.47 seconds
Started Aug 18 04:35:36 PM PDT 24
Finished Aug 18 04:35:37 PM PDT 24
Peak memory 213760 kb
Host smart-fb0a965f-26ca-420d-be18-33af057189cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845317692 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.845317692
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.964687175
Short name T427
Test name
Test status
Simulation time 4876478704 ps
CPU time 6.75 seconds
Started Aug 18 04:35:31 PM PDT 24
Finished Aug 18 04:35:38 PM PDT 24
Peak memory 205372 kb
Host smart-6dd079c6-203b-4af4-8cfb-9cf56d1467f7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964687175 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
rv_dm_jtag_dmi_csr_bit_bash.964687175
Directory /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.2288068817
Short name T399
Test name
Test status
Simulation time 1149443757 ps
CPU time 1.91 seconds
Started Aug 18 04:35:33 PM PDT 24
Finished Aug 18 04:35:35 PM PDT 24
Peak memory 205288 kb
Host smart-ac86f653-9dd4-47bd-aa87-645e97048f33
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288068817 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
2288068817
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2377286096
Short name T92
Test name
Test status
Simulation time 1138083250 ps
CPU time 3.73 seconds
Started Aug 18 04:35:28 PM PDT 24
Finished Aug 18 04:35:31 PM PDT 24
Peak memory 205288 kb
Host smart-a4c9e428-d862-493f-b75d-034b7eabddbe
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377286096 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
2377286096
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.1077342660
Short name T137
Test name
Test status
Simulation time 1604477301 ps
CPU time 7.42 seconds
Started Aug 18 04:35:31 PM PDT 24
Finished Aug 18 04:35:38 PM PDT 24
Peak memory 205420 kb
Host smart-5bdd4204-6d53-433d-add4-64a836d48dc1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077342660 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.1077342660
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.1178898132
Short name T390
Test name
Test status
Simulation time 295153952 ps
CPU time 3.21 seconds
Started Aug 18 04:35:29 PM PDT 24
Finished Aug 18 04:35:32 PM PDT 24
Peak memory 213712 kb
Host smart-86be9056-0715-40ea-b32c-2354d40840c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178898132 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.1178898132
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.3328060129
Short name T454
Test name
Test status
Simulation time 2121300668 ps
CPU time 10.18 seconds
Started Aug 18 04:35:29 PM PDT 24
Finished Aug 18 04:35:39 PM PDT 24
Peak memory 213724 kb
Host smart-a85a7679-f625-4e38-a872-e97bc6ddf490
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328060129 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.3
328060129
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.4085629444
Short name T339
Test name
Test status
Simulation time 149585872 ps
CPU time 2.61 seconds
Started Aug 18 04:35:30 PM PDT 24
Finished Aug 18 04:35:33 PM PDT 24
Peak memory 217300 kb
Host smart-b9596511-5682-461a-bf6a-c4ab583b8ce8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085629444 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.4085629444
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.4040695845
Short name T109
Test name
Test status
Simulation time 35606449 ps
CPU time 1.53 seconds
Started Aug 18 04:35:30 PM PDT 24
Finished Aug 18 04:35:31 PM PDT 24
Peak memory 213708 kb
Host smart-87897e4a-a2cf-4987-95ba-fc39210a7991
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040695845 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.4040695845
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.2699180331
Short name T406
Test name
Test status
Simulation time 14509271989 ps
CPU time 14.3 seconds
Started Aug 18 04:35:32 PM PDT 24
Finished Aug 18 04:35:46 PM PDT 24
Peak memory 205304 kb
Host smart-4cf0df10-3fdf-4ea5-9244-b0903d556035
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699180331 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.rv_dm_jtag_dmi_csr_bit_bash.2699180331
Directory /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.1936969439
Short name T332
Test name
Test status
Simulation time 13356419433 ps
CPU time 18.27 seconds
Started Aug 18 04:35:29 PM PDT 24
Finished Aug 18 04:35:47 PM PDT 24
Peak memory 205376 kb
Host smart-bbe12fda-874f-4d4f-862c-9944781904b7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936969439 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
1936969439
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2695819490
Short name T453
Test name
Test status
Simulation time 511685556 ps
CPU time 1.22 seconds
Started Aug 18 04:35:31 PM PDT 24
Finished Aug 18 04:35:33 PM PDT 24
Peak memory 205092 kb
Host smart-07af34d1-ed69-49ad-9c7f-1357700bc15b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695819490 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
2695819490
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.808281886
Short name T123
Test name
Test status
Simulation time 438018027 ps
CPU time 6.67 seconds
Started Aug 18 04:35:28 PM PDT 24
Finished Aug 18 04:35:35 PM PDT 24
Peak memory 205568 kb
Host smart-e8b16a23-81da-40ac-85a5-f7f89b0991af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808281886 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same_
csr_outstanding.808281886
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.221119280
Short name T413
Test name
Test status
Simulation time 327078072 ps
CPU time 4.69 seconds
Started Aug 18 04:35:29 PM PDT 24
Finished Aug 18 04:35:34 PM PDT 24
Peak memory 213604 kb
Host smart-7a43b514-3524-489a-bb82-b9cbbc161edf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221119280 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.221119280
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.2078773259
Short name T362
Test name
Test status
Simulation time 53914681 ps
CPU time 1.77 seconds
Started Aug 18 04:35:35 PM PDT 24
Finished Aug 18 04:35:37 PM PDT 24
Peak memory 214720 kb
Host smart-5e7f2051-aea4-464d-ba95-9344c9a84ad6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078773259 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.2078773259
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.688621095
Short name T131
Test name
Test status
Simulation time 119794760 ps
CPU time 2.3 seconds
Started Aug 18 04:35:31 PM PDT 24
Finished Aug 18 04:35:33 PM PDT 24
Peak memory 218552 kb
Host smart-69c4469a-8da5-4495-a781-700fd07f33ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688621095 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.688621095
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.4100216934
Short name T407
Test name
Test status
Simulation time 27987991807 ps
CPU time 22.51 seconds
Started Aug 18 04:35:31 PM PDT 24
Finished Aug 18 04:35:53 PM PDT 24
Peak memory 205420 kb
Host smart-d02d18e0-c5e9-4b85-8eca-497cd073a79c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100216934 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.rv_dm_jtag_dmi_csr_bit_bash.4100216934
Directory /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3124012312
Short name T479
Test name
Test status
Simulation time 2516514026 ps
CPU time 2.33 seconds
Started Aug 18 04:35:34 PM PDT 24
Finished Aug 18 04:35:36 PM PDT 24
Peak memory 205380 kb
Host smart-9ab8ec79-8c7b-46ef-800e-cfbce8be51e4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124012312 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
3124012312
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.2386343891
Short name T462
Test name
Test status
Simulation time 260047732 ps
CPU time 0.87 seconds
Started Aug 18 04:35:31 PM PDT 24
Finished Aug 18 04:35:32 PM PDT 24
Peak memory 205152 kb
Host smart-106c3cd9-af5e-4deb-866a-3ffd23ee2769
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386343891 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
2386343891
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.1146699019
Short name T120
Test name
Test status
Simulation time 247216114 ps
CPU time 4.11 seconds
Started Aug 18 04:35:28 PM PDT 24
Finished Aug 18 04:35:33 PM PDT 24
Peak memory 205460 kb
Host smart-0aeb372f-e49e-4d87-9b02-af1d75d21f0a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146699019 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.1146699019
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.3151888346
Short name T350
Test name
Test status
Simulation time 159427485 ps
CPU time 2.3 seconds
Started Aug 18 04:35:29 PM PDT 24
Finished Aug 18 04:35:31 PM PDT 24
Peak memory 213628 kb
Host smart-66004d5e-bdb4-4c5d-8f5f-31014969764b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151888346 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.3151888346
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.4260657727
Short name T452
Test name
Test status
Simulation time 2935806582 ps
CPU time 23.62 seconds
Started Aug 18 04:35:31 PM PDT 24
Finished Aug 18 04:35:55 PM PDT 24
Peak memory 221932 kb
Host smart-62964c7a-5bf1-4136-8ffd-95eef3d760c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260657727 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.4
260657727
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.2539003377
Short name T475
Test name
Test status
Simulation time 119669100 ps
CPU time 4.12 seconds
Started Aug 18 04:35:27 PM PDT 24
Finished Aug 18 04:35:32 PM PDT 24
Peak memory 220172 kb
Host smart-63fb8653-9ccd-49ed-9ec8-3558759e2fe1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539003377 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.2539003377
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.338050421
Short name T129
Test name
Test status
Simulation time 188108011 ps
CPU time 1.65 seconds
Started Aug 18 04:35:26 PM PDT 24
Finished Aug 18 04:35:28 PM PDT 24
Peak memory 218864 kb
Host smart-29f8b118-a2a9-49b4-bd48-e1eaef5a8aff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338050421 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.338050421
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.1348826469
Short name T381
Test name
Test status
Simulation time 5014915508 ps
CPU time 14.85 seconds
Started Aug 18 04:35:36 PM PDT 24
Finished Aug 18 04:35:51 PM PDT 24
Peak memory 205540 kb
Host smart-6efee9df-0ad4-499f-8b4d-b4d144b7aaa9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348826469 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.rv_dm_jtag_dmi_csr_bit_bash.1348826469
Directory /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.276363966
Short name T401
Test name
Test status
Simulation time 5948874642 ps
CPU time 5.35 seconds
Started Aug 18 04:35:30 PM PDT 24
Finished Aug 18 04:35:35 PM PDT 24
Peak memory 205444 kb
Host smart-8b7f3199-b726-4282-a1df-5f9d6e627c68
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276363966 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.276363966
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3664511578
Short name T355
Test name
Test status
Simulation time 762883572 ps
CPU time 1.69 seconds
Started Aug 18 04:35:35 PM PDT 24
Finished Aug 18 04:35:37 PM PDT 24
Peak memory 205144 kb
Host smart-a4ea7af9-af6f-4013-a2d6-69063c057802
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664511578 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
3664511578
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.380253726
Short name T437
Test name
Test status
Simulation time 213890327 ps
CPU time 4.02 seconds
Started Aug 18 04:35:31 PM PDT 24
Finished Aug 18 04:35:35 PM PDT 24
Peak memory 205300 kb
Host smart-051586ab-8466-4cfd-a8a0-bca60ec60bb2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380253726 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same_
csr_outstanding.380253726
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.629537405
Short name T442
Test name
Test status
Simulation time 495639181 ps
CPU time 2.9 seconds
Started Aug 18 04:35:35 PM PDT 24
Finished Aug 18 04:35:38 PM PDT 24
Peak memory 213600 kb
Host smart-ec5de6f8-d6a9-4dcb-a07f-9140fabe3892
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629537405 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.629537405
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.3946118119
Short name T391
Test name
Test status
Simulation time 1216184544 ps
CPU time 9.24 seconds
Started Aug 18 04:35:36 PM PDT 24
Finished Aug 18 04:35:45 PM PDT 24
Peak memory 213696 kb
Host smart-f7488c8e-7740-4d7a-8c56-fcd9f401d489
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946118119 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.3
946118119
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.578449369
Short name T340
Test name
Test status
Simulation time 55343990 ps
CPU time 2.03 seconds
Started Aug 18 04:35:28 PM PDT 24
Finished Aug 18 04:35:30 PM PDT 24
Peak memory 217064 kb
Host smart-66e47cd1-1fea-4822-9667-0daa054f345e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578449369 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.578449369
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.2857618524
Short name T469
Test name
Test status
Simulation time 96307948 ps
CPU time 1.64 seconds
Started Aug 18 04:35:27 PM PDT 24
Finished Aug 18 04:35:28 PM PDT 24
Peak memory 218676 kb
Host smart-baa9fd5e-3e74-4eca-91ff-9b393901859b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857618524 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.2857618524
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.3828341426
Short name T431
Test name
Test status
Simulation time 20509253855 ps
CPU time 10.24 seconds
Started Aug 18 04:35:30 PM PDT 24
Finished Aug 18 04:35:40 PM PDT 24
Peak memory 205312 kb
Host smart-96fe14e5-27ab-4bd5-a9a4-dab0f3f69403
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828341426 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.rv_dm_jtag_dmi_csr_bit_bash.3828341426
Directory /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.1309212184
Short name T329
Test name
Test status
Simulation time 2463736310 ps
CPU time 7.32 seconds
Started Aug 18 04:35:33 PM PDT 24
Finished Aug 18 04:35:40 PM PDT 24
Peak memory 205364 kb
Host smart-760c6895-e5fd-48b2-a6f8-0a2466acbdd7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309212184 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.
1309212184
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.652577962
Short name T458
Test name
Test status
Simulation time 331530072 ps
CPU time 1.16 seconds
Started Aug 18 04:35:34 PM PDT 24
Finished Aug 18 04:35:35 PM PDT 24
Peak memory 205052 kb
Host smart-d827fa54-d820-4a8c-8508-87300e5a3951
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652577962 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.652577962
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.2849652337
Short name T105
Test name
Test status
Simulation time 175519595 ps
CPU time 7.04 seconds
Started Aug 18 04:35:31 PM PDT 24
Finished Aug 18 04:35:39 PM PDT 24
Peak memory 205488 kb
Host smart-49efade5-717e-415e-83c6-3855593fa68e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849652337 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.2849652337
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.3911415357
Short name T330
Test name
Test status
Simulation time 531288771 ps
CPU time 4.77 seconds
Started Aug 18 04:35:27 PM PDT 24
Finished Aug 18 04:35:32 PM PDT 24
Peak memory 213564 kb
Host smart-f495a3a5-d455-4725-93f7-14b239e4a147
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911415357 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.3911415357
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.1744796187
Short name T473
Test name
Test status
Simulation time 694748473 ps
CPU time 8.7 seconds
Started Aug 18 04:35:34 PM PDT 24
Finished Aug 18 04:35:43 PM PDT 24
Peak memory 213660 kb
Host smart-0e211fa8-d21b-4f4b-8e09-8c92a3434c8d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744796187 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.1
744796187
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.3153384486
Short name T446
Test name
Test status
Simulation time 105484961 ps
CPU time 2.82 seconds
Started Aug 18 04:35:31 PM PDT 24
Finished Aug 18 04:35:34 PM PDT 24
Peak memory 221448 kb
Host smart-65965211-2070-4a66-a717-2662479de2df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153384486 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.3153384486
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.163571316
Short name T455
Test name
Test status
Simulation time 172795447 ps
CPU time 1.99 seconds
Started Aug 18 04:35:28 PM PDT 24
Finished Aug 18 04:35:30 PM PDT 24
Peak memory 213720 kb
Host smart-0c6b7c1f-a652-40ad-b2c8-af75748bfd3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163571316 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.163571316
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.4222332512
Short name T383
Test name
Test status
Simulation time 2703879605 ps
CPU time 2.12 seconds
Started Aug 18 04:35:31 PM PDT 24
Finished Aug 18 04:35:33 PM PDT 24
Peak memory 205440 kb
Host smart-82c858ba-34d0-4c31-a40c-89decf0b5191
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222332512 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.rv_dm_jtag_dmi_csr_bit_bash.4222332512
Directory /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.656050854
Short name T363
Test name
Test status
Simulation time 1587917892 ps
CPU time 1.86 seconds
Started Aug 18 04:35:30 PM PDT 24
Finished Aug 18 04:35:32 PM PDT 24
Peak memory 205316 kb
Host smart-00ac316a-2d2c-4e69-a232-85d85889f335
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656050854 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.656050854
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.1561571285
Short name T335
Test name
Test status
Simulation time 194170237 ps
CPU time 0.94 seconds
Started Aug 18 04:35:35 PM PDT 24
Finished Aug 18 04:35:36 PM PDT 24
Peak memory 205144 kb
Host smart-2ca6e14f-00ac-4c3a-93e5-9965d26bbd85
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561571285 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
1561571285
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.2658976706
Short name T344
Test name
Test status
Simulation time 215071074 ps
CPU time 4.55 seconds
Started Aug 18 04:35:29 PM PDT 24
Finished Aug 18 04:35:33 PM PDT 24
Peak memory 213656 kb
Host smart-07eeb417-4fa8-4e3e-8696-da8621cc8c08
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658976706 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.2658976706
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.2411447802
Short name T409
Test name
Test status
Simulation time 764507033 ps
CPU time 10.68 seconds
Started Aug 18 04:35:32 PM PDT 24
Finished Aug 18 04:35:43 PM PDT 24
Peak memory 222112 kb
Host smart-5c761e3d-2169-4813-8dcd-e315bccc369c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411447802 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.2
411447802
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.1413357446
Short name T343
Test name
Test status
Simulation time 74913789 ps
CPU time 3.48 seconds
Started Aug 18 04:35:36 PM PDT 24
Finished Aug 18 04:35:39 PM PDT 24
Peak memory 219040 kb
Host smart-d1be4954-63b6-41bd-a0eb-1812db1fc59b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413357446 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.1413357446
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.3674747033
Short name T461
Test name
Test status
Simulation time 65736897 ps
CPU time 1.47 seconds
Started Aug 18 04:35:38 PM PDT 24
Finished Aug 18 04:35:40 PM PDT 24
Peak memory 213676 kb
Host smart-dcd83937-3708-466f-8bc0-dbfd3b8cb480
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674747033 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.3674747033
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.1884718725
Short name T405
Test name
Test status
Simulation time 7526611661 ps
CPU time 16.09 seconds
Started Aug 18 04:35:31 PM PDT 24
Finished Aug 18 04:35:47 PM PDT 24
Peak memory 205396 kb
Host smart-79a1731f-5dfd-4cac-9764-521d4b0a827c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884718725 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.rv_dm_jtag_dmi_csr_bit_bash.1884718725
Directory /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.1418592441
Short name T328
Test name
Test status
Simulation time 2416295453 ps
CPU time 2.43 seconds
Started Aug 18 04:35:33 PM PDT 24
Finished Aug 18 04:35:36 PM PDT 24
Peak memory 205348 kb
Host smart-0be871d8-b66c-48b1-b119-ecc44a41aea5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418592441 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.
1418592441
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.1260419621
Short name T460
Test name
Test status
Simulation time 550837719 ps
CPU time 1.7 seconds
Started Aug 18 04:35:35 PM PDT 24
Finished Aug 18 04:35:37 PM PDT 24
Peak memory 205148 kb
Host smart-17212968-a642-4985-b524-2e287c5d1411
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260419621 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
1260419621
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.4279668453
Short name T110
Test name
Test status
Simulation time 201668834 ps
CPU time 3.72 seconds
Started Aug 18 04:35:36 PM PDT 24
Finished Aug 18 04:35:40 PM PDT 24
Peak memory 205420 kb
Host smart-664e53ef-c8a0-4c8c-9ef8-9089e8ef9157
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279668453 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.4279668453
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.3834664847
Short name T474
Test name
Test status
Simulation time 516503409 ps
CPU time 3.28 seconds
Started Aug 18 04:35:29 PM PDT 24
Finished Aug 18 04:35:32 PM PDT 24
Peak memory 213640 kb
Host smart-430747f1-0e7a-46c7-809f-6d16f5315fff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834664847 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.3834664847
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.4180961278
Short name T371
Test name
Test status
Simulation time 2572301625 ps
CPU time 20.16 seconds
Started Aug 18 04:35:31 PM PDT 24
Finished Aug 18 04:35:51 PM PDT 24
Peak memory 213720 kb
Host smart-35b2025b-5e9f-43a1-a796-4895d8364206
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180961278 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.4
180961278
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.3177685649
Short name T457
Test name
Test status
Simulation time 3476494130 ps
CPU time 31.51 seconds
Started Aug 18 04:35:03 PM PDT 24
Finished Aug 18 04:35:34 PM PDT 24
Peak memory 205512 kb
Host smart-0b463aab-87b5-4721-b8ec-9f1a21ced2b6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177685649 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.3177685649
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.1167799430
Short name T117
Test name
Test status
Simulation time 757496782 ps
CPU time 26.78 seconds
Started Aug 18 04:35:11 PM PDT 24
Finished Aug 18 04:35:38 PM PDT 24
Peak memory 205412 kb
Host smart-06c693ea-9783-42ee-ab9e-9b938bb7fbc6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167799430 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.1167799430
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3906080301
Short name T440
Test name
Test status
Simulation time 443086453 ps
CPU time 1.77 seconds
Started Aug 18 04:35:04 PM PDT 24
Finished Aug 18 04:35:06 PM PDT 24
Peak memory 213644 kb
Host smart-65cf7215-40f5-430a-b2e2-8472b765bad4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906080301 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.3906080301
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3343828643
Short name T467
Test name
Test status
Simulation time 244928335 ps
CPU time 3.94 seconds
Started Aug 18 04:35:06 PM PDT 24
Finished Aug 18 04:35:10 PM PDT 24
Peak memory 221856 kb
Host smart-21019c7a-812e-4c68-8fec-0ed398656b58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343828643 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.3343828643
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.4064000695
Short name T119
Test name
Test status
Simulation time 82581972 ps
CPU time 1.78 seconds
Started Aug 18 04:35:08 PM PDT 24
Finished Aug 18 04:35:10 PM PDT 24
Peak memory 213536 kb
Host smart-0349f33f-8b62-4d3d-a8ae-070565beb14d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064000695 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.4064000695
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2981339025
Short name T365
Test name
Test status
Simulation time 18121152314 ps
CPU time 51.57 seconds
Started Aug 18 04:35:04 PM PDT 24
Finished Aug 18 04:35:55 PM PDT 24
Peak memory 205372 kb
Host smart-04e1d877-14d6-4261-8d34-1796a57d9fc2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981339025 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_aliasing.2981339025
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.2450301698
Short name T464
Test name
Test status
Simulation time 8359178898 ps
CPU time 7.15 seconds
Started Aug 18 04:35:12 PM PDT 24
Finished Aug 18 04:35:19 PM PDT 24
Peak memory 205388 kb
Host smart-7476a284-63a0-4060-8075-42a3eecc0423
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450301698 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
rv_dm_jtag_dmi_csr_bit_bash.2450301698
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.1495176919
Short name T114
Test name
Test status
Simulation time 11645939555 ps
CPU time 8.32 seconds
Started Aug 18 04:35:05 PM PDT 24
Finished Aug 18 04:35:14 PM PDT 24
Peak memory 205392 kb
Host smart-d4c1418d-7200-4ee4-a563-a4026b2268a1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495176919 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.1495176919
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.574768382
Short name T398
Test name
Test status
Simulation time 5254301025 ps
CPU time 7.71 seconds
Started Aug 18 04:35:06 PM PDT 24
Finished Aug 18 04:35:14 PM PDT 24
Peak memory 205572 kb
Host smart-2fdb11d6-5676-4b7e-9302-b75b067a8cd0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574768382 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.574768382
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.2984278631
Short name T441
Test name
Test status
Simulation time 193370366 ps
CPU time 0.93 seconds
Started Aug 18 04:35:06 PM PDT 24
Finished Aug 18 04:35:07 PM PDT 24
Peak memory 205280 kb
Host smart-2e3218a0-0f21-41e0-86d7-041bcc0f935f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984278631 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_aliasing.2984278631
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.4201989599
Short name T449
Test name
Test status
Simulation time 8281567340 ps
CPU time 10.45 seconds
Started Aug 18 04:35:12 PM PDT 24
Finished Aug 18 04:35:22 PM PDT 24
Peak memory 205408 kb
Host smart-2edb3e64-bcdc-4c41-a818-dd642e87cfce
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201989599 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_bit_bash.4201989599
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.1676516411
Short name T369
Test name
Test status
Simulation time 150585820 ps
CPU time 1.04 seconds
Started Aug 18 04:35:03 PM PDT 24
Finished Aug 18 04:35:05 PM PDT 24
Peak memory 205128 kb
Host smart-708be8f6-c6c1-4858-8482-c91c91d44077
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676516411 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.1676516411
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.1461627449
Short name T424
Test name
Test status
Simulation time 542808925 ps
CPU time 0.94 seconds
Started Aug 18 04:35:02 PM PDT 24
Finished Aug 18 04:35:04 PM PDT 24
Peak memory 205144 kb
Host smart-f7ea25e9-85a4-4032-b99c-26be67a4626f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461627449 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.1
461627449
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2119091030
Short name T389
Test name
Test status
Simulation time 60194707 ps
CPU time 0.83 seconds
Started Aug 18 04:35:03 PM PDT 24
Finished Aug 18 04:35:05 PM PDT 24
Peak memory 205420 kb
Host smart-6e4fb36a-495f-46ca-b217-3c378d27aac0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119091030 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.2119091030
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.2540226538
Short name T336
Test name
Test status
Simulation time 60691182 ps
CPU time 0.86 seconds
Started Aug 18 04:35:08 PM PDT 24
Finished Aug 18 04:35:09 PM PDT 24
Peak memory 205140 kb
Host smart-00e7e3c9-ffbb-44be-b088-380b0e6c9506
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540226538 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.2540226538
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.3508782654
Short name T135
Test name
Test status
Simulation time 419174556 ps
CPU time 7.11 seconds
Started Aug 18 04:35:06 PM PDT 24
Finished Aug 18 04:35:13 PM PDT 24
Peak memory 205416 kb
Host smart-c2940900-ffa9-456a-b5dc-0b1cee3da35d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508782654 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.3508782654
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.563561548
Short name T88
Test name
Test status
Simulation time 2085864791 ps
CPU time 51.63 seconds
Started Aug 18 04:35:07 PM PDT 24
Finished Aug 18 04:35:58 PM PDT 24
Peak memory 215316 kb
Host smart-498e839e-1913-4118-80c2-a32976ef206c
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563561548 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.563561548
Directory /workspace/2.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.1575286536
Short name T338
Test name
Test status
Simulation time 100650153 ps
CPU time 2.47 seconds
Started Aug 18 04:35:07 PM PDT 24
Finished Aug 18 04:35:10 PM PDT 24
Peak memory 213608 kb
Host smart-aebb3e4a-db2b-43e9-a15d-fc32847b2ee5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575286536 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.1575286536
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.2975166332
Short name T106
Test name
Test status
Simulation time 1217131353 ps
CPU time 67.93 seconds
Started Aug 18 04:35:12 PM PDT 24
Finished Aug 18 04:36:20 PM PDT 24
Peak memory 205372 kb
Host smart-39c44e4d-b4e1-4290-a313-803db457c349
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975166332 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.2975166332
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1142418522
Short name T359
Test name
Test status
Simulation time 21319618428 ps
CPU time 39.62 seconds
Started Aug 18 04:35:13 PM PDT 24
Finished Aug 18 04:35:53 PM PDT 24
Peak memory 205504 kb
Host smart-8898800e-4d41-4ce3-8539-480b87791f22
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142418522 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.1142418522
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.2534208530
Short name T133
Test name
Test status
Simulation time 122367091 ps
CPU time 1.88 seconds
Started Aug 18 04:35:14 PM PDT 24
Finished Aug 18 04:35:16 PM PDT 24
Peak memory 213628 kb
Host smart-2114faca-03d8-4a3c-b743-89c2e5c90849
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534208530 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.2534208530
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.1728423901
Short name T448
Test name
Test status
Simulation time 246275739 ps
CPU time 2 seconds
Started Aug 18 04:35:15 PM PDT 24
Finished Aug 18 04:35:17 PM PDT 24
Peak memory 216324 kb
Host smart-df807e34-74ef-4a51-9cee-4d96bbf324e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728423901 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.1728423901
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.1830257584
Short name T450
Test name
Test status
Simulation time 150902234 ps
CPU time 1.89 seconds
Started Aug 18 04:35:12 PM PDT 24
Finished Aug 18 04:35:14 PM PDT 24
Peak memory 219192 kb
Host smart-6e26917a-171d-4faa-afab-c292f5c71407
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830257584 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.1830257584
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.4200185367
Short name T345
Test name
Test status
Simulation time 15549691760 ps
CPU time 14.44 seconds
Started Aug 18 04:35:11 PM PDT 24
Finished Aug 18 04:35:26 PM PDT 24
Peak memory 205468 kb
Host smart-233ecaa7-289c-499a-8a80-2ac2eeb1231f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200185367 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.4200185367
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.1882474037
Short name T420
Test name
Test status
Simulation time 24983917255 ps
CPU time 10.2 seconds
Started Aug 18 04:35:13 PM PDT 24
Finished Aug 18 04:35:23 PM PDT 24
Peak memory 205380 kb
Host smart-18a6bb87-24d0-48ca-a8be-f7782b3a8b2c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882474037 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
rv_dm_jtag_dmi_csr_bit_bash.1882474037
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.1709045356
Short name T347
Test name
Test status
Simulation time 2369443250 ps
CPU time 3.12 seconds
Started Aug 18 04:35:14 PM PDT 24
Finished Aug 18 04:35:17 PM PDT 24
Peak memory 205324 kb
Host smart-e18a1aa9-1571-4d2e-bb41-9d80849ec867
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709045356 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_hw_reset.1709045356
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.1133837046
Short name T356
Test name
Test status
Simulation time 1707467994 ps
CPU time 3.13 seconds
Started Aug 18 04:35:11 PM PDT 24
Finished Aug 18 04:35:15 PM PDT 24
Peak memory 205316 kb
Host smart-4c0e6ac9-d3ed-4825-8538-bad71b316f9c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133837046 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.1
133837046
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.3845548953
Short name T354
Test name
Test status
Simulation time 485296054 ps
CPU time 2 seconds
Started Aug 18 04:35:11 PM PDT 24
Finished Aug 18 04:35:13 PM PDT 24
Peak memory 205080 kb
Host smart-7bd806f9-aeb6-4a5b-a1c0-973569b67be0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845548953 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.3845548953
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2244031454
Short name T387
Test name
Test status
Simulation time 5022256271 ps
CPU time 5.12 seconds
Started Aug 18 04:35:10 PM PDT 24
Finished Aug 18 04:35:16 PM PDT 24
Peak memory 205560 kb
Host smart-4114f67e-7a47-4e8c-9ca2-b3a55d6f81ff
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244031454 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_bit_bash.2244031454
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.2619060402
Short name T477
Test name
Test status
Simulation time 951175216 ps
CPU time 1.2 seconds
Started Aug 18 04:35:07 PM PDT 24
Finished Aug 18 04:35:08 PM PDT 24
Peak memory 205216 kb
Host smart-3b61500c-56ea-4652-873b-5d9523c1445b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619060402 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_hw_reset.2619060402
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.172808954
Short name T360
Test name
Test status
Simulation time 249651643 ps
CPU time 0.84 seconds
Started Aug 18 04:35:04 PM PDT 24
Finished Aug 18 04:35:05 PM PDT 24
Peak memory 205112 kb
Host smart-b9623544-ea40-4725-a1ab-4d95fef109ce
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172808954 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.172808954
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.1493322013
Short name T415
Test name
Test status
Simulation time 37695870 ps
CPU time 0.73 seconds
Started Aug 18 04:35:12 PM PDT 24
Finished Aug 18 04:35:13 PM PDT 24
Peak memory 205228 kb
Host smart-c53f860b-78b2-43a4-bdf0-27de9082ede0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493322013 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.1493322013
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.1338152882
Short name T384
Test name
Test status
Simulation time 67785885 ps
CPU time 0.8 seconds
Started Aug 18 04:35:11 PM PDT 24
Finished Aug 18 04:35:12 PM PDT 24
Peak memory 205172 kb
Host smart-90d760df-4292-455d-a7c3-00cf2ad164db
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338152882 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.1338152882
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.228165511
Short name T436
Test name
Test status
Simulation time 898958607 ps
CPU time 7.25 seconds
Started Aug 18 04:35:10 PM PDT 24
Finished Aug 18 04:35:18 PM PDT 24
Peak memory 205392 kb
Host smart-5d895313-2145-48a7-b793-7aface3204ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228165511 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_c
sr_outstanding.228165511
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.3707725047
Short name T80
Test name
Test status
Simulation time 22141253784 ps
CPU time 20.35 seconds
Started Aug 18 04:35:12 PM PDT 24
Finished Aug 18 04:35:32 PM PDT 24
Peak memory 216960 kb
Host smart-a6f38d67-bbe5-415b-972d-53b3d5176837
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707725047 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.3707725047
Directory /workspace/3.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.507477509
Short name T364
Test name
Test status
Simulation time 116823640 ps
CPU time 6.2 seconds
Started Aug 18 04:35:12 PM PDT 24
Finished Aug 18 04:35:18 PM PDT 24
Peak memory 213676 kb
Host smart-8209ce8a-e3e7-4114-af23-5fa7cf493784
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507477509 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.507477509
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2324690530
Short name T372
Test name
Test status
Simulation time 3489095255 ps
CPU time 10.52 seconds
Started Aug 18 04:35:12 PM PDT 24
Finished Aug 18 04:35:23 PM PDT 24
Peak memory 213796 kb
Host smart-a67fc09f-7f63-4ac6-a880-505e633b64f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324690530 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.2324690530
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.643322484
Short name T433
Test name
Test status
Simulation time 2540853674 ps
CPU time 35.76 seconds
Started Aug 18 04:35:13 PM PDT 24
Finished Aug 18 04:35:49 PM PDT 24
Peak memory 213748 kb
Host smart-b90d49f0-02b2-43d7-a9fa-991a35c9eb5a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643322484 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.rv_dm_csr_aliasing.643322484
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.181253990
Short name T380
Test name
Test status
Simulation time 1845039327 ps
CPU time 56.21 seconds
Started Aug 18 04:35:13 PM PDT 24
Finished Aug 18 04:36:09 PM PDT 24
Peak memory 205424 kb
Host smart-7451e652-febe-429a-af3c-e78dcc233f95
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181253990 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.181253990
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.1888485788
Short name T124
Test name
Test status
Simulation time 922897707 ps
CPU time 2.3 seconds
Started Aug 18 04:35:13 PM PDT 24
Finished Aug 18 04:35:16 PM PDT 24
Peak memory 213696 kb
Host smart-3bc3168d-eeac-4e2c-8c4e-e5c941b6500f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888485788 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.1888485788
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2314292705
Short name T333
Test name
Test status
Simulation time 74181404 ps
CPU time 4.12 seconds
Started Aug 18 04:35:09 PM PDT 24
Finished Aug 18 04:35:14 PM PDT 24
Peak memory 213672 kb
Host smart-34cc659e-185f-4c94-9128-1b511fb1f3b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314292705 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.2314292705
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.223836295
Short name T118
Test name
Test status
Simulation time 313444485 ps
CPU time 2.41 seconds
Started Aug 18 04:35:12 PM PDT 24
Finished Aug 18 04:35:15 PM PDT 24
Peak memory 213636 kb
Host smart-6e206a85-e893-402c-99c0-a41898d64abc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223836295 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.223836295
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.3395756311
Short name T370
Test name
Test status
Simulation time 43909436270 ps
CPU time 33.97 seconds
Started Aug 18 04:35:14 PM PDT 24
Finished Aug 18 04:35:48 PM PDT 24
Peak memory 205304 kb
Host smart-8c83c385-1783-4a7e-af04-232bd3c44e6e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395756311 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_aliasing.3395756311
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.3506275606
Short name T396
Test name
Test status
Simulation time 53178109724 ps
CPU time 149.6 seconds
Started Aug 18 04:35:12 PM PDT 24
Finished Aug 18 04:37:42 PM PDT 24
Peak memory 205380 kb
Host smart-a4859869-bdb5-487d-94e0-4501a832f740
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506275606 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
rv_dm_jtag_dmi_csr_bit_bash.3506275606
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.4172449951
Short name T113
Test name
Test status
Simulation time 2440376737 ps
CPU time 6.35 seconds
Started Aug 18 04:35:11 PM PDT 24
Finished Aug 18 04:35:18 PM PDT 24
Peak memory 205372 kb
Host smart-e3704893-5d41-45ad-849c-6004f4696d29
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172449951 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.4172449951
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.4250959319
Short name T386
Test name
Test status
Simulation time 2766458073 ps
CPU time 3.48 seconds
Started Aug 18 04:35:13 PM PDT 24
Finished Aug 18 04:35:16 PM PDT 24
Peak memory 205304 kb
Host smart-b5f16932-3939-4985-a2ae-44e67688c6f9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250959319 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.4
250959319
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.197742890
Short name T394
Test name
Test status
Simulation time 380808881 ps
CPU time 1.13 seconds
Started Aug 18 04:35:10 PM PDT 24
Finished Aug 18 04:35:12 PM PDT 24
Peak memory 205124 kb
Host smart-8878a200-38d1-4b7c-a2ce-61d2c38d7909
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197742890 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr
_aliasing.197742890
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.1012773820
Short name T445
Test name
Test status
Simulation time 3956414542 ps
CPU time 11.2 seconds
Started Aug 18 04:35:12 PM PDT 24
Finished Aug 18 04:35:23 PM PDT 24
Peak memory 205372 kb
Host smart-0b799566-f63a-4311-9f05-ce2ed9754e5c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012773820 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.1012773820
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.4206691621
Short name T382
Test name
Test status
Simulation time 985341300 ps
CPU time 2.95 seconds
Started Aug 18 04:35:14 PM PDT 24
Finished Aug 18 04:35:17 PM PDT 24
Peak memory 205140 kb
Host smart-5f9afd05-f7da-4992-bd62-eb0c988d924f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206691621 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.4206691621
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2472549119
Short name T480
Test name
Test status
Simulation time 404442841 ps
CPU time 1.03 seconds
Started Aug 18 04:35:12 PM PDT 24
Finished Aug 18 04:35:14 PM PDT 24
Peak memory 205120 kb
Host smart-6b75687b-590e-42ec-9c55-d0c7659e5b04
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472549119 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.2
472549119
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.1653162626
Short name T327
Test name
Test status
Simulation time 112206387 ps
CPU time 0.76 seconds
Started Aug 18 04:35:12 PM PDT 24
Finished Aug 18 04:35:13 PM PDT 24
Peak memory 205104 kb
Host smart-3748810d-1fc4-4316-b499-a476a0d76ad1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653162626 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.1653162626
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.3451294159
Short name T403
Test name
Test status
Simulation time 28184022 ps
CPU time 0.72 seconds
Started Aug 18 04:35:13 PM PDT 24
Finished Aug 18 04:35:14 PM PDT 24
Peak memory 205160 kb
Host smart-dd63b739-fa8e-4952-b66a-cdc46ff0e9fa
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451294159 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.3451294159
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3750893761
Short name T101
Test name
Test status
Simulation time 112916789 ps
CPU time 3.97 seconds
Started Aug 18 04:35:12 PM PDT 24
Finished Aug 18 04:35:16 PM PDT 24
Peak memory 205428 kb
Host smart-eba0882c-3e22-48f9-abea-57f367bd427f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750893761 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.3750893761
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.1915586552
Short name T81
Test name
Test status
Simulation time 18816847369 ps
CPU time 68.99 seconds
Started Aug 18 04:35:13 PM PDT 24
Finished Aug 18 04:36:22 PM PDT 24
Peak memory 218728 kb
Host smart-0088edef-de9b-4e74-a622-fd8c5763042c
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915586552 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.1915586552
Directory /workspace/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2693507425
Short name T337
Test name
Test status
Simulation time 139573712 ps
CPU time 2.36 seconds
Started Aug 18 04:35:14 PM PDT 24
Finished Aug 18 04:35:17 PM PDT 24
Peak memory 213636 kb
Host smart-12df13ab-7507-4b79-8593-6bc9c520325a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693507425 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.2693507425
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.682514315
Short name T375
Test name
Test status
Simulation time 165573220 ps
CPU time 3.76 seconds
Started Aug 18 04:35:24 PM PDT 24
Finished Aug 18 04:35:28 PM PDT 24
Peak memory 219696 kb
Host smart-56a4bb94-9447-401b-829c-c6044727ec88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682514315 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.682514315
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.3639169111
Short name T116
Test name
Test status
Simulation time 163706639 ps
CPU time 2.52 seconds
Started Aug 18 04:35:20 PM PDT 24
Finished Aug 18 04:35:22 PM PDT 24
Peak memory 213592 kb
Host smart-bcde60ea-4a5a-4ca3-aaaf-a090ecbaa38d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639169111 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.3639169111
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.2059187220
Short name T423
Test name
Test status
Simulation time 58902870 ps
CPU time 0.66 seconds
Started Aug 18 04:35:12 PM PDT 24
Finished Aug 18 04:35:13 PM PDT 24
Peak memory 205144 kb
Host smart-d03e481f-6c1e-4378-85a7-3dd24cfc8802
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059187220 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
rv_dm_jtag_dmi_csr_bit_bash.2059187220
Directory /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.2556794454
Short name T385
Test name
Test status
Simulation time 5973565216 ps
CPU time 3.73 seconds
Started Aug 18 04:35:12 PM PDT 24
Finished Aug 18 04:35:16 PM PDT 24
Peak memory 205500 kb
Host smart-af491afa-06b9-401b-ab6a-0af8745b3678
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556794454 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.2
556794454
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.883256592
Short name T374
Test name
Test status
Simulation time 230574575 ps
CPU time 1.02 seconds
Started Aug 18 04:35:13 PM PDT 24
Finished Aug 18 04:35:14 PM PDT 24
Peak memory 205120 kb
Host smart-e753c028-cc0f-4389-9d5b-9564db975540
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883256592 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.883256592
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.2862989813
Short name T136
Test name
Test status
Simulation time 377206667 ps
CPU time 4.31 seconds
Started Aug 18 04:35:24 PM PDT 24
Finished Aug 18 04:35:28 PM PDT 24
Peak memory 205332 kb
Host smart-3a638bf7-338c-48ca-a619-7f11ba05354f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862989813 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.2862989813
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.692814753
Short name T397
Test name
Test status
Simulation time 309638963 ps
CPU time 4.2 seconds
Started Aug 18 04:35:11 PM PDT 24
Finished Aug 18 04:35:15 PM PDT 24
Peak memory 213628 kb
Host smart-313ae627-37af-4fe6-8d4e-6e6c44e918b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692814753 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.692814753
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.103045009
Short name T182
Test name
Test status
Simulation time 2338299186 ps
CPU time 16.43 seconds
Started Aug 18 04:35:12 PM PDT 24
Finished Aug 18 04:35:29 PM PDT 24
Peak memory 221932 kb
Host smart-442a4955-7233-4de2-b770-2b8301b4c7ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103045009 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.103045009
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.942145001
Short name T459
Test name
Test status
Simulation time 101835433 ps
CPU time 1.93 seconds
Started Aug 18 04:35:26 PM PDT 24
Finished Aug 18 04:35:28 PM PDT 24
Peak memory 214664 kb
Host smart-89590496-781b-40e5-b938-9c81ede1e875
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942145001 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.942145001
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.21953711
Short name T126
Test name
Test status
Simulation time 81485696 ps
CPU time 1.58 seconds
Started Aug 18 04:35:22 PM PDT 24
Finished Aug 18 04:35:24 PM PDT 24
Peak memory 219020 kb
Host smart-cf3e9782-6f14-40fd-9e96-ce616167021b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21953711 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.21953711
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.1259917365
Short name T346
Test name
Test status
Simulation time 21071005189 ps
CPU time 44.17 seconds
Started Aug 18 04:35:19 PM PDT 24
Finished Aug 18 04:36:04 PM PDT 24
Peak memory 205348 kb
Host smart-8e28cc6b-ccaa-4201-a982-2c22b6b50237
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259917365 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
rv_dm_jtag_dmi_csr_bit_bash.1259917365
Directory /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2326376843
Short name T476
Test name
Test status
Simulation time 2880543288 ps
CPU time 3.26 seconds
Started Aug 18 04:35:24 PM PDT 24
Finished Aug 18 04:35:27 PM PDT 24
Peak memory 205440 kb
Host smart-465e29af-3732-4694-ac6e-a32eec884299
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326376843 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.2
326376843
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.730070227
Short name T430
Test name
Test status
Simulation time 1163612429 ps
CPU time 2.33 seconds
Started Aug 18 04:35:21 PM PDT 24
Finished Aug 18 04:35:24 PM PDT 24
Peak memory 205148 kb
Host smart-70c2706a-2104-4b23-902f-288a835104dc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730070227 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.730070227
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.3155633515
Short name T134
Test name
Test status
Simulation time 395842236 ps
CPU time 3.48 seconds
Started Aug 18 04:35:20 PM PDT 24
Finished Aug 18 04:35:24 PM PDT 24
Peak memory 205400 kb
Host smart-b07d5b7f-776d-4856-a0c6-a7df508d80db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155633515 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.3155633515
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.330117126
Short name T366
Test name
Test status
Simulation time 4185741008 ps
CPU time 35.61 seconds
Started Aug 18 04:35:24 PM PDT 24
Finished Aug 18 04:36:00 PM PDT 24
Peak memory 213728 kb
Host smart-6b70926d-0ca0-4ebb-b599-0843b3a12fcc
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330117126 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.330117126
Directory /workspace/6.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.3993398489
Short name T140
Test name
Test status
Simulation time 269325902 ps
CPU time 2.18 seconds
Started Aug 18 04:35:22 PM PDT 24
Finished Aug 18 04:35:25 PM PDT 24
Peak memory 213556 kb
Host smart-ac26e219-7085-4274-9763-4cfb3ce71391
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993398489 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.3993398489
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.3266396672
Short name T139
Test name
Test status
Simulation time 2131774755 ps
CPU time 20.54 seconds
Started Aug 18 04:35:19 PM PDT 24
Finished Aug 18 04:35:40 PM PDT 24
Peak memory 221856 kb
Host smart-a1fb4774-ba2d-45d9-a735-e5ea96a04769
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266396672 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.3266396672
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.2764955129
Short name T361
Test name
Test status
Simulation time 13840695131 ps
CPU time 9.46 seconds
Started Aug 18 04:35:18 PM PDT 24
Finished Aug 18 04:35:28 PM PDT 24
Peak memory 205348 kb
Host smart-f4cc9036-7863-44b0-9962-0effe6c5a189
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764955129 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
rv_dm_jtag_dmi_csr_bit_bash.2764955129
Directory /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.3196832879
Short name T417
Test name
Test status
Simulation time 5925747793 ps
CPU time 2.82 seconds
Started Aug 18 04:35:21 PM PDT 24
Finished Aug 18 04:35:24 PM PDT 24
Peak memory 205352 kb
Host smart-edf763b5-f642-4279-8ea5-4dfbf26517cd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196832879 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.3
196832879
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.3186678881
Short name T353
Test name
Test status
Simulation time 248268900 ps
CPU time 0.85 seconds
Started Aug 18 04:35:26 PM PDT 24
Finished Aug 18 04:35:27 PM PDT 24
Peak memory 205136 kb
Host smart-d6bad54c-cabe-43e9-9a3f-575d5c26d29d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186678881 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.3
186678881
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.1758717370
Short name T411
Test name
Test status
Simulation time 192874458 ps
CPU time 4.17 seconds
Started Aug 18 04:35:23 PM PDT 24
Finished Aug 18 04:35:27 PM PDT 24
Peak memory 205840 kb
Host smart-da61d38f-5c65-4b69-b661-6209944dd844
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758717370 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.1758717370
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.2098548238
Short name T393
Test name
Test status
Simulation time 123959663 ps
CPU time 2.43 seconds
Started Aug 18 04:35:21 PM PDT 24
Finished Aug 18 04:35:24 PM PDT 24
Peak memory 213600 kb
Host smart-8ccb9ff8-fce1-41ed-aed4-e606b36bd50b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098548238 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.2098548238
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.3340726845
Short name T439
Test name
Test status
Simulation time 5738070454 ps
CPU time 24.45 seconds
Started Aug 18 04:35:22 PM PDT 24
Finished Aug 18 04:35:47 PM PDT 24
Peak memory 213660 kb
Host smart-e7e093ec-8233-4b2a-8e52-a7e811080c96
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340726845 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.3340726845
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.964312775
Short name T377
Test name
Test status
Simulation time 162937515 ps
CPU time 3.31 seconds
Started Aug 18 04:35:24 PM PDT 24
Finished Aug 18 04:35:27 PM PDT 24
Peak memory 221752 kb
Host smart-d4fbbbfb-3429-45d4-aceb-77c19bd770d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964312775 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.964312775
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.2288857138
Short name T482
Test name
Test status
Simulation time 196277918 ps
CPU time 1.96 seconds
Started Aug 18 04:35:22 PM PDT 24
Finished Aug 18 04:35:24 PM PDT 24
Peak memory 213532 kb
Host smart-050f9f48-676e-41eb-b077-5170b279ff5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288857138 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.2288857138
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.4050057278
Short name T349
Test name
Test status
Simulation time 8814522280 ps
CPU time 14.32 seconds
Started Aug 18 04:35:20 PM PDT 24
Finished Aug 18 04:35:34 PM PDT 24
Peak memory 205464 kb
Host smart-b0dcf7b9-7004-43c2-8e8b-fb4ab2b8c447
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050057278 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
rv_dm_jtag_dmi_csr_bit_bash.4050057278
Directory /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.2384858465
Short name T456
Test name
Test status
Simulation time 2973349620 ps
CPU time 8.99 seconds
Started Aug 18 04:35:20 PM PDT 24
Finished Aug 18 04:35:30 PM PDT 24
Peak memory 205572 kb
Host smart-c103ae31-087b-4b28-baf1-7c4b10af32b1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384858465 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.2
384858465
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.4150964951
Short name T412
Test name
Test status
Simulation time 178362164 ps
CPU time 0.81 seconds
Started Aug 18 04:35:19 PM PDT 24
Finished Aug 18 04:35:20 PM PDT 24
Peak memory 205156 kb
Host smart-b9648c2a-d430-4a2c-832e-4a246e1f0c0c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150964951 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.4
150964951
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.1453780507
Short name T122
Test name
Test status
Simulation time 1115254944 ps
CPU time 8.26 seconds
Started Aug 18 04:35:22 PM PDT 24
Finished Aug 18 04:35:31 PM PDT 24
Peak memory 205104 kb
Host smart-1c46eb73-2851-4ba0-b171-4fcea7bbe2d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453780507 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_
csr_outstanding.1453780507
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.1881204860
Short name T83
Test name
Test status
Simulation time 5038762090 ps
CPU time 58.46 seconds
Started Aug 18 04:35:20 PM PDT 24
Finished Aug 18 04:36:19 PM PDT 24
Peak memory 213816 kb
Host smart-64ee7f8c-70ce-46cd-baba-734f0aea4c0b
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881204860 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.1881204860
Directory /workspace/8.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.2377008790
Short name T138
Test name
Test status
Simulation time 326397306 ps
CPU time 3.92 seconds
Started Aug 18 04:35:22 PM PDT 24
Finished Aug 18 04:35:26 PM PDT 24
Peak memory 213544 kb
Host smart-f8a58762-1181-4abd-b00a-a1081cb70395
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377008790 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.2377008790
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.1411102456
Short name T181
Test name
Test status
Simulation time 2928908147 ps
CPU time 11.6 seconds
Started Aug 18 04:35:20 PM PDT 24
Finished Aug 18 04:35:32 PM PDT 24
Peak memory 222004 kb
Host smart-cb3e7df1-e275-4eda-a246-e8c9b0164e9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411102456 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.1411102456
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.3234175307
Short name T89
Test name
Test status
Simulation time 103151587 ps
CPU time 4.16 seconds
Started Aug 18 04:35:22 PM PDT 24
Finished Aug 18 04:35:26 PM PDT 24
Peak memory 221972 kb
Host smart-b94e6e37-91e7-4351-9d70-8771ac5c138e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234175307 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.3234175307
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.2378333012
Short name T435
Test name
Test status
Simulation time 43499555 ps
CPU time 1.49 seconds
Started Aug 18 04:35:19 PM PDT 24
Finished Aug 18 04:35:21 PM PDT 24
Peak memory 218840 kb
Host smart-6197b084-aa59-479c-90f3-8ab5d93d5980
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378333012 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.2378333012
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.3327964005
Short name T425
Test name
Test status
Simulation time 99280321879 ps
CPU time 135.75 seconds
Started Aug 18 04:35:21 PM PDT 24
Finished Aug 18 04:37:37 PM PDT 24
Peak memory 205396 kb
Host smart-a700a477-09d8-4892-b14e-82c27a7325d8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327964005 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
rv_dm_jtag_dmi_csr_bit_bash.3327964005
Directory /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.1019932085
Short name T334
Test name
Test status
Simulation time 4676199103 ps
CPU time 13.83 seconds
Started Aug 18 04:35:19 PM PDT 24
Finished Aug 18 04:35:33 PM PDT 24
Peak memory 204448 kb
Host smart-137ce0b0-2df1-426f-8f17-2ee34814adf8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019932085 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.1
019932085
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.3833047365
Short name T351
Test name
Test status
Simulation time 681055186 ps
CPU time 1.77 seconds
Started Aug 18 04:35:24 PM PDT 24
Finished Aug 18 04:35:26 PM PDT 24
Peak memory 205164 kb
Host smart-f0bb0855-d610-4cdf-a7cb-bb003910d4a6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833047365 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.3
833047365
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.3016100003
Short name T103
Test name
Test status
Simulation time 486433203 ps
CPU time 6.6 seconds
Started Aug 18 04:35:22 PM PDT 24
Finished Aug 18 04:35:28 PM PDT 24
Peak memory 205360 kb
Host smart-7f50a511-ec92-4c29-9c5a-c2111a5358a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016100003 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_
csr_outstanding.3016100003
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.1298671563
Short name T451
Test name
Test status
Simulation time 3687074339 ps
CPU time 28.63 seconds
Started Aug 18 04:35:19 PM PDT 24
Finished Aug 18 04:35:48 PM PDT 24
Peak memory 221304 kb
Host smart-3d0550f7-9bb3-46a0-bb25-0740a7cc8af0
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298671563 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.1298671563
Directory /workspace/9.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.234889871
Short name T388
Test name
Test status
Simulation time 347125844 ps
CPU time 6.93 seconds
Started Aug 18 04:35:22 PM PDT 24
Finished Aug 18 04:35:29 PM PDT 24
Peak memory 213696 kb
Host smart-e5ae455d-d42c-4c7b-ac38-c43051c1b489
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234889871 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.234889871
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.608978278
Short name T481
Test name
Test status
Simulation time 698398546 ps
CPU time 9.81 seconds
Started Aug 18 04:35:25 PM PDT 24
Finished Aug 18 04:35:34 PM PDT 24
Peak memory 221720 kb
Host smart-8e14ffad-653a-4da8-ba00-dbf09e6c15e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608978278 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.608978278
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_abstractcmd_status.3968100003
Short name T50
Test name
Test status
Simulation time 157564707 ps
CPU time 0.82 seconds
Started Aug 18 04:38:59 PM PDT 24
Finished Aug 18 04:39:00 PM PDT 24
Peak memory 204848 kb
Host smart-d8cc5860-cb6a-4da3-9822-789eb88cea06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968100003 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.3968100003
Directory /workspace/0.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.975103000
Short name T71
Test name
Test status
Simulation time 62971377 ps
CPU time 0.78 seconds
Started Aug 18 04:38:59 PM PDT 24
Finished Aug 18 04:39:00 PM PDT 24
Peak memory 204920 kb
Host smart-50a64240-c928-4ae4-9915-d6a4561d5486
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975103000 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.975103000
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.1387669540
Short name T190
Test name
Test status
Simulation time 18190677651 ps
CPU time 49.15 seconds
Started Aug 18 04:38:52 PM PDT 24
Finished Aug 18 04:39:41 PM PDT 24
Peak memory 213500 kb
Host smart-aede94b6-a641-4739-8e63-bd6d3595786d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387669540 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.1387669540
Directory /workspace/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.2243847523
Short name T263
Test name
Test status
Simulation time 1301125416 ps
CPU time 4.42 seconds
Started Aug 18 04:38:52 PM PDT 24
Finished Aug 18 04:38:56 PM PDT 24
Peak memory 205296 kb
Host smart-ad3504da-0052-4e18-b9b5-3376ff00c8bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243847523 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.2243847523
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_buffered_enable.3853728635
Short name T151
Test name
Test status
Simulation time 474305838 ps
CPU time 1.16 seconds
Started Aug 18 04:39:02 PM PDT 24
Finished Aug 18 04:39:03 PM PDT 24
Peak memory 225796 kb
Host smart-e5f9a7fc-0360-44e3-a286-d4c97e5e7b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853728635 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_buffered_enable.3853728635
Directory /workspace/0.rv_dm_buffered_enable/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.3452482980
Short name T188
Test name
Test status
Simulation time 530709653 ps
CPU time 1.05 seconds
Started Aug 18 04:38:50 PM PDT 24
Finished Aug 18 04:38:52 PM PDT 24
Peak memory 204900 kb
Host smart-d9a5607d-1a26-460c-a303-e9f7181735ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452482980 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.3452482980
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.1741180006
Short name T18
Test name
Test status
Simulation time 153481444 ps
CPU time 0.88 seconds
Started Aug 18 04:38:52 PM PDT 24
Finished Aug 18 04:38:53 PM PDT 24
Peak memory 204828 kb
Host smart-bac88011-8e8f-4996-aa2f-065592fdb78e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741180006 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.1741180006
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.457821729
Short name T282
Test name
Test status
Simulation time 673686705 ps
CPU time 2.24 seconds
Started Aug 18 04:38:50 PM PDT 24
Finished Aug 18 04:38:52 PM PDT 24
Peak memory 204852 kb
Host smart-079a19dd-88ba-4b31-8305-4eeb5c040ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457821729 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.457821729
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.468396127
Short name T159
Test name
Test status
Simulation time 80588071 ps
CPU time 0.78 seconds
Started Aug 18 04:38:58 PM PDT 24
Finished Aug 18 04:38:59 PM PDT 24
Peak memory 204900 kb
Host smart-1443cd5f-6537-4e42-8397-ab5da11a31f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468396127 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.468396127
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_debug_disabled.343855924
Short name T297
Test name
Test status
Simulation time 85522777 ps
CPU time 0.97 seconds
Started Aug 18 04:39:06 PM PDT 24
Finished Aug 18 04:39:07 PM PDT 24
Peak memory 215024 kb
Host smart-55672e8b-6e2f-488d-b652-627a63190542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343855924 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.343855924
Directory /workspace/0.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.618029548
Short name T325
Test name
Test status
Simulation time 2139969674 ps
CPU time 6.71 seconds
Started Aug 18 04:38:50 PM PDT 24
Finished Aug 18 04:38:57 PM PDT 24
Peak memory 205220 kb
Host smart-e1cbaa1d-fa81-4525-8fc3-8c3f15d1fe4a
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=618029548 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_tl
_access.618029548
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_dmi_failed_op.2429967367
Short name T54
Test name
Test status
Simulation time 97692825 ps
CPU time 0.97 seconds
Started Aug 18 04:38:58 PM PDT 24
Finished Aug 18 04:38:59 PM PDT 24
Peak memory 204908 kb
Host smart-21952e09-a8cd-4f8c-9439-1113f394b0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429967367 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dmi_failed_op.2429967367
Directory /workspace/0.rv_dm_dmi_failed_op/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.301389115
Short name T8
Test name
Test status
Simulation time 540855012 ps
CPU time 2.28 seconds
Started Aug 18 04:38:59 PM PDT 24
Finished Aug 18 04:39:02 PM PDT 24
Peak memory 204908 kb
Host smart-51e19761-33f4-4fb0-86e3-86211914b59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301389115 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.301389115
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.1677945989
Short name T256
Test name
Test status
Simulation time 259018878 ps
CPU time 1.37 seconds
Started Aug 18 04:39:06 PM PDT 24
Finished Aug 18 04:39:07 PM PDT 24
Peak memory 204904 kb
Host smart-2a1a1f5b-87ee-429a-a8d4-6c77e8c6cf09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677945989 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.1677945989
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_hartsel_warl.2883902147
Short name T290
Test name
Test status
Simulation time 133969253 ps
CPU time 0.78 seconds
Started Aug 18 04:38:59 PM PDT 24
Finished Aug 18 04:39:00 PM PDT 24
Peak memory 204908 kb
Host smart-404a16cc-c525-4256-a77a-285f711e76e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883902147 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hartsel_warl_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hartsel_warl.2883902147
Directory /workspace/0.rv_dm_hartsel_warl/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.1915054807
Short name T177
Test name
Test status
Simulation time 343735473 ps
CPU time 0.97 seconds
Started Aug 18 04:38:58 PM PDT 24
Finished Aug 18 04:38:59 PM PDT 24
Peak memory 204836 kb
Host smart-93a874fa-9e80-43f0-81c6-fb1a3310c385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915054807 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.1915054807
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.4015791596
Short name T257
Test name
Test status
Simulation time 411307951 ps
CPU time 1.24 seconds
Started Aug 18 04:38:58 PM PDT 24
Finished Aug 18 04:39:00 PM PDT 24
Peak memory 205020 kb
Host smart-07551482-7d13-4df4-9696-67fc82b4de27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015791596 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.4015791596
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.771636903
Short name T234
Test name
Test status
Simulation time 211364395 ps
CPU time 0.97 seconds
Started Aug 18 04:38:59 PM PDT 24
Finished Aug 18 04:39:00 PM PDT 24
Peak memory 204780 kb
Host smart-3321e539-02e4-4ec1-ab2d-04ae2bb786c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771636903 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.771636903
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.2330121780
Short name T230
Test name
Test status
Simulation time 234977640 ps
CPU time 0.92 seconds
Started Aug 18 04:38:57 PM PDT 24
Finished Aug 18 04:38:58 PM PDT 24
Peak memory 204924 kb
Host smart-1e207c84-5de7-4847-b2e9-d5912c567718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330121780 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.2330121780
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.272245349
Short name T283
Test name
Test status
Simulation time 139336830 ps
CPU time 0.94 seconds
Started Aug 18 04:38:51 PM PDT 24
Finished Aug 18 04:38:53 PM PDT 24
Peak memory 204900 kb
Host smart-cd72ea58-fad2-4244-bbb2-eca67ab2d039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272245349 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.272245349
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.2897847175
Short name T228
Test name
Test status
Simulation time 185210343 ps
CPU time 0.78 seconds
Started Aug 18 04:38:49 PM PDT 24
Finished Aug 18 04:38:50 PM PDT 24
Peak memory 204864 kb
Host smart-916333dc-8d73-4fbb-8939-03b0d9f68ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897847175 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.2897847175
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.501639826
Short name T284
Test name
Test status
Simulation time 134240659 ps
CPU time 0.83 seconds
Started Aug 18 04:39:06 PM PDT 24
Finished Aug 18 04:39:07 PM PDT 24
Peak memory 213120 kb
Host smart-3ec578bd-029f-40a7-ad8f-4be8de35def2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501639826 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.501639826
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.2462451423
Short name T264
Test name
Test status
Simulation time 479974608 ps
CPU time 1 seconds
Started Aug 18 04:39:00 PM PDT 24
Finished Aug 18 04:39:02 PM PDT 24
Peak memory 204864 kb
Host smart-28c01557-fcf5-40bd-be32-3ce70e4ec52a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462451423 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.2462451423
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.3204395411
Short name T82
Test name
Test status
Simulation time 4871998527 ps
CPU time 12.86 seconds
Started Aug 18 04:38:49 PM PDT 24
Finished Aug 18 04:39:02 PM PDT 24
Peak memory 205496 kb
Host smart-6bc94564-2736-4be8-a394-de8e2090ea13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204395411 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.3204395411
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.1773678036
Short name T268
Test name
Test status
Simulation time 1916598561 ps
CPU time 3.4 seconds
Started Aug 18 04:38:51 PM PDT 24
Finished Aug 18 04:38:55 PM PDT 24
Peak memory 205092 kb
Host smart-8b8fc2e4-9f5a-436b-adb8-7bf822829cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773678036 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.1773678036
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/0.rv_dm_stress_all_with_rand_reset.1955981167
Short name T99
Test name
Test status
Simulation time 7596280738 ps
CPU time 32.07 seconds
Started Aug 18 04:39:00 PM PDT 24
Finished Aug 18 04:39:32 PM PDT 24
Peak memory 217444 kb
Host smart-e9c9cf4e-8fe4-46ce-b5bd-f2104a565294
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955981167 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all_with_rand_reset.1955981167
Directory /workspace/0.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rv_dm_abstractcmd_status.3178538323
Short name T51
Test name
Test status
Simulation time 126225577 ps
CPU time 0.81 seconds
Started Aug 18 04:39:11 PM PDT 24
Finished Aug 18 04:39:12 PM PDT 24
Peak memory 205024 kb
Host smart-47b37ccf-f9a6-4583-9271-9b3ab64022fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178538323 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.3178538323
Directory /workspace/1.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.2685116061
Short name T217
Test name
Test status
Simulation time 82959454 ps
CPU time 0.7 seconds
Started Aug 18 04:39:11 PM PDT 24
Finished Aug 18 04:39:12 PM PDT 24
Peak memory 205008 kb
Host smart-505e7bf4-580a-423f-b456-ebaa2a10619c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685116061 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.2685116061
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.541017513
Short name T1
Test name
Test status
Simulation time 37593285054 ps
CPU time 33.74 seconds
Started Aug 18 04:38:58 PM PDT 24
Finished Aug 18 04:39:32 PM PDT 24
Peak memory 217224 kb
Host smart-aee130c0-68bf-4a7b-95a0-e417b6768225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541017513 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.541017513
Directory /workspace/1.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.2910491619
Short name T303
Test name
Test status
Simulation time 3299888095 ps
CPU time 6.62 seconds
Started Aug 18 04:39:02 PM PDT 24
Finished Aug 18 04:39:08 PM PDT 24
Peak memory 213536 kb
Host smart-416bf72d-c146-492b-8d71-4d8028736b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910491619 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.2910491619
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_buffered_enable.3837031010
Short name T58
Test name
Test status
Simulation time 134801171 ps
CPU time 1.18 seconds
Started Aug 18 04:39:05 PM PDT 24
Finished Aug 18 04:39:07 PM PDT 24
Peak memory 226008 kb
Host smart-3ef1fde6-ed97-4b4d-83fc-5a4fc146a0a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837031010 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_buffered_enable.3837031010
Directory /workspace/1.rv_dm_buffered_enable/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.561197633
Short name T16
Test name
Test status
Simulation time 273468975 ps
CPU time 1.18 seconds
Started Aug 18 04:38:59 PM PDT 24
Finished Aug 18 04:39:00 PM PDT 24
Peak memory 204776 kb
Host smart-ca181e90-6f19-48f5-b7f2-6fa4d1afedb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561197633 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.561197633
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.2512369945
Short name T38
Test name
Test status
Simulation time 722970188 ps
CPU time 0.96 seconds
Started Aug 18 04:38:59 PM PDT 24
Finished Aug 18 04:39:00 PM PDT 24
Peak memory 204848 kb
Host smart-4abbb2d8-419c-4ef1-806b-6e571e36ecff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512369945 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.2512369945
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.1402004547
Short name T68
Test name
Test status
Simulation time 327692634 ps
CPU time 1.59 seconds
Started Aug 18 04:38:58 PM PDT 24
Finished Aug 18 04:39:00 PM PDT 24
Peak memory 204868 kb
Host smart-49726f8b-2bb9-4f94-9c5e-8f1f4af4ff20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402004547 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.1402004547
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.2515700408
Short name T187
Test name
Test status
Simulation time 268511603 ps
CPU time 1.02 seconds
Started Aug 18 04:38:59 PM PDT 24
Finished Aug 18 04:39:01 PM PDT 24
Peak memory 204928 kb
Host smart-e6538ae7-ddd3-45f0-97e4-a47ad5aaf637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515700408 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.2515700408
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_debug_disabled.3810390292
Short name T269
Test name
Test status
Simulation time 68302623 ps
CPU time 0.94 seconds
Started Aug 18 04:39:06 PM PDT 24
Finished Aug 18 04:39:07 PM PDT 24
Peak memory 214932 kb
Host smart-75e811a3-d99e-4791-95dc-56b233830d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810390292 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.3810390292
Directory /workspace/1.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.2824675820
Short name T308
Test name
Test status
Simulation time 1528105008 ps
CPU time 4.67 seconds
Started Aug 18 04:39:00 PM PDT 24
Finished Aug 18 04:39:04 PM PDT 24
Peak memory 205188 kb
Host smart-5e0c67ae-733e-4b6a-a51d-3363eecf0127
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2824675820 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t
l_access.2824675820
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_dmi_failed_op.1580664044
Short name T52
Test name
Test status
Simulation time 615023105 ps
CPU time 1.2 seconds
Started Aug 18 04:39:05 PM PDT 24
Finished Aug 18 04:39:06 PM PDT 24
Peak memory 204976 kb
Host smart-5343957d-0450-4435-84d0-62f19a6962e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580664044 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dmi_failed_op.1580664044
Directory /workspace/1.rv_dm_dmi_failed_op/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.2382859186
Short name T321
Test name
Test status
Simulation time 303162787 ps
CPU time 1.15 seconds
Started Aug 18 04:38:57 PM PDT 24
Finished Aug 18 04:38:59 PM PDT 24
Peak memory 204876 kb
Host smart-b36dfa8a-c653-4e14-91a0-56b1695a1cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382859186 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.2382859186
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.3083218638
Short name T306
Test name
Test status
Simulation time 80855148 ps
CPU time 0.69 seconds
Started Aug 18 04:38:58 PM PDT 24
Finished Aug 18 04:38:59 PM PDT 24
Peak memory 204836 kb
Host smart-f415c512-6365-46d6-aec2-efd5b2ca796f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083218638 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.3083218638
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.3036585479
Short name T315
Test name
Test status
Simulation time 671892833 ps
CPU time 1.92 seconds
Started Aug 18 04:39:11 PM PDT 24
Finished Aug 18 04:39:13 PM PDT 24
Peak memory 205008 kb
Host smart-cacb16ee-873a-4e58-aef7-8486b3f0ada6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036585479 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.3036585479
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.1702418805
Short name T253
Test name
Test status
Simulation time 415958288 ps
CPU time 1.84 seconds
Started Aug 18 04:38:58 PM PDT 24
Finished Aug 18 04:39:00 PM PDT 24
Peak memory 204900 kb
Host smart-807dd867-3834-414e-96ce-c4d775caa091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702418805 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.1702418805
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.921811947
Short name T29
Test name
Test status
Simulation time 295710328 ps
CPU time 0.84 seconds
Started Aug 18 04:38:57 PM PDT 24
Finished Aug 18 04:38:58 PM PDT 24
Peak memory 204872 kb
Host smart-b096a129-ca91-43d6-a4a4-a38ac3fcc51d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921811947 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.921811947
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.2781409927
Short name T291
Test name
Test status
Simulation time 158527268 ps
CPU time 0.77 seconds
Started Aug 18 04:39:03 PM PDT 24
Finished Aug 18 04:39:04 PM PDT 24
Peak memory 204908 kb
Host smart-bc51be49-4420-4e4a-b9a6-a4191c1d19a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781409927 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.2781409927
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.3482585398
Short name T186
Test name
Test status
Simulation time 189848540 ps
CPU time 0.92 seconds
Started Aug 18 04:39:03 PM PDT 24
Finished Aug 18 04:39:04 PM PDT 24
Peak memory 204908 kb
Host smart-7055aff8-76b4-4e53-a6f0-049f840268a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482585398 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.3482585398
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.4234801750
Short name T148
Test name
Test status
Simulation time 263273312 ps
CPU time 1.06 seconds
Started Aug 18 04:38:59 PM PDT 24
Finished Aug 18 04:39:00 PM PDT 24
Peak memory 213136 kb
Host smart-c03820e0-c479-4fc2-ba5a-d478eb6fb17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234801750 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.4234801750
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.3721910312
Short name T313
Test name
Test status
Simulation time 1209467886 ps
CPU time 1.29 seconds
Started Aug 18 04:39:05 PM PDT 24
Finished Aug 18 04:39:07 PM PDT 24
Peak memory 204900 kb
Host smart-5abafa9a-4bcd-4155-8cf8-567ffc53167b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721910312 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.3721910312
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.639737881
Short name T41
Test name
Test status
Simulation time 124469258 ps
CPU time 0.83 seconds
Started Aug 18 04:39:06 PM PDT 24
Finished Aug 18 04:39:07 PM PDT 24
Peak memory 213176 kb
Host smart-040c28d3-cdfa-4875-b41d-4102115f3aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639737881 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.639737881
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_sba_debug_disabled.3333730245
Short name T152
Test name
Test status
Simulation time 2790394935 ps
CPU time 7.21 seconds
Started Aug 18 04:38:59 PM PDT 24
Finished Aug 18 04:39:06 PM PDT 24
Peak memory 205236 kb
Host smart-f9b64fa2-3104-4baa-b0e4-cdf50b58c44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333730245 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.3333730245
Directory /workspace/1.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.2368099641
Short name T322
Test name
Test status
Simulation time 3869326870 ps
CPU time 3.55 seconds
Started Aug 18 04:39:00 PM PDT 24
Finished Aug 18 04:39:04 PM PDT 24
Peak memory 205340 kb
Host smart-8f54ca92-daf5-4ba3-a6cb-bb3e1aef207c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368099641 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.2368099641
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.2379048408
Short name T35
Test name
Test status
Simulation time 678263269 ps
CPU time 1.15 seconds
Started Aug 18 04:39:12 PM PDT 24
Finished Aug 18 04:39:13 PM PDT 24
Peak memory 229620 kb
Host smart-47660896-3c6e-4b99-b9b2-f52c023e7361
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379048408 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.2379048408
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.2282506945
Short name T318
Test name
Test status
Simulation time 701243341 ps
CPU time 1.79 seconds
Started Aug 18 04:38:57 PM PDT 24
Finished Aug 18 04:38:59 PM PDT 24
Peak memory 204860 kb
Host smart-ea337c4e-3e55-462b-836f-267f2ff88268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282506945 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.2282506945
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/1.rv_dm_sparse_lc_gate_fsm.3410727372
Short name T57
Test name
Test status
Simulation time 90319083 ps
CPU time 0.8 seconds
Started Aug 18 04:39:05 PM PDT 24
Finished Aug 18 04:39:06 PM PDT 24
Peak memory 213256 kb
Host smart-f69ec585-83b4-4345-b774-a5a7804bce83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410727372 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sparse_lc_gate_fsm.3410727372
Directory /workspace/1.rv_dm_sparse_lc_gate_fsm/latest

Test location /workspace/coverage/default/1.rv_dm_stress_all.2922761064
Short name T20
Test name
Test status
Simulation time 6211912286 ps
CPU time 18.99 seconds
Started Aug 18 04:39:10 PM PDT 24
Finished Aug 18 04:39:30 PM PDT 24
Peak memory 213468 kb
Host smart-9a239432-8cbd-4c7f-bfb7-bcc89e0990af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922761064 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.2922761064
Directory /workspace/1.rv_dm_stress_all/latest

Test location /workspace/coverage/default/1.rv_dm_stress_all_with_rand_reset.4240774432
Short name T47
Test name
Test status
Simulation time 4041164827 ps
CPU time 65.92 seconds
Started Aug 18 04:39:06 PM PDT 24
Finished Aug 18 04:40:12 PM PDT 24
Peak memory 218304 kb
Host smart-22109d4a-9825-4bc6-9ef9-7514273fac46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240774432 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all_with_rand_reset.4240774432
Directory /workspace/1.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.154867665
Short name T229
Test name
Test status
Simulation time 30792150 ps
CPU time 0.78 seconds
Started Aug 18 04:39:32 PM PDT 24
Finished Aug 18 04:39:33 PM PDT 24
Peak memory 204992 kb
Host smart-a2ee272f-030b-4600-a6fa-3d862bca8703
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154867665 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.154867665
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.3351085511
Short name T305
Test name
Test status
Simulation time 1369295667 ps
CPU time 2.35 seconds
Started Aug 18 04:39:36 PM PDT 24
Finished Aug 18 04:39:38 PM PDT 24
Peak memory 205404 kb
Host smart-fb15fc63-fa37-4902-8ab9-168aeb3ffcf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351085511 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.3351085511
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.2669801726
Short name T220
Test name
Test status
Simulation time 11778151297 ps
CPU time 32.13 seconds
Started Aug 18 04:39:34 PM PDT 24
Finished Aug 18 04:40:07 PM PDT 24
Peak memory 205296 kb
Host smart-04e2a467-c9cf-4108-a3ca-2fa5acb80f13
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2669801726 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_
tl_access.2669801726
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.1566028282
Short name T2
Test name
Test status
Simulation time 953386399 ps
CPU time 3.56 seconds
Started Aug 18 04:39:31 PM PDT 24
Finished Aug 18 04:39:35 PM PDT 24
Peak memory 205336 kb
Host smart-9451b4f6-1eb1-49f2-9605-3e265e2e21a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566028282 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.1566028282
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_stress_all.2675225630
Short name T261
Test name
Test status
Simulation time 6227880071 ps
CPU time 6.07 seconds
Started Aug 18 04:39:33 PM PDT 24
Finished Aug 18 04:39:40 PM PDT 24
Peak memory 205176 kb
Host smart-b7fce8dc-fb5e-41bc-a508-a3c0ac44676c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675225630 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.2675225630
Directory /workspace/10.rv_dm_stress_all/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.1475261845
Short name T309
Test name
Test status
Simulation time 121868382 ps
CPU time 0.7 seconds
Started Aug 18 04:39:33 PM PDT 24
Finished Aug 18 04:39:34 PM PDT 24
Peak memory 204904 kb
Host smart-2738089d-20c2-4905-9303-70d13b65cdc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475261845 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.1475261845
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.291354211
Short name T209
Test name
Test status
Simulation time 11703434246 ps
CPU time 12.03 seconds
Started Aug 18 04:39:35 PM PDT 24
Finished Aug 18 04:39:48 PM PDT 24
Peak memory 215288 kb
Host smart-aa334c25-6253-432d-90db-d4113fd553d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291354211 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.291354211
Directory /workspace/11.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.2910806596
Short name T216
Test name
Test status
Simulation time 2013008480 ps
CPU time 3.98 seconds
Started Aug 18 04:39:32 PM PDT 24
Finished Aug 18 04:39:36 PM PDT 24
Peak memory 213412 kb
Host smart-70e1eb38-4f9c-44ac-a2be-22cfbeccfa26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910806596 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.2910806596
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.52182919
Short name T265
Test name
Test status
Simulation time 1331088417 ps
CPU time 4.68 seconds
Started Aug 18 04:39:34 PM PDT 24
Finished Aug 18 04:39:39 PM PDT 24
Peak memory 205428 kb
Host smart-0e25bc78-f679-48f8-aef7-fc7dc9a21877
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=52182919 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_tl
_access.52182919
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.2197632431
Short name T271
Test name
Test status
Simulation time 4286109483 ps
CPU time 4.49 seconds
Started Aug 18 04:39:32 PM PDT 24
Finished Aug 18 04:39:36 PM PDT 24
Peak memory 205300 kb
Host smart-702688bb-5962-4743-a265-fcaf96d0c340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197632431 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.2197632431
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_stress_all.3209756844
Short name T30
Test name
Test status
Simulation time 4109413441 ps
CPU time 2.05 seconds
Started Aug 18 04:39:35 PM PDT 24
Finished Aug 18 04:39:38 PM PDT 24
Peak memory 213304 kb
Host smart-0861bc53-a03f-4513-a269-094e996f159b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209756844 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.3209756844
Directory /workspace/11.rv_dm_stress_all/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.850632912
Short name T316
Test name
Test status
Simulation time 129058635 ps
CPU time 0.76 seconds
Started Aug 18 04:39:39 PM PDT 24
Finished Aug 18 04:39:40 PM PDT 24
Peak memory 205016 kb
Host smart-66d4dad7-4302-4601-b2c7-00e9aafb78b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850632912 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.850632912
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.1689758253
Short name T96
Test name
Test status
Simulation time 14151157380 ps
CPU time 21.28 seconds
Started Aug 18 04:39:42 PM PDT 24
Finished Aug 18 04:40:04 PM PDT 24
Peak memory 213472 kb
Host smart-b941d5c6-a360-4547-9ab8-7cfb4aa68a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689758253 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.1689758253
Directory /workspace/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.4106103469
Short name T166
Test name
Test status
Simulation time 7458189238 ps
CPU time 18.88 seconds
Started Aug 18 04:39:42 PM PDT 24
Finished Aug 18 04:40:01 PM PDT 24
Peak memory 213508 kb
Host smart-7c455fa9-aa4a-49a6-ad9d-f395af737a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106103469 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.4106103469
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.3167660192
Short name T214
Test name
Test status
Simulation time 9575281551 ps
CPU time 27.02 seconds
Started Aug 18 04:39:31 PM PDT 24
Finished Aug 18 04:39:58 PM PDT 24
Peak memory 213556 kb
Host smart-7938062b-eece-4e41-a1f5-2d53676ea098
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3167660192 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_
tl_access.3167660192
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.3042109610
Short name T240
Test name
Test status
Simulation time 5608080752 ps
CPU time 9.05 seconds
Started Aug 18 04:39:33 PM PDT 24
Finished Aug 18 04:39:43 PM PDT 24
Peak memory 205088 kb
Host smart-25f789ed-f9c1-4748-ad9e-3fd99b843f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042109610 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.3042109610
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_stress_all.3655410297
Short name T189
Test name
Test status
Simulation time 1660351994 ps
CPU time 5.01 seconds
Started Aug 18 04:39:44 PM PDT 24
Finished Aug 18 04:39:49 PM PDT 24
Peak memory 205172 kb
Host smart-eaeb1f02-7206-4c90-a517-a386d95e477d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655410297 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.3655410297
Directory /workspace/12.rv_dm_stress_all/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.3682015660
Short name T75
Test name
Test status
Simulation time 46564879 ps
CPU time 0.73 seconds
Started Aug 18 04:39:42 PM PDT 24
Finished Aug 18 04:39:43 PM PDT 24
Peak memory 205008 kb
Host smart-4240c982-9cea-41a8-89c6-48451b074bb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682015660 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.3682015660
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.427388736
Short name T66
Test name
Test status
Simulation time 5382831158 ps
CPU time 10.4 seconds
Started Aug 18 04:39:43 PM PDT 24
Finished Aug 18 04:39:53 PM PDT 24
Peak memory 213696 kb
Host smart-8a2b5afb-5b5e-4c18-b189-3293730efc17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427388736 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.427388736
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.2619630624
Short name T170
Test name
Test status
Simulation time 1978223339 ps
CPU time 2.81 seconds
Started Aug 18 04:39:41 PM PDT 24
Finished Aug 18 04:39:44 PM PDT 24
Peak memory 213432 kb
Host smart-a7023dff-7c89-4bc3-b8a1-6998e27de566
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2619630624 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_
tl_access.2619630624
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.867521194
Short name T255
Test name
Test status
Simulation time 8849222325 ps
CPU time 7.67 seconds
Started Aug 18 04:39:39 PM PDT 24
Finished Aug 18 04:39:47 PM PDT 24
Peak memory 205404 kb
Host smart-28c64ac6-7e83-40e5-8df4-1b5312b75f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867521194 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.867521194
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_stress_all.2208975270
Short name T11
Test name
Test status
Simulation time 4161828404 ps
CPU time 11.83 seconds
Started Aug 18 04:39:42 PM PDT 24
Finished Aug 18 04:39:54 PM PDT 24
Peak memory 205244 kb
Host smart-67922a66-06d0-40da-9a46-1a0c54323b80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208975270 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.2208975270
Directory /workspace/13.rv_dm_stress_all/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.4203517914
Short name T72
Test name
Test status
Simulation time 149643034 ps
CPU time 0.73 seconds
Started Aug 18 04:39:40 PM PDT 24
Finished Aug 18 04:39:41 PM PDT 24
Peak memory 204912 kb
Host smart-5d41984a-f0b7-44da-bfae-aabd1d06c991
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203517914 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.4203517914
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.1743432020
Short name T203
Test name
Test status
Simulation time 13550575503 ps
CPU time 17.25 seconds
Started Aug 18 04:39:44 PM PDT 24
Finished Aug 18 04:40:01 PM PDT 24
Peak memory 215272 kb
Host smart-9d323ac4-e0a2-4ecb-b6ce-e0779473621f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743432020 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.1743432020
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.4165499320
Short name T175
Test name
Test status
Simulation time 1595533989 ps
CPU time 3 seconds
Started Aug 18 04:39:41 PM PDT 24
Finished Aug 18 04:39:45 PM PDT 24
Peak memory 205612 kb
Host smart-4eeaa97d-88f2-45dd-8ea5-1bb019ee74a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165499320 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.4165499320
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.3537125489
Short name T97
Test name
Test status
Simulation time 1826671359 ps
CPU time 2.57 seconds
Started Aug 18 04:39:40 PM PDT 24
Finished Aug 18 04:39:42 PM PDT 24
Peak memory 205260 kb
Host smart-95199e9a-2bb1-497d-a4ab-ec200e649935
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3537125489 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_
tl_access.3537125489
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.2652290187
Short name T3
Test name
Test status
Simulation time 1307294100 ps
CPU time 4.33 seconds
Started Aug 18 04:39:39 PM PDT 24
Finished Aug 18 04:39:44 PM PDT 24
Peak memory 205168 kb
Host smart-5113ebeb-b9ec-4d04-ab6d-cfacdbbca302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652290187 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.2652290187
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.1547444304
Short name T193
Test name
Test status
Simulation time 116038802 ps
CPU time 0.98 seconds
Started Aug 18 04:39:42 PM PDT 24
Finished Aug 18 04:39:43 PM PDT 24
Peak memory 204912 kb
Host smart-a3a2e31e-0c21-479a-85ae-b23d7e0debd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547444304 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.1547444304
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.3388486430
Short name T196
Test name
Test status
Simulation time 50940381001 ps
CPU time 75.17 seconds
Started Aug 18 04:39:41 PM PDT 24
Finished Aug 18 04:40:56 PM PDT 24
Peak memory 213576 kb
Host smart-4325242f-92a7-4ae0-a14a-aebe8833aeda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388486430 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.3388486430
Directory /workspace/15.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.3576348614
Short name T154
Test name
Test status
Simulation time 3446025540 ps
CPU time 9.51 seconds
Started Aug 18 04:39:42 PM PDT 24
Finished Aug 18 04:39:51 PM PDT 24
Peak memory 213596 kb
Host smart-b5a7c56e-71ca-4c4a-9ea8-72412dcec716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576348614 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.3576348614
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.2608886231
Short name T275
Test name
Test status
Simulation time 11457904550 ps
CPU time 3.75 seconds
Started Aug 18 04:39:45 PM PDT 24
Finished Aug 18 04:39:49 PM PDT 24
Peak memory 213580 kb
Host smart-3d7281bc-a7ca-4843-9fbf-36af9f017cd0
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2608886231 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_
tl_access.2608886231
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.3499549503
Short name T215
Test name
Test status
Simulation time 6202024033 ps
CPU time 9.26 seconds
Started Aug 18 04:39:41 PM PDT 24
Finished Aug 18 04:39:51 PM PDT 24
Peak memory 213728 kb
Host smart-957a17aa-db28-41c1-8115-d48be6d76569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499549503 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.3499549503
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_stress_all.2567355465
Short name T293
Test name
Test status
Simulation time 2060510962 ps
CPU time 4.48 seconds
Started Aug 18 04:39:39 PM PDT 24
Finished Aug 18 04:39:44 PM PDT 24
Peak memory 213356 kb
Host smart-48611fb7-64d1-4484-b671-4c108901bc1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567355465 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.2567355465
Directory /workspace/15.rv_dm_stress_all/latest

Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.3372561018
Short name T213
Test name
Test status
Simulation time 7971571190 ps
CPU time 8.56 seconds
Started Aug 18 04:39:44 PM PDT 24
Finished Aug 18 04:39:53 PM PDT 24
Peak memory 213556 kb
Host smart-f519fabf-d111-46e0-abbc-7555aa7b5f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372561018 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.3372561018
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.1706400566
Short name T231
Test name
Test status
Simulation time 2459106001 ps
CPU time 4.09 seconds
Started Aug 18 04:39:39 PM PDT 24
Finished Aug 18 04:39:43 PM PDT 24
Peak memory 213548 kb
Host smart-9cc946f4-b478-4fec-a1b5-10d9fd3ce32c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706400566 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.1706400566
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.2627574026
Short name T147
Test name
Test status
Simulation time 13392610001 ps
CPU time 35.63 seconds
Started Aug 18 04:39:39 PM PDT 24
Finished Aug 18 04:40:15 PM PDT 24
Peak memory 213576 kb
Host smart-f9b177e7-ad16-4395-84be-a4d46eee46d0
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2627574026 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_
tl_access.2627574026
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.3159069048
Short name T304
Test name
Test status
Simulation time 5705923996 ps
CPU time 8.04 seconds
Started Aug 18 04:39:40 PM PDT 24
Finished Aug 18 04:39:48 PM PDT 24
Peak memory 205380 kb
Host smart-da8cb266-d59e-4419-9c90-2fd9c850b7bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159069048 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.3159069048
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_stress_all.1113441296
Short name T164
Test name
Test status
Simulation time 4595772404 ps
CPU time 11.43 seconds
Started Aug 18 04:39:42 PM PDT 24
Finished Aug 18 04:39:54 PM PDT 24
Peak memory 205268 kb
Host smart-d8bbefa4-6a00-4a4b-8799-aeab98d0a2e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113441296 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.1113441296
Directory /workspace/16.rv_dm_stress_all/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.1178182690
Short name T232
Test name
Test status
Simulation time 106483440 ps
CPU time 0.78 seconds
Started Aug 18 04:39:42 PM PDT 24
Finished Aug 18 04:39:43 PM PDT 24
Peak memory 204856 kb
Host smart-422fa430-5410-4ccd-8860-d33a5d915758
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178182690 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.1178182690
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.1372900708
Short name T165
Test name
Test status
Simulation time 88638713806 ps
CPU time 129 seconds
Started Aug 18 04:39:42 PM PDT 24
Finished Aug 18 04:41:51 PM PDT 24
Peak memory 213604 kb
Host smart-5639dec1-0411-4a4a-9d36-5ec369e536ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372900708 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.1372900708
Directory /workspace/17.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.1385011559
Short name T243
Test name
Test status
Simulation time 1962690624 ps
CPU time 2.66 seconds
Started Aug 18 04:39:41 PM PDT 24
Finished Aug 18 04:39:43 PM PDT 24
Peak memory 205436 kb
Host smart-9b878d37-0aef-4125-92e4-50d7bab3080b
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1385011559 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_
tl_access.1385011559
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.715485460
Short name T310
Test name
Test status
Simulation time 1818039626 ps
CPU time 3.5 seconds
Started Aug 18 04:39:42 PM PDT 24
Finished Aug 18 04:39:45 PM PDT 24
Peak memory 205392 kb
Host smart-72e61db4-b773-47d9-9918-fc81ff3a37f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715485460 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.715485460
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_stress_all.3254926821
Short name T288
Test name
Test status
Simulation time 3152649879 ps
CPU time 9.56 seconds
Started Aug 18 04:39:43 PM PDT 24
Finished Aug 18 04:39:53 PM PDT 24
Peak memory 205280 kb
Host smart-78738d4c-1c16-4532-9b0e-fa5ea3a1ab70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254926821 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.3254926821
Directory /workspace/17.rv_dm_stress_all/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.2289289446
Short name T33
Test name
Test status
Simulation time 195722575 ps
CPU time 0.82 seconds
Started Aug 18 04:39:45 PM PDT 24
Finished Aug 18 04:39:46 PM PDT 24
Peak memory 204904 kb
Host smart-3197a30c-f9ac-4562-bb92-cb95fa23f3bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289289446 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.2289289446
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.128631985
Short name T172
Test name
Test status
Simulation time 1403454518 ps
CPU time 3.08 seconds
Started Aug 18 04:39:43 PM PDT 24
Finished Aug 18 04:39:46 PM PDT 24
Peak memory 205292 kb
Host smart-267a13a4-3133-46a2-8bbc-666c4ca131b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128631985 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.128631985
Directory /workspace/18.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.1741521715
Short name T153
Test name
Test status
Simulation time 1397679742 ps
CPU time 4.69 seconds
Started Aug 18 04:39:43 PM PDT 24
Finished Aug 18 04:39:48 PM PDT 24
Peak memory 213572 kb
Host smart-d12e741c-a2a8-4b3c-9ae0-0bcb541e6380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741521715 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.1741521715
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.2919283552
Short name T173
Test name
Test status
Simulation time 9262064221 ps
CPU time 7.42 seconds
Started Aug 18 04:39:40 PM PDT 24
Finished Aug 18 04:39:47 PM PDT 24
Peak memory 213676 kb
Host smart-2cf58752-f809-4372-a1d9-e16adaccd218
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2919283552 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_
tl_access.2919283552
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.3771078195
Short name T239
Test name
Test status
Simulation time 4845361064 ps
CPU time 7.14 seconds
Started Aug 18 04:39:41 PM PDT 24
Finished Aug 18 04:39:49 PM PDT 24
Peak memory 205516 kb
Host smart-cf355760-7800-4fc2-b16b-d19f6d2c6bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771078195 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.3771078195
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.959058698
Short name T225
Test name
Test status
Simulation time 66420567 ps
CPU time 0.83 seconds
Started Aug 18 04:39:43 PM PDT 24
Finished Aug 18 04:39:45 PM PDT 24
Peak memory 205020 kb
Host smart-7124d069-3b8c-44f8-83e1-8bc8e7b47587
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959058698 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.959058698
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.3576823486
Short name T320
Test name
Test status
Simulation time 47853051063 ps
CPU time 70 seconds
Started Aug 18 04:39:42 PM PDT 24
Finished Aug 18 04:40:52 PM PDT 24
Peak memory 205356 kb
Host smart-710d5a50-c1a1-4c08-a54c-bf7f2d621daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576823486 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.3576823486
Directory /workspace/19.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.1220853846
Short name T245
Test name
Test status
Simulation time 2437358447 ps
CPU time 4.78 seconds
Started Aug 18 04:39:41 PM PDT 24
Finished Aug 18 04:39:46 PM PDT 24
Peak memory 205472 kb
Host smart-14fe1f4e-1e65-49b4-8f5e-7d116c01f249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220853846 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.1220853846
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.3062253306
Short name T292
Test name
Test status
Simulation time 5672736468 ps
CPU time 4.95 seconds
Started Aug 18 04:39:43 PM PDT 24
Finished Aug 18 04:39:48 PM PDT 24
Peak memory 213600 kb
Host smart-7a0fada0-db3a-4fb8-b5f5-dbd955bdc97f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3062253306 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_
tl_access.3062253306
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.1107231650
Short name T248
Test name
Test status
Simulation time 6808673952 ps
CPU time 11.96 seconds
Started Aug 18 04:39:41 PM PDT 24
Finished Aug 18 04:39:53 PM PDT 24
Peak memory 213556 kb
Host smart-d3158cfa-3bb4-42bb-95ba-91a65a7cb67b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107231650 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.1107231650
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_stress_all.2180754269
Short name T294
Test name
Test status
Simulation time 3001050981 ps
CPU time 8.91 seconds
Started Aug 18 04:39:40 PM PDT 24
Finished Aug 18 04:39:49 PM PDT 24
Peak memory 205276 kb
Host smart-78ca2f01-80a4-4c78-8825-fa3cfc7d2e0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180754269 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.2180754269
Directory /workspace/19.rv_dm_stress_all/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.3558199393
Short name T281
Test name
Test status
Simulation time 152406435 ps
CPU time 0.74 seconds
Started Aug 18 04:39:20 PM PDT 24
Finished Aug 18 04:39:21 PM PDT 24
Peak memory 204996 kb
Host smart-66b05e0e-4604-4cd9-99b2-ed301a422760
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558199393 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.3558199393
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.2304893550
Short name T224
Test name
Test status
Simulation time 5560766690 ps
CPU time 11.77 seconds
Started Aug 18 04:39:05 PM PDT 24
Finished Aug 18 04:39:17 PM PDT 24
Peak memory 213652 kb
Host smart-aa64a73b-2650-438d-b558-a0aeb7c5ebf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304893550 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.2304893550
Directory /workspace/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.3253039341
Short name T259
Test name
Test status
Simulation time 4758456572 ps
CPU time 14.06 seconds
Started Aug 18 04:39:07 PM PDT 24
Finished Aug 18 04:39:21 PM PDT 24
Peak memory 213716 kb
Host smart-98edbc0a-9b82-4675-ad65-fdba0ae6bf7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253039341 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.3253039341
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.2864617935
Short name T98
Test name
Test status
Simulation time 3393937910 ps
CPU time 2.31 seconds
Started Aug 18 04:39:05 PM PDT 24
Finished Aug 18 04:39:07 PM PDT 24
Peak memory 205424 kb
Host smart-416ac562-e8c8-4a9c-80c4-924ef8360d80
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2864617935 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t
l_access.2864617935
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_halt_resume_whereto.2472286179
Short name T43
Test name
Test status
Simulation time 568738055 ps
CPU time 1.48 seconds
Started Aug 18 04:39:06 PM PDT 24
Finished Aug 18 04:39:08 PM PDT 24
Peak memory 204908 kb
Host smart-87859299-f1db-4438-a450-27ca702e68c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472286179 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_halt_resume_whereto.2472286179
Directory /workspace/2.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.1301165448
Short name T274
Test name
Test status
Simulation time 121252071 ps
CPU time 0.77 seconds
Started Aug 18 04:39:07 PM PDT 24
Finished Aug 18 04:39:08 PM PDT 24
Peak memory 204884 kb
Host smart-a1717e2e-74e2-4a0e-8ccc-51e432312e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301165448 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.1301165448
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.604563650
Short name T250
Test name
Test status
Simulation time 6020836776 ps
CPU time 11.33 seconds
Started Aug 18 04:39:07 PM PDT 24
Finished Aug 18 04:39:18 PM PDT 24
Peak memory 213524 kb
Host smart-147feedb-0151-4520-9659-f99463ec69c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604563650 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.604563650
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.1171386220
Short name T62
Test name
Test status
Simulation time 225342669 ps
CPU time 1.25 seconds
Started Aug 18 04:39:17 PM PDT 24
Finished Aug 18 04:39:18 PM PDT 24
Peak memory 229560 kb
Host smart-2950739d-83e9-446f-aa3b-868fb7e0af78
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171386220 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.1171386220
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/2.rv_dm_sparse_lc_gate_fsm.3330184140
Short name T36
Test name
Test status
Simulation time 144560477 ps
CPU time 0.85 seconds
Started Aug 18 04:39:05 PM PDT 24
Finished Aug 18 04:39:06 PM PDT 24
Peak memory 213360 kb
Host smart-d7d0a88c-b8ac-4cb0-a552-069a7cb7ea19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330184140 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sparse_lc_gate_fsm.3330184140
Directory /workspace/2.rv_dm_sparse_lc_gate_fsm/latest

Test location /workspace/coverage/default/2.rv_dm_stress_all.3110033793
Short name T298
Test name
Test status
Simulation time 5285240428 ps
CPU time 6.56 seconds
Started Aug 18 04:39:05 PM PDT 24
Finished Aug 18 04:39:12 PM PDT 24
Peak memory 205276 kb
Host smart-fdbeaa75-0c11-4e03-a410-ac5b9b230abb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110033793 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.3110033793
Directory /workspace/2.rv_dm_stress_all/latest

Test location /workspace/coverage/default/2.rv_dm_stress_all_with_rand_reset.3049732613
Short name T12
Test name
Test status
Simulation time 11108594665 ps
CPU time 73.42 seconds
Started Aug 18 04:39:15 PM PDT 24
Finished Aug 18 04:40:28 PM PDT 24
Peak memory 217524 kb
Host smart-9e479cde-a080-46db-85f0-92ace26dc91e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049732613 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all_with_rand_reset.3049732613
Directory /workspace/2.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.1073003670
Short name T249
Test name
Test status
Simulation time 84142453 ps
CPU time 0.79 seconds
Started Aug 18 04:39:42 PM PDT 24
Finished Aug 18 04:39:43 PM PDT 24
Peak memory 205248 kb
Host smart-aa703268-560c-42e4-9f17-ad011c0d2622
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073003670 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.1073003670
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/20.rv_dm_stress_all.3357529496
Short name T24
Test name
Test status
Simulation time 6795414025 ps
CPU time 6.27 seconds
Started Aug 18 04:39:39 PM PDT 24
Finished Aug 18 04:39:45 PM PDT 24
Peak memory 205128 kb
Host smart-ca865746-07c4-4146-9bc6-8bdfb3699e99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357529496 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.3357529496
Directory /workspace/20.rv_dm_stress_all/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.2214152419
Short name T319
Test name
Test status
Simulation time 154257940 ps
CPU time 0.77 seconds
Started Aug 18 04:39:45 PM PDT 24
Finished Aug 18 04:39:46 PM PDT 24
Peak memory 204880 kb
Host smart-dce5e75c-5c21-48c7-9813-23a8ac7b3f27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214152419 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.2214152419
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_stress_all.2992061128
Short name T61
Test name
Test status
Simulation time 2535820770 ps
CPU time 2.48 seconds
Started Aug 18 04:39:39 PM PDT 24
Finished Aug 18 04:39:42 PM PDT 24
Peak memory 213456 kb
Host smart-5f9787a2-0472-4202-a466-07e41b8330a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992061128 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.2992061128
Directory /workspace/21.rv_dm_stress_all/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.3664176307
Short name T202
Test name
Test status
Simulation time 117983366 ps
CPU time 0.7 seconds
Started Aug 18 04:39:40 PM PDT 24
Finished Aug 18 04:39:41 PM PDT 24
Peak memory 205004 kb
Host smart-9ace8527-884c-423b-bce8-8e182e73f125
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664176307 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.3664176307
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_stress_all.390147768
Short name T6
Test name
Test status
Simulation time 4417688183 ps
CPU time 4.27 seconds
Started Aug 18 04:39:41 PM PDT 24
Finished Aug 18 04:39:46 PM PDT 24
Peak memory 205300 kb
Host smart-43744ac0-aacc-4e05-9d04-a116723ab5ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390147768 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.390147768
Directory /workspace/22.rv_dm_stress_all/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.1216233077
Short name T208
Test name
Test status
Simulation time 53141371 ps
CPU time 0.73 seconds
Started Aug 18 04:39:43 PM PDT 24
Finished Aug 18 04:39:45 PM PDT 24
Peak memory 205012 kb
Host smart-9d7f74c5-70fc-44b9-8f2b-4aee9724b694
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216233077 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.1216233077
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_stress_all.2692223502
Short name T238
Test name
Test status
Simulation time 3468716097 ps
CPU time 6.28 seconds
Started Aug 18 04:39:42 PM PDT 24
Finished Aug 18 04:39:48 PM PDT 24
Peak memory 205172 kb
Host smart-df4962dc-457e-4e50-9083-3de38433a969
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692223502 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.2692223502
Directory /workspace/23.rv_dm_stress_all/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.2269818463
Short name T192
Test name
Test status
Simulation time 59067324 ps
CPU time 0.75 seconds
Started Aug 18 04:39:41 PM PDT 24
Finished Aug 18 04:39:42 PM PDT 24
Peak memory 204984 kb
Host smart-271a1c12-1aca-47a3-b0c3-6d6b99226015
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269818463 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.2269818463
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_stress_all.1185258902
Short name T15
Test name
Test status
Simulation time 2767047697 ps
CPU time 2.56 seconds
Started Aug 18 04:39:44 PM PDT 24
Finished Aug 18 04:39:47 PM PDT 24
Peak memory 205096 kb
Host smart-c3c9f542-8878-4825-84fe-9540c9a6a10f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185258902 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.1185258902
Directory /workspace/24.rv_dm_stress_all/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.3420725879
Short name T300
Test name
Test status
Simulation time 165942129 ps
CPU time 0.8 seconds
Started Aug 18 04:39:42 PM PDT 24
Finished Aug 18 04:39:43 PM PDT 24
Peak memory 204860 kb
Host smart-122a65b6-20cd-4ee2-81a2-521274e9f2af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420725879 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.3420725879
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_stress_all.1991467990
Short name T42
Test name
Test status
Simulation time 2550434427 ps
CPU time 4.6 seconds
Started Aug 18 04:39:40 PM PDT 24
Finished Aug 18 04:39:45 PM PDT 24
Peak memory 205176 kb
Host smart-cfd25b58-3ba5-4a0f-b994-eff13adf9f6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991467990 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.1991467990
Directory /workspace/25.rv_dm_stress_all/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.643788399
Short name T267
Test name
Test status
Simulation time 107301467 ps
CPU time 0.92 seconds
Started Aug 18 04:39:41 PM PDT 24
Finished Aug 18 04:39:43 PM PDT 24
Peak memory 204896 kb
Host smart-05e0c4c8-29a5-4638-9392-de1a0e198015
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643788399 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.643788399
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_stress_all.3317376646
Short name T9
Test name
Test status
Simulation time 2760175058 ps
CPU time 8.09 seconds
Started Aug 18 04:39:41 PM PDT 24
Finished Aug 18 04:39:49 PM PDT 24
Peak memory 213436 kb
Host smart-c6a380cd-b979-4e92-ab59-a5cd251905fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317376646 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.3317376646
Directory /workspace/26.rv_dm_stress_all/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.3881884683
Short name T211
Test name
Test status
Simulation time 56812206 ps
CPU time 0.77 seconds
Started Aug 18 04:39:42 PM PDT 24
Finished Aug 18 04:39:43 PM PDT 24
Peak memory 204912 kb
Host smart-78394035-7674-44ce-9a6e-e38b76699f7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881884683 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.3881884683
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_stress_all.3837192362
Short name T44
Test name
Test status
Simulation time 2222193309 ps
CPU time 6.67 seconds
Started Aug 18 04:39:44 PM PDT 24
Finished Aug 18 04:39:51 PM PDT 24
Peak memory 213332 kb
Host smart-1ecb0787-3a05-46f0-a2ca-1f006dba5fe5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837192362 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.3837192362
Directory /workspace/27.rv_dm_stress_all/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.3729106799
Short name T31
Test name
Test status
Simulation time 44526493 ps
CPU time 0.79 seconds
Started Aug 18 04:39:43 PM PDT 24
Finished Aug 18 04:39:44 PM PDT 24
Peak memory 204924 kb
Host smart-add4aec3-29f7-4cf3-9293-539397240412
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729106799 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.3729106799
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_stress_all.2671134079
Short name T14
Test name
Test status
Simulation time 1844759107 ps
CPU time 3.03 seconds
Started Aug 18 04:39:44 PM PDT 24
Finished Aug 18 04:39:47 PM PDT 24
Peak memory 205132 kb
Host smart-97ab8f07-0f79-4875-9b3d-871fda07eb36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671134079 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.2671134079
Directory /workspace/28.rv_dm_stress_all/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.1564057057
Short name T312
Test name
Test status
Simulation time 56177774 ps
CPU time 0.74 seconds
Started Aug 18 04:39:44 PM PDT 24
Finished Aug 18 04:39:45 PM PDT 24
Peak memory 205000 kb
Host smart-43f35ad8-5a55-462b-8af1-c0bf9b5967fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564057057 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.1564057057
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_stress_all.1885002400
Short name T163
Test name
Test status
Simulation time 1967168184 ps
CPU time 1.88 seconds
Started Aug 18 04:39:44 PM PDT 24
Finished Aug 18 04:39:46 PM PDT 24
Peak memory 204728 kb
Host smart-2202f402-1e80-4e98-991a-0ef6017e77b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885002400 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.1885002400
Directory /workspace/29.rv_dm_stress_all/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.123244259
Short name T67
Test name
Test status
Simulation time 122726899 ps
CPU time 0.96 seconds
Started Aug 18 04:39:14 PM PDT 24
Finished Aug 18 04:39:15 PM PDT 24
Peak memory 205004 kb
Host smart-67e9d4c7-96d3-4d0f-9c18-ecfff9ea6ae2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123244259 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.123244259
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.2173348527
Short name T73
Test name
Test status
Simulation time 22749153235 ps
CPU time 70.87 seconds
Started Aug 18 04:39:16 PM PDT 24
Finished Aug 18 04:40:27 PM PDT 24
Peak memory 213528 kb
Host smart-7bb1eede-66bd-435e-82e0-6c5f08aa7ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173348527 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.2173348527
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.2903857585
Short name T247
Test name
Test status
Simulation time 1709413767 ps
CPU time 2.63 seconds
Started Aug 18 04:39:13 PM PDT 24
Finished Aug 18 04:39:16 PM PDT 24
Peak memory 213496 kb
Host smart-78bd2e8f-4af7-447e-ad60-ffc15b617ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903857585 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.2903857585
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_buffered_enable.3524241692
Short name T295
Test name
Test status
Simulation time 294950174 ps
CPU time 0.93 seconds
Started Aug 18 04:39:15 PM PDT 24
Finished Aug 18 04:39:16 PM PDT 24
Peak memory 226096 kb
Host smart-4b08e018-c97c-48c5-a01e-a6f4e23789ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524241692 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_buffered_enable.3524241692
Directory /workspace/3.rv_dm_buffered_enable/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.3604725853
Short name T227
Test name
Test status
Simulation time 8211430271 ps
CPU time 3.46 seconds
Started Aug 18 04:39:19 PM PDT 24
Finished Aug 18 04:39:23 PM PDT 24
Peak memory 213612 kb
Host smart-60ed31a8-aca5-423f-bd66-08be0198a8d9
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3604725853 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t
l_access.3604725853
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_halt_resume_whereto.2442445944
Short name T45
Test name
Test status
Simulation time 297087280 ps
CPU time 1.61 seconds
Started Aug 18 04:39:21 PM PDT 24
Finished Aug 18 04:39:22 PM PDT 24
Peak memory 205024 kb
Host smart-3fb2ad11-17dd-44d2-bfe2-c79a022695dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442445944 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_halt_resume_whereto.2442445944
Directory /workspace/3.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.4282895371
Short name T223
Test name
Test status
Simulation time 91609579 ps
CPU time 0.93 seconds
Started Aug 18 04:39:14 PM PDT 24
Finished Aug 18 04:39:15 PM PDT 24
Peak memory 204924 kb
Host smart-65cbbe3b-abfe-4b7c-90b4-0a8c65cdac62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282895371 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.4282895371
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.2374322512
Short name T168
Test name
Test status
Simulation time 3754770602 ps
CPU time 3.46 seconds
Started Aug 18 04:39:17 PM PDT 24
Finished Aug 18 04:39:21 PM PDT 24
Peak memory 205380 kb
Host smart-a98f60b0-1f86-4315-9d02-e94643a50657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374322512 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.2374322512
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.197063953
Short name T63
Test name
Test status
Simulation time 1311000598 ps
CPU time 1.88 seconds
Started Aug 18 04:39:19 PM PDT 24
Finished Aug 18 04:39:21 PM PDT 24
Peak memory 228508 kb
Host smart-cbc00d02-29c5-4461-b44f-4f67fdfdad65
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197063953 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.197063953
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/3.rv_dm_sparse_lc_gate_fsm.3945123062
Short name T69
Test name
Test status
Simulation time 262036229 ps
CPU time 0.93 seconds
Started Aug 18 04:39:15 PM PDT 24
Finished Aug 18 04:39:16 PM PDT 24
Peak memory 213264 kb
Host smart-01fbdb43-fa7f-4f70-b8d8-694cbfa603cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945123062 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sparse_lc_gate_fsm.3945123062
Directory /workspace/3.rv_dm_sparse_lc_gate_fsm/latest

Test location /workspace/coverage/default/3.rv_dm_stress_all.366157189
Short name T178
Test name
Test status
Simulation time 1475094416 ps
CPU time 4.51 seconds
Started Aug 18 04:39:15 PM PDT 24
Finished Aug 18 04:39:20 PM PDT 24
Peak memory 204988 kb
Host smart-49fe4877-f356-42d5-93b6-a3e6e50aa597
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366157189 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.366157189
Directory /workspace/3.rv_dm_stress_all/latest

Test location /workspace/coverage/default/3.rv_dm_stress_all_with_rand_reset.2465388188
Short name T21
Test name
Test status
Simulation time 2917143192 ps
CPU time 63.39 seconds
Started Aug 18 04:39:20 PM PDT 24
Finished Aug 18 04:40:24 PM PDT 24
Peak memory 216996 kb
Host smart-7d451dc9-ea9c-4cea-afc0-7c9acc332b72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465388188 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all_with_rand_reset.2465388188
Directory /workspace/3.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.58633224
Short name T258
Test name
Test status
Simulation time 56502305 ps
CPU time 0.8 seconds
Started Aug 18 04:39:45 PM PDT 24
Finished Aug 18 04:39:46 PM PDT 24
Peak memory 204876 kb
Host smart-52e5bc7c-a663-48fa-bac7-dc152100670f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58633224 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.58633224
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/30.rv_dm_stress_all.3096471592
Short name T23
Test name
Test status
Simulation time 1674532971 ps
CPU time 3.36 seconds
Started Aug 18 04:39:41 PM PDT 24
Finished Aug 18 04:39:45 PM PDT 24
Peak memory 213288 kb
Host smart-066300e7-fb81-4c1a-8f8e-82a8abad2d24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096471592 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.3096471592
Directory /workspace/30.rv_dm_stress_all/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.1626686101
Short name T266
Test name
Test status
Simulation time 35464170 ps
CPU time 0.77 seconds
Started Aug 18 04:39:45 PM PDT 24
Finished Aug 18 04:39:46 PM PDT 24
Peak memory 205000 kb
Host smart-342b7b9c-f158-4b08-aa7a-8ac90f448af5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626686101 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.1626686101
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_stress_all.2132943505
Short name T218
Test name
Test status
Simulation time 3038816853 ps
CPU time 3.63 seconds
Started Aug 18 04:39:41 PM PDT 24
Finished Aug 18 04:39:45 PM PDT 24
Peak memory 205168 kb
Host smart-2b16f703-722e-47e5-b7e4-604a9e9a9881
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132943505 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.2132943505
Directory /workspace/31.rv_dm_stress_all/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.2683243705
Short name T286
Test name
Test status
Simulation time 50581952 ps
CPU time 0.69 seconds
Started Aug 18 04:39:48 PM PDT 24
Finished Aug 18 04:39:49 PM PDT 24
Peak memory 205008 kb
Host smart-8886f2f5-ab60-461b-a0a7-986251bd43b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683243705 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.2683243705
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.712198516
Short name T307
Test name
Test status
Simulation time 106745972 ps
CPU time 0.73 seconds
Started Aug 18 04:39:53 PM PDT 24
Finished Aug 18 04:39:54 PM PDT 24
Peak memory 204648 kb
Host smart-4c8e6dd3-6723-400f-b951-b707a403339e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712198516 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.712198516
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_stress_all.2408770957
Short name T39
Test name
Test status
Simulation time 3184147006 ps
CPU time 2.47 seconds
Started Aug 18 04:39:48 PM PDT 24
Finished Aug 18 04:39:51 PM PDT 24
Peak memory 205156 kb
Host smart-148cce07-e84a-45fa-812d-54a857e44817
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408770957 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.2408770957
Directory /workspace/33.rv_dm_stress_all/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.1263217843
Short name T237
Test name
Test status
Simulation time 137300216 ps
CPU time 0.9 seconds
Started Aug 18 04:39:54 PM PDT 24
Finished Aug 18 04:39:56 PM PDT 24
Peak memory 205000 kb
Host smart-5b37ffc0-319d-4b03-ad4c-1193d593c60a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263217843 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.1263217843
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_stress_all.2548433928
Short name T160
Test name
Test status
Simulation time 4688030536 ps
CPU time 11.89 seconds
Started Aug 18 04:39:47 PM PDT 24
Finished Aug 18 04:39:59 PM PDT 24
Peak memory 213356 kb
Host smart-633fdf50-a71a-4b9c-b38c-19954db6e5bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548433928 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.2548433928
Directory /workspace/34.rv_dm_stress_all/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.963095970
Short name T233
Test name
Test status
Simulation time 62642344 ps
CPU time 0.87 seconds
Started Aug 18 04:39:54 PM PDT 24
Finished Aug 18 04:39:55 PM PDT 24
Peak memory 204988 kb
Host smart-058734eb-8db6-4b51-bc3a-5cfab1bd20fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963095970 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.963095970
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_stress_all.3973117564
Short name T25
Test name
Test status
Simulation time 1469904943 ps
CPU time 4.81 seconds
Started Aug 18 04:39:51 PM PDT 24
Finished Aug 18 04:39:56 PM PDT 24
Peak memory 205172 kb
Host smart-6eccb386-4544-4155-b655-a942f7a3cfb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973117564 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.3973117564
Directory /workspace/35.rv_dm_stress_all/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.4161925343
Short name T204
Test name
Test status
Simulation time 56608044 ps
CPU time 0.71 seconds
Started Aug 18 04:39:56 PM PDT 24
Finished Aug 18 04:39:57 PM PDT 24
Peak memory 205004 kb
Host smart-a00d3254-ff83-46b5-ab52-023c78c647d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161925343 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.4161925343
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_stress_all.1206990598
Short name T260
Test name
Test status
Simulation time 2502886295 ps
CPU time 4.1 seconds
Started Aug 18 04:39:50 PM PDT 24
Finished Aug 18 04:39:55 PM PDT 24
Peak memory 205156 kb
Host smart-6a0901e5-aea0-4f1d-8422-39f8c969a2b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206990598 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.1206990598
Directory /workspace/36.rv_dm_stress_all/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.1394842874
Short name T289
Test name
Test status
Simulation time 81382773 ps
CPU time 0.75 seconds
Started Aug 18 04:39:49 PM PDT 24
Finished Aug 18 04:39:50 PM PDT 24
Peak memory 204876 kb
Host smart-8b4498e4-b241-4372-bbda-aeddd43de8b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394842874 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.1394842874
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_stress_all.1698074834
Short name T169
Test name
Test status
Simulation time 3291197684 ps
CPU time 5.9 seconds
Started Aug 18 04:39:53 PM PDT 24
Finished Aug 18 04:39:59 PM PDT 24
Peak memory 213256 kb
Host smart-b00bc513-ec89-4099-92bd-19742abd5bc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698074834 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.1698074834
Directory /workspace/37.rv_dm_stress_all/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.2559163044
Short name T60
Test name
Test status
Simulation time 121666520 ps
CPU time 0.79 seconds
Started Aug 18 04:39:54 PM PDT 24
Finished Aug 18 04:39:55 PM PDT 24
Peak memory 204992 kb
Host smart-e9ea1d5a-8c44-4be1-8ef1-3b90db6625d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559163044 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.2559163044
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.1328231668
Short name T246
Test name
Test status
Simulation time 83390874 ps
CPU time 0.76 seconds
Started Aug 18 04:39:49 PM PDT 24
Finished Aug 18 04:39:50 PM PDT 24
Peak memory 204900 kb
Host smart-64f1ddae-cc69-475d-9ec8-18c077df4093
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328231668 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.1328231668
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_stress_all.1779993276
Short name T324
Test name
Test status
Simulation time 4148429795 ps
CPU time 12.56 seconds
Started Aug 18 04:39:48 PM PDT 24
Finished Aug 18 04:40:01 PM PDT 24
Peak memory 205128 kb
Host smart-c7b31215-573d-49da-a938-e943ad4c87d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779993276 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.1779993276
Directory /workspace/39.rv_dm_stress_all/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.1626513362
Short name T278
Test name
Test status
Simulation time 128109185 ps
CPU time 0.96 seconds
Started Aug 18 04:39:15 PM PDT 24
Finished Aug 18 04:39:16 PM PDT 24
Peak memory 205012 kb
Host smart-00552c95-50de-4472-80e8-232cd998d435
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626513362 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.1626513362
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.1444904088
Short name T199
Test name
Test status
Simulation time 5507855175 ps
CPU time 7.89 seconds
Started Aug 18 04:39:13 PM PDT 24
Finished Aug 18 04:39:21 PM PDT 24
Peak memory 213516 kb
Host smart-9fe93c6a-c60b-4592-b8ee-5ac58b579ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444904088 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.1444904088
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.869027658
Short name T280
Test name
Test status
Simulation time 2061041033 ps
CPU time 3.6 seconds
Started Aug 18 04:39:20 PM PDT 24
Finished Aug 18 04:39:23 PM PDT 24
Peak memory 205388 kb
Host smart-074d360f-5b49-4ac4-9ea5-216bed92a453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869027658 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.869027658
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_buffered_enable.2499420047
Short name T252
Test name
Test status
Simulation time 424161426 ps
CPU time 1.92 seconds
Started Aug 18 04:39:17 PM PDT 24
Finished Aug 18 04:39:20 PM PDT 24
Peak memory 225704 kb
Host smart-d4cacaf0-ab11-4033-816a-4547e58680f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499420047 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_buffered_enable.2499420047
Directory /workspace/4.rv_dm_buffered_enable/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.3604368748
Short name T296
Test name
Test status
Simulation time 2625575146 ps
CPU time 8.49 seconds
Started Aug 18 04:39:13 PM PDT 24
Finished Aug 18 04:39:22 PM PDT 24
Peak memory 213544 kb
Host smart-74ab31fa-9074-423d-a4d9-4e37b570b5b7
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3604368748 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t
l_access.3604368748
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_halt_resume_whereto.3907414581
Short name T76
Test name
Test status
Simulation time 158392111 ps
CPU time 1.16 seconds
Started Aug 18 04:39:15 PM PDT 24
Finished Aug 18 04:39:16 PM PDT 24
Peak memory 204888 kb
Host smart-11482c69-8f0d-442c-90e7-8f241dce8d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907414581 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_halt_resume_whereto.3907414581
Directory /workspace/4.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.1272252552
Short name T262
Test name
Test status
Simulation time 90997162 ps
CPU time 0.81 seconds
Started Aug 18 04:39:15 PM PDT 24
Finished Aug 18 04:39:16 PM PDT 24
Peak memory 205024 kb
Host smart-d9dadf0d-8cca-41f8-9bc2-0816b16930b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272252552 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.1272252552
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.3279961705
Short name T206
Test name
Test status
Simulation time 1102359598 ps
CPU time 3.87 seconds
Started Aug 18 04:39:14 PM PDT 24
Finished Aug 18 04:39:18 PM PDT 24
Peak memory 205316 kb
Host smart-3b19d634-5008-4424-a2ed-822c50275861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279961705 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.3279961705
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.117515764
Short name T59
Test name
Test status
Simulation time 1302394388 ps
CPU time 1.74 seconds
Started Aug 18 04:39:15 PM PDT 24
Finished Aug 18 04:39:16 PM PDT 24
Peak memory 229464 kb
Host smart-82208e4a-c6eb-43b5-95f5-4a6a85979e54
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117515764 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.117515764
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/4.rv_dm_stress_all.3074577259
Short name T167
Test name
Test status
Simulation time 3838523803 ps
CPU time 3.27 seconds
Started Aug 18 04:39:18 PM PDT 24
Finished Aug 18 04:39:21 PM PDT 24
Peak memory 205228 kb
Host smart-ce306fb5-79f9-4e4a-81eb-4606e9beecba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074577259 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.3074577259
Directory /workspace/4.rv_dm_stress_all/latest

Test location /workspace/coverage/default/4.rv_dm_stress_all_with_rand_reset.3138107454
Short name T87
Test name
Test status
Simulation time 8442715145 ps
CPU time 35.76 seconds
Started Aug 18 04:39:18 PM PDT 24
Finished Aug 18 04:39:54 PM PDT 24
Peak memory 221636 kb
Host smart-634115da-9840-4ac9-942b-5385e25c436a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138107454 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all_with_rand_reset.3138107454
Directory /workspace/4.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.2434681324
Short name T100
Test name
Test status
Simulation time 175318703 ps
CPU time 0.78 seconds
Started Aug 18 04:39:48 PM PDT 24
Finished Aug 18 04:39:49 PM PDT 24
Peak memory 204904 kb
Host smart-25550a06-c78f-4469-afd6-a5a724f5d1b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434681324 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.2434681324
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/40.rv_dm_stress_all.575003050
Short name T158
Test name
Test status
Simulation time 3120465785 ps
CPU time 9.12 seconds
Started Aug 18 04:39:54 PM PDT 24
Finished Aug 18 04:40:04 PM PDT 24
Peak memory 205252 kb
Host smart-c7f43aca-d48f-4279-a7d0-79274d4da4f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575003050 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.575003050
Directory /workspace/40.rv_dm_stress_all/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.1682364777
Short name T311
Test name
Test status
Simulation time 68455842 ps
CPU time 0.74 seconds
Started Aug 18 04:39:50 PM PDT 24
Finished Aug 18 04:39:51 PM PDT 24
Peak memory 204912 kb
Host smart-d5e04ec2-5454-4c15-86dc-b710f691b10c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682364777 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.1682364777
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_stress_all.3559649123
Short name T146
Test name
Test status
Simulation time 2639827704 ps
CPU time 4.45 seconds
Started Aug 18 04:39:50 PM PDT 24
Finished Aug 18 04:39:55 PM PDT 24
Peak memory 213556 kb
Host smart-4de7f19a-ce65-4c45-8050-d2d85cd583c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559649123 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.3559649123
Directory /workspace/41.rv_dm_stress_all/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.3634901678
Short name T279
Test name
Test status
Simulation time 129793263 ps
CPU time 0.83 seconds
Started Aug 18 04:39:47 PM PDT 24
Finished Aug 18 04:39:48 PM PDT 24
Peak memory 204860 kb
Host smart-f0dd3310-471c-4bc7-b238-9480e6b69ca6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634901678 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.3634901678
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_stress_all.3436397837
Short name T323
Test name
Test status
Simulation time 1095331073 ps
CPU time 2.54 seconds
Started Aug 18 04:39:50 PM PDT 24
Finished Aug 18 04:39:52 PM PDT 24
Peak memory 205292 kb
Host smart-0c0d9871-5956-4fad-823c-0878e0ccac20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436397837 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.3436397837
Directory /workspace/42.rv_dm_stress_all/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.3344104218
Short name T212
Test name
Test status
Simulation time 102764193 ps
CPU time 0.94 seconds
Started Aug 18 04:39:53 PM PDT 24
Finished Aug 18 04:39:54 PM PDT 24
Peak memory 204644 kb
Host smart-d1efc498-3eec-480e-b657-77f348fa2442
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344104218 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.3344104218
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_stress_all.2002045090
Short name T301
Test name
Test status
Simulation time 2579072076 ps
CPU time 7.47 seconds
Started Aug 18 04:39:49 PM PDT 24
Finished Aug 18 04:39:56 PM PDT 24
Peak memory 213488 kb
Host smart-7b5e0419-b226-480b-be9e-7e41b813bcfb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002045090 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.2002045090
Directory /workspace/43.rv_dm_stress_all/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.3420254427
Short name T201
Test name
Test status
Simulation time 110864183 ps
CPU time 0.71 seconds
Started Aug 18 04:39:54 PM PDT 24
Finished Aug 18 04:39:55 PM PDT 24
Peak memory 204828 kb
Host smart-75e4a296-335e-4838-ba0b-9c9a90284a2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420254427 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.3420254427
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_stress_all.1825123472
Short name T156
Test name
Test status
Simulation time 6817221284 ps
CPU time 6.34 seconds
Started Aug 18 04:39:50 PM PDT 24
Finished Aug 18 04:39:56 PM PDT 24
Peak memory 205312 kb
Host smart-221f7429-5182-4a1a-819e-89e29b3100d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825123472 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.1825123472
Directory /workspace/44.rv_dm_stress_all/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.3777938311
Short name T276
Test name
Test status
Simulation time 47942872 ps
CPU time 0.82 seconds
Started Aug 18 04:39:54 PM PDT 24
Finished Aug 18 04:39:55 PM PDT 24
Peak memory 205004 kb
Host smart-78a0b8d1-e249-493a-94ea-3b3f44906d27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777938311 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.3777938311
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_stress_all.532680999
Short name T287
Test name
Test status
Simulation time 4650879090 ps
CPU time 4.11 seconds
Started Aug 18 04:39:50 PM PDT 24
Finished Aug 18 04:39:55 PM PDT 24
Peak memory 213520 kb
Host smart-68e062ba-4c53-4486-beff-c621de95d80d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532680999 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.532680999
Directory /workspace/45.rv_dm_stress_all/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.1440496877
Short name T272
Test name
Test status
Simulation time 32689776 ps
CPU time 0.77 seconds
Started Aug 18 04:39:54 PM PDT 24
Finished Aug 18 04:39:54 PM PDT 24
Peak memory 204832 kb
Host smart-c0b2d7b4-1b58-41af-bc4a-894ee2f7bf67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440496877 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.1440496877
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.1022001834
Short name T32
Test name
Test status
Simulation time 146960164 ps
CPU time 0.82 seconds
Started Aug 18 04:39:50 PM PDT 24
Finished Aug 18 04:39:51 PM PDT 24
Peak memory 205012 kb
Host smart-291a9eae-3d0a-4d47-baea-04d001aba2cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022001834 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.1022001834
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_stress_all.578059977
Short name T254
Test name
Test status
Simulation time 2214999879 ps
CPU time 6.69 seconds
Started Aug 18 04:39:49 PM PDT 24
Finished Aug 18 04:39:56 PM PDT 24
Peak memory 205284 kb
Host smart-f2c4223e-c445-4a27-a484-e491e363f124
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578059977 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.578059977
Directory /workspace/47.rv_dm_stress_all/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.1145137133
Short name T207
Test name
Test status
Simulation time 58031110 ps
CPU time 0.88 seconds
Started Aug 18 04:39:54 PM PDT 24
Finished Aug 18 04:39:56 PM PDT 24
Peak memory 204992 kb
Host smart-282484ec-8ce0-4efc-b391-da8ab342cef1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145137133 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.1145137133
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_stress_all.2069012457
Short name T22
Test name
Test status
Simulation time 3047752170 ps
CPU time 8.62 seconds
Started Aug 18 04:39:49 PM PDT 24
Finished Aug 18 04:39:58 PM PDT 24
Peak memory 205244 kb
Host smart-f5971d51-12a0-4056-a40b-a865a97cf7a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069012457 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.2069012457
Directory /workspace/48.rv_dm_stress_all/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.312208423
Short name T195
Test name
Test status
Simulation time 77894018 ps
CPU time 0.81 seconds
Started Aug 18 04:39:57 PM PDT 24
Finished Aug 18 04:39:58 PM PDT 24
Peak memory 204992 kb
Host smart-71f7dac8-f1a5-46a7-b05b-ddb0695b6aa5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312208423 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.312208423
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_stress_all.2729145198
Short name T10
Test name
Test status
Simulation time 1838234312 ps
CPU time 5.85 seconds
Started Aug 18 04:39:51 PM PDT 24
Finished Aug 18 04:39:57 PM PDT 24
Peak memory 213244 kb
Host smart-3cc7a5d8-5f3c-441b-8a2d-3ee7e5e098a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729145198 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.2729145198
Directory /workspace/49.rv_dm_stress_all/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.812556325
Short name T194
Test name
Test status
Simulation time 34285948 ps
CPU time 0.77 seconds
Started Aug 18 04:39:22 PM PDT 24
Finished Aug 18 04:39:23 PM PDT 24
Peak memory 205016 kb
Host smart-fbf5a433-e991-457f-8eaa-bed483cd8664
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812556325 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.812556325
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.2658109146
Short name T235
Test name
Test status
Simulation time 1210412579 ps
CPU time 2.84 seconds
Started Aug 18 04:39:26 PM PDT 24
Finished Aug 18 04:39:29 PM PDT 24
Peak memory 213620 kb
Host smart-76306fe9-d103-4ef3-9bbb-1b11542c0bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658109146 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.2658109146
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_buffered_enable.4109696618
Short name T270
Test name
Test status
Simulation time 354566577 ps
CPU time 1.08 seconds
Started Aug 18 04:39:26 PM PDT 24
Finished Aug 18 04:39:27 PM PDT 24
Peak memory 234232 kb
Host smart-54a84da1-b1f3-4f27-984c-aa5d174bb5f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109696618 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_buffered_enable.4109696618
Directory /workspace/5.rv_dm_buffered_enable/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.2963526961
Short name T64
Test name
Test status
Simulation time 2211142820 ps
CPU time 4.23 seconds
Started Aug 18 04:39:30 PM PDT 24
Finished Aug 18 04:39:34 PM PDT 24
Peak memory 205408 kb
Host smart-94cbe9ae-de5b-4d2e-9dae-c99c331c8144
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2963526961 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t
l_access.2963526961
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_halt_resume_whereto.3684456247
Short name T5
Test name
Test status
Simulation time 474039241 ps
CPU time 1.44 seconds
Started Aug 18 04:39:26 PM PDT 24
Finished Aug 18 04:39:27 PM PDT 24
Peak memory 204892 kb
Host smart-e4039f11-51ff-4b19-aef1-ded52d7f60bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684456247 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_halt_resume_whereto.3684456247
Directory /workspace/5.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.3893013210
Short name T242
Test name
Test status
Simulation time 6118978918 ps
CPU time 5.44 seconds
Started Aug 18 04:39:15 PM PDT 24
Finished Aug 18 04:39:20 PM PDT 24
Peak memory 205372 kb
Host smart-e717ad92-0204-4336-ae1c-bf34e5582ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893013210 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.3893013210
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_stress_all.1320277227
Short name T285
Test name
Test status
Simulation time 5773678052 ps
CPU time 8.83 seconds
Started Aug 18 04:39:23 PM PDT 24
Finished Aug 18 04:39:32 PM PDT 24
Peak memory 205100 kb
Host smart-3018523b-81b4-477a-aea9-4cd6d11f06c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320277227 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.1320277227
Directory /workspace/5.rv_dm_stress_all/latest

Test location /workspace/coverage/default/5.rv_dm_stress_all_with_rand_reset.3110354386
Short name T84
Test name
Test status
Simulation time 1811741165 ps
CPU time 44.23 seconds
Started Aug 18 04:39:24 PM PDT 24
Finished Aug 18 04:40:08 PM PDT 24
Peak memory 217192 kb
Host smart-a8894930-ba0c-4316-8529-6c525e9969ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110354386 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all_with_rand_reset.3110354386
Directory /workspace/5.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.959577849
Short name T197
Test name
Test status
Simulation time 100650552 ps
CPU time 0.76 seconds
Started Aug 18 04:39:22 PM PDT 24
Finished Aug 18 04:39:23 PM PDT 24
Peak memory 204828 kb
Host smart-ec304776-16c0-43c5-b309-68823aafce1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959577849 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.959577849
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.2326050574
Short name T226
Test name
Test status
Simulation time 1545243879 ps
CPU time 2.42 seconds
Started Aug 18 04:39:26 PM PDT 24
Finished Aug 18 04:39:28 PM PDT 24
Peak memory 205380 kb
Host smart-37841140-7d40-4ba5-8437-0b8e3562881d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326050574 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.2326050574
Directory /workspace/6.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.2800551327
Short name T221
Test name
Test status
Simulation time 3218779094 ps
CPU time 2.18 seconds
Started Aug 18 04:39:23 PM PDT 24
Finished Aug 18 04:39:25 PM PDT 24
Peak memory 213648 kb
Host smart-e3529217-2efa-44d0-823e-e4241ff6fe51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800551327 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.2800551327
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_buffered_enable.3040225088
Short name T95
Test name
Test status
Simulation time 732906180 ps
CPU time 1.68 seconds
Started Aug 18 04:39:25 PM PDT 24
Finished Aug 18 04:39:27 PM PDT 24
Peak memory 225772 kb
Host smart-986d2a84-97a6-4092-b89e-aceb72b13d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040225088 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_buffered_enable.3040225088
Directory /workspace/6.rv_dm_buffered_enable/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.2652938132
Short name T210
Test name
Test status
Simulation time 2110709780 ps
CPU time 7.15 seconds
Started Aug 18 04:39:23 PM PDT 24
Finished Aug 18 04:39:30 PM PDT 24
Peak memory 205280 kb
Host smart-9e33d988-238b-486b-acda-0f2ab88f9cf6
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2652938132 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t
l_access.2652938132
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_halt_resume_whereto.1799673275
Short name T145
Test name
Test status
Simulation time 555499330 ps
CPU time 2.29 seconds
Started Aug 18 04:39:25 PM PDT 24
Finished Aug 18 04:39:27 PM PDT 24
Peak memory 204924 kb
Host smart-124df83a-13d3-4697-9cac-3b7c0fcd12b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799673275 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_halt_resume_whereto.1799673275
Directory /workspace/6.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.3631316177
Short name T70
Test name
Test status
Simulation time 1861163406 ps
CPU time 4.3 seconds
Started Aug 18 04:39:26 PM PDT 24
Finished Aug 18 04:39:30 PM PDT 24
Peak memory 205432 kb
Host smart-5ac25e54-5bd6-4f9e-b9a8-10c4bc336041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631316177 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.3631316177
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_stress_all.1437246515
Short name T17
Test name
Test status
Simulation time 3321633819 ps
CPU time 9.57 seconds
Started Aug 18 04:39:26 PM PDT 24
Finished Aug 18 04:39:35 PM PDT 24
Peak memory 213324 kb
Host smart-2ba4d6a5-85ae-462a-8a0f-d03f2de61821
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437246515 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.1437246515
Directory /workspace/6.rv_dm_stress_all/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.3313206956
Short name T241
Test name
Test status
Simulation time 100928978 ps
CPU time 0.81 seconds
Started Aug 18 04:39:34 PM PDT 24
Finished Aug 18 04:39:35 PM PDT 24
Peak memory 204996 kb
Host smart-0b8334dd-78f8-4d0c-b200-877b6b5cc81a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313206956 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.3313206956
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.352563637
Short name T74
Test name
Test status
Simulation time 27512615440 ps
CPU time 14.86 seconds
Started Aug 18 04:39:23 PM PDT 24
Finished Aug 18 04:39:38 PM PDT 24
Peak memory 213504 kb
Host smart-2095c2bb-b6ec-49e8-8092-4c70d8c770f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352563637 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.352563637
Directory /workspace/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.3953001304
Short name T277
Test name
Test status
Simulation time 8376483700 ps
CPU time 24.1 seconds
Started Aug 18 04:39:26 PM PDT 24
Finished Aug 18 04:39:51 PM PDT 24
Peak memory 213632 kb
Host smart-1d7d32b0-e10b-463d-b083-0c1d2207ccd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953001304 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.3953001304
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_buffered_enable.2686859583
Short name T49
Test name
Test status
Simulation time 194427535 ps
CPU time 0.92 seconds
Started Aug 18 04:39:23 PM PDT 24
Finished Aug 18 04:39:24 PM PDT 24
Peak memory 225724 kb
Host smart-cf89eac7-42da-4b70-9dd4-a0edc7262ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686859583 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_buffered_enable.2686859583
Directory /workspace/7.rv_dm_buffered_enable/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.1807499189
Short name T222
Test name
Test status
Simulation time 3265703177 ps
CPU time 5.88 seconds
Started Aug 18 04:39:23 PM PDT 24
Finished Aug 18 04:39:29 PM PDT 24
Peak memory 213544 kb
Host smart-432478ff-c9a0-4558-a5ac-05792e4c294e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1807499189 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t
l_access.1807499189
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_halt_resume_whereto.2517607052
Short name T251
Test name
Test status
Simulation time 277124243 ps
CPU time 0.91 seconds
Started Aug 18 04:39:23 PM PDT 24
Finished Aug 18 04:39:24 PM PDT 24
Peak memory 204864 kb
Host smart-2fbbeab8-a6c0-455f-866d-28ee83bb5e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517607052 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_halt_resume_whereto.2517607052
Directory /workspace/7.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.1279295472
Short name T244
Test name
Test status
Simulation time 13968698131 ps
CPU time 12.78 seconds
Started Aug 18 04:39:24 PM PDT 24
Finished Aug 18 04:39:37 PM PDT 24
Peak memory 213580 kb
Host smart-9b2f075d-ef3d-452e-a4f0-7e7a533ae317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279295472 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.1279295472
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_stress_all.1200719812
Short name T314
Test name
Test status
Simulation time 2094982805 ps
CPU time 5.31 seconds
Started Aug 18 04:39:28 PM PDT 24
Finished Aug 18 04:39:33 PM PDT 24
Peak memory 205248 kb
Host smart-62f5d92c-13e6-4281-8f79-1e06a454d74d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200719812 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.1200719812
Directory /workspace/7.rv_dm_stress_all/latest

Test location /workspace/coverage/default/7.rv_dm_stress_all_with_rand_reset.2820912804
Short name T85
Test name
Test status
Simulation time 1596746494 ps
CPU time 26.81 seconds
Started Aug 18 04:39:23 PM PDT 24
Finished Aug 18 04:39:50 PM PDT 24
Peak memory 215456 kb
Host smart-95e57f63-4cd7-40bc-95c4-c4cdb1a5cf46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820912804 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all_with_rand_reset.2820912804
Directory /workspace/7.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.3522544219
Short name T191
Test name
Test status
Simulation time 47970014 ps
CPU time 0.8 seconds
Started Aug 18 04:39:34 PM PDT 24
Finished Aug 18 04:39:34 PM PDT 24
Peak memory 205008 kb
Host smart-4ee726d0-b8b5-4a18-b1d8-0b5ce47e09b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522544219 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.3522544219
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.2712240764
Short name T200
Test name
Test status
Simulation time 5985875421 ps
CPU time 2.93 seconds
Started Aug 18 04:39:30 PM PDT 24
Finished Aug 18 04:39:33 PM PDT 24
Peak memory 214640 kb
Host smart-0c696a50-3f07-470f-9dfc-081877731495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712240764 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.2712240764
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_buffered_enable.161595618
Short name T143
Test name
Test status
Simulation time 474205074 ps
CPU time 1.97 seconds
Started Aug 18 04:39:31 PM PDT 24
Finished Aug 18 04:39:33 PM PDT 24
Peak memory 226132 kb
Host smart-203fcf69-ac08-4046-93c7-0637d1a495c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161595618 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_buffered_enable.161595618
Directory /workspace/8.rv_dm_buffered_enable/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.1647105052
Short name T142
Test name
Test status
Simulation time 3980686093 ps
CPU time 7.18 seconds
Started Aug 18 04:39:30 PM PDT 24
Finished Aug 18 04:39:37 PM PDT 24
Peak memory 205364 kb
Host smart-973e84a0-81fe-4eaf-ac26-e92d4946ddca
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1647105052 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_t
l_access.1647105052
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.4259114119
Short name T219
Test name
Test status
Simulation time 2806003797 ps
CPU time 8.38 seconds
Started Aug 18 04:39:33 PM PDT 24
Finished Aug 18 04:39:42 PM PDT 24
Peak memory 205388 kb
Host smart-f7699b46-7efd-44ff-9dd4-20e21f666e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259114119 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.4259114119
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_stress_all.2939691536
Short name T299
Test name
Test status
Simulation time 6827483246 ps
CPU time 4.81 seconds
Started Aug 18 04:39:31 PM PDT 24
Finished Aug 18 04:39:36 PM PDT 24
Peak memory 205172 kb
Host smart-ad6d2236-82a3-4eb4-8fc5-7775c0808073
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939691536 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.2939691536
Directory /workspace/8.rv_dm_stress_all/latest

Test location /workspace/coverage/default/8.rv_dm_stress_all_with_rand_reset.747081910
Short name T46
Test name
Test status
Simulation time 3404747334 ps
CPU time 58.63 seconds
Started Aug 18 04:39:31 PM PDT 24
Finished Aug 18 04:40:29 PM PDT 24
Peak memory 221788 kb
Host smart-52a82a6c-c7a0-4a59-98e7-b5599dac5dc8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747081910 -assert nopostp
roc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all_with_rand_reset.747081910
Directory /workspace/8.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.3891177382
Short name T317
Test name
Test status
Simulation time 29618889 ps
CPU time 0.72 seconds
Started Aug 18 04:39:33 PM PDT 24
Finished Aug 18 04:39:34 PM PDT 24
Peak memory 204868 kb
Host smart-20017cb5-4647-466d-b043-c120b56ef1b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891177382 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.3891177382
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.555126700
Short name T28
Test name
Test status
Simulation time 5923394363 ps
CPU time 17.19 seconds
Started Aug 18 04:39:31 PM PDT 24
Finished Aug 18 04:39:49 PM PDT 24
Peak memory 213500 kb
Host smart-fa69fb35-b262-4727-ad92-335ff4bb4b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555126700 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.555126700
Directory /workspace/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.2817055637
Short name T302
Test name
Test status
Simulation time 1375884630 ps
CPU time 1.94 seconds
Started Aug 18 04:39:33 PM PDT 24
Finished Aug 18 04:39:35 PM PDT 24
Peak memory 205620 kb
Host smart-59a0db70-0a96-4ca3-9005-f06f30780d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817055637 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.2817055637
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_buffered_enable.1758329139
Short name T236
Test name
Test status
Simulation time 694732814 ps
CPU time 2.61 seconds
Started Aug 18 04:39:33 PM PDT 24
Finished Aug 18 04:39:36 PM PDT 24
Peak memory 225856 kb
Host smart-63f695a3-29ae-4ccb-a54e-ff9d7568b7d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758329139 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_buffered_enable.1758329139
Directory /workspace/9.rv_dm_buffered_enable/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.50418491
Short name T198
Test name
Test status
Simulation time 11151057859 ps
CPU time 17.26 seconds
Started Aug 18 04:39:31 PM PDT 24
Finished Aug 18 04:39:49 PM PDT 24
Peak memory 214560 kb
Host smart-53dd49d1-4c8b-4dc5-aa11-27d22863c2ec
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=50418491 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_tl_
access.50418491
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.428299240
Short name T176
Test name
Test status
Simulation time 2072856293 ps
CPU time 1.91 seconds
Started Aug 18 04:39:32 PM PDT 24
Finished Aug 18 04:39:34 PM PDT 24
Peak memory 205232 kb
Host smart-0cfc3143-22fc-4f09-9ef6-fc77b7c712af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428299240 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.428299240
Directory /workspace/9.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_stress_all.3026338595
Short name T144
Test name
Test status
Simulation time 1771430626 ps
CPU time 2.42 seconds
Started Aug 18 04:39:36 PM PDT 24
Finished Aug 18 04:39:38 PM PDT 24
Peak memory 205012 kb
Host smart-c82125f6-dbc1-4ac2-9037-db275e734859
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026338595 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.3026338595
Directory /workspace/9.rv_dm_stress_all/latest
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