Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 261191 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 606104 1 T3 2290 T7 1 T4 1



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 500569 1 T3 1763 T4 3 T5 4
values[0x0] 159246 1 T3 763 T4 2 T5 4
values[0x1] 207480 1 T3 2122 T7 2 T4 2



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 176448 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 690847 1 T3 3591 T7 2 T4 2



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 3920 1 T3 19 T81 1 T13 35
valid_sources[0x01] 3244 1 T3 13 T33 1 T13 45
valid_sources[0x02] 2740 1 T3 20 T13 29 T10 18
valid_sources[0x03] 3332 1 T3 18 T13 21 T10 5
valid_sources[0x04] 3162 1 T3 26 T13 43 T10 26
valid_sources[0x05] 3425 1 T3 27 T13 57 T10 17
valid_sources[0x06] 4096 1 T3 15 T13 36 T10 16
valid_sources[0x07] 2858 1 T3 14 T13 22 T41 2
valid_sources[0x08] 3391 1 T3 21 T43 4 T44 1
valid_sources[0x09] 4360 1 T3 22 T13 47 T10 2
valid_sources[0x0a] 3602 1 T3 17 T13 26 T41 2
valid_sources[0x0b] 2765 1 T3 22 T13 19 T41 1
valid_sources[0x0c] 3630 1 T3 16 T27 3 T12 18
valid_sources[0x0d] 3416 1 T3 22 T13 36 T41 2
valid_sources[0x0e] 3080 1 T3 16 T13 45 T10 18
valid_sources[0x0f] 3860 1 T3 21 T13 50 T10 25
valid_sources[0x10] 3608 1 T3 19 T13 35 T10 28
valid_sources[0x11] 3003 1 T3 22 T13 38 T10 29
valid_sources[0x12] 3567 1 T3 16 T13 56 T10 23
valid_sources[0x13] 3340 1 T3 23 T13 35 T10 20
valid_sources[0x14] 3521 1 T3 14 T13 23 T10 31
valid_sources[0x15] 2861 1 T3 21 T13 34 T10 34
valid_sources[0x16] 4241 1 T3 15 T20 1 T13 26
valid_sources[0x17] 3436 1 T3 20 T13 57 T14 1
valid_sources[0x18] 4253 1 T3 17 T13 53 T10 34
valid_sources[0x19] 3277 1 T3 25 T9 1 T13 24
valid_sources[0x1a] 3221 1 T3 9 T13 26 T10 15
valid_sources[0x1b] 3224 1 T3 19 T6 1 T13 27
valid_sources[0x1c] 3443 1 T3 16 T44 1 T13 51
valid_sources[0x1d] 3056 1 T3 11 T13 25 T10 20
valid_sources[0x1e] 3757 1 T3 24 T13 27 T10 14
valid_sources[0x1f] 3052 1 T3 19 T13 39 T10 12
valid_sources[0x20] 3109 1 T3 31 T13 23 T10 12
valid_sources[0x21] 2626 1 T3 15 T40 1 T48 1
valid_sources[0x22] 3165 1 T3 29 T13 44 T10 17
valid_sources[0x23] 2612 1 T3 16 T20 1 T13 41
valid_sources[0x24] 3499 1 T3 14 T13 30 T10 39
valid_sources[0x25] 3543 1 T3 20 T13 26 T10 20
valid_sources[0x26] 3172 1 T3 25 T13 45 T10 13
valid_sources[0x27] 3556 1 T3 14 T13 23 T10 20
valid_sources[0x28] 3815 1 T3 15 T13 33 T10 13
valid_sources[0x29] 4315 1 T3 13 T13 50 T41 1
valid_sources[0x2a] 4479 1 T3 24 T13 41 T10 14
valid_sources[0x2b] 3919 1 T3 15 T17 1 T13 44
valid_sources[0x2c] 3434 1 T3 18 T13 39 T10 16
valid_sources[0x2d] 2864 1 T3 22 T24 1 T13 17
valid_sources[0x2e] 3238 1 T3 11 T13 40 T10 11
valid_sources[0x2f] 3185 1 T3 28 T6 3 T13 30
valid_sources[0x30] 2699 1 T3 18 T6 2 T20 1
valid_sources[0x31] 3646 1 T3 20 T13 22 T10 45
valid_sources[0x32] 3222 1 T3 17 T13 44 T10 18
valid_sources[0x33] 2834 1 T3 15 T13 35 T10 5
valid_sources[0x34] 3351 1 T3 16 T13 40 T10 24
valid_sources[0x35] 3492 1 T3 13 T13 25 T10 6
valid_sources[0x36] 3795 1 T3 21 T13 31 T10 39
valid_sources[0x37] 3303 1 T3 14 T13 33 T10 13
valid_sources[0x38] 2992 1 T3 14 T13 29 T41 1
valid_sources[0x39] 3043 1 T3 15 T24 2 T13 26
valid_sources[0x3a] 3159 1 T3 19 T13 25 T10 49
valid_sources[0x3b] 3577 1 T3 15 T20 1 T17 1
valid_sources[0x3c] 2932 1 T3 17 T40 1 T13 21
valid_sources[0x3d] 2690 1 T3 13 T48 1 T13 27
valid_sources[0x3e] 3660 1 T3 18 T46 1 T24 1
valid_sources[0x3f] 3391 1 T3 16 T13 24 T10 16
valid_sources[0x40] 3704 1 T3 15 T13 50 T41 1
valid_sources[0x41] 4375 1 T3 16 T13 19 T10 34
valid_sources[0x42] 3317 1 T3 16 T9 2 T13 39
valid_sources[0x43] 3449 1 T3 21 T44 1 T48 1
valid_sources[0x44] 3127 1 T3 20 T13 38 T10 21
valid_sources[0x45] 3052 1 T3 27 T46 1 T13 30
valid_sources[0x46] 3520 1 T3 22 T13 42 T10 14
valid_sources[0x47] 4128 1 T3 17 T44 1 T13 36
valid_sources[0x48] 3040 1 T3 19 T13 26 T41 1
valid_sources[0x49] 3330 1 T3 17 T40 1 T13 51
valid_sources[0x4a] 3441 1 T3 20 T13 29 T10 18
valid_sources[0x4b] 2941 1 T3 21 T20 1 T13 29
valid_sources[0x4c] 2754 1 T3 16 T46 1 T40 1
valid_sources[0x4d] 3102 1 T3 17 T44 1 T13 32
valid_sources[0x4e] 3767 1 T3 14 T40 2 T13 44
valid_sources[0x4f] 3284 1 T3 13 T20 1 T48 1
valid_sources[0x50] 3057 1 T3 14 T4 2 T17 1
valid_sources[0x51] 3097 1 T3 20 T13 39 T10 16
valid_sources[0x52] 3596 1 T3 20 T13 30 T10 7
valid_sources[0x53] 3796 1 T3 17 T17 1 T13 54
valid_sources[0x54] 2794 1 T3 13 T13 24 T41 3
valid_sources[0x55] 3310 1 T3 22 T13 40 T41 1
valid_sources[0x56] 3177 1 T3 19 T13 44 T10 25
valid_sources[0x57] 3765 1 T3 19 T13 44 T41 1
valid_sources[0x58] 3057 1 T3 18 T13 18 T10 6
valid_sources[0x59] 3425 1 T3 20 T13 40 T41 1
valid_sources[0x5a] 4128 1 T3 13 T13 28 T10 23
valid_sources[0x5b] 2883 1 T3 18 T13 35 T10 12
valid_sources[0x5c] 3792 1 T3 16 T13 22 T10 14
valid_sources[0x5d] 2847 1 T3 15 T13 31 T10 17
valid_sources[0x5e] 3309 1 T3 22 T68 1 T48 1
valid_sources[0x5f] 4823 1 T3 19 T13 34 T14 2
valid_sources[0x60] 3025 1 T3 16 T13 27 T41 1
valid_sources[0x61] 3160 1 T3 20 T13 34 T41 2
valid_sources[0x62] 3316 1 T3 25 T13 26 T41 1
valid_sources[0x63] 3552 1 T3 25 T40 1 T13 40
valid_sources[0x64] 3256 1 T3 18 T44 1 T13 25
valid_sources[0x65] 3235 1 T3 21 T44 1 T13 36
valid_sources[0x66] 3574 1 T3 23 T43 3 T13 39
valid_sources[0x67] 3379 1 T3 15 T6 1 T48 1
valid_sources[0x68] 3064 1 T3 16 T13 18 T10 27
valid_sources[0x69] 3106 1 T3 20 T28 2 T13 46
valid_sources[0x6a] 3530 1 T3 8 T13 32 T10 4
valid_sources[0x6b] 3085 1 T3 18 T13 33 T10 20
valid_sources[0x6c] 4556 1 T3 15 T13 33 T10 10
valid_sources[0x6d] 3470 1 T3 13 T13 36 T10 30
valid_sources[0x6e] 2904 1 T3 12 T47 1 T24 1
valid_sources[0x6f] 3719 1 T3 25 T13 30 T10 17
valid_sources[0x70] 3323 1 T3 17 T13 22 T10 12
valid_sources[0x71] 3317 1 T3 20 T13 43 T10 20
valid_sources[0x72] 3016 1 T3 11 T9 1 T13 46
valid_sources[0x73] 3123 1 T3 8 T13 28 T10 27
valid_sources[0x74] 3317 1 T3 17 T13 24 T41 1
valid_sources[0x75] 3325 1 T3 19 T27 1 T20 1
valid_sources[0x76] 4146 1 T3 15 T13 33 T10 29
valid_sources[0x77] 3164 1 T3 14 T13 28 T10 12
valid_sources[0x78] 3971 1 T3 22 T47 3 T13 49
valid_sources[0x79] 2689 1 T3 15 T13 26 T10 21
valid_sources[0x7a] 3434 1 T3 21 T17 1 T13 23
valid_sources[0x7b] 3196 1 T3 22 T44 1 T13 32
valid_sources[0x7c] 3166 1 T3 24 T13 35 T10 37
valid_sources[0x7d] 3473 1 T3 18 T9 1 T13 32
valid_sources[0x7e] 3156 1 T3 20 T13 12 T10 11
valid_sources[0x7f] 3180 1 T3 15 T24 1 T13 39
valid_sources[0x80] 2756 1 T3 21 T20 2 T13 31



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 301140 1 T3 1086 T4 1 T5 2
values[0x0] all_enables biggest_size 152682 1 T3 616 T6 2 T33 2
values[0x1] all_enables biggest_size 152282 1 T3 588 T7 1 T5 1


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 7757 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 96169 1 T1 2 T2 4 T3 2485



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 29299 1 T3 661 T13 1557 T10 693
values[0x0] 36403 1 T1 5 T2 8 T3 951
values[0x1] 38224 1 T1 6 T2 6 T3 966



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 5119 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 98807 1 T1 5 T2 6 T3 2526



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 322 1 T3 1 T78 2 T10 14
valid_sources[0x01] 510 1 T3 57 T40 1 T10 14
valid_sources[0x02] 540 1 T3 41 T13 78 T10 10
valid_sources[0x03] 370 1 T10 13 T211 1 T53 49
valid_sources[0x04] 501 1 T3 55 T212 2 T49 2
valid_sources[0x05] 389 1 T10 8 T168 1 T194 1
valid_sources[0x06] 569 1 T10 6 T213 1 T214 15
valid_sources[0x07] 264 1 T3 1 T13 6 T10 10
valid_sources[0x08] 413 1 T2 2 T3 1 T13 27
valid_sources[0x09] 298 1 T10 9 T53 40 T102 1
valid_sources[0x0a] 429 1 T1 1 T3 2 T13 51
valid_sources[0x0b] 358 1 T126 1 T13 2 T10 18
valid_sources[0x0c] 584 1 T3 3 T33 1 T13 175
valid_sources[0x0d] 431 1 T13 124 T10 3 T53 55
valid_sources[0x0e] 681 1 T43 1 T13 104 T10 7
valid_sources[0x0f] 244 1 T215 1 T10 10 T53 26
valid_sources[0x10] 428 1 T3 2 T10 6 T53 22
valid_sources[0x11] 332 1 T13 2 T10 10 T53 39
valid_sources[0x12] 258 1 T79 1 T13 3 T49 5
valid_sources[0x13] 726 1 T13 235 T10 10 T53 36
valid_sources[0x14] 307 1 T109 1 T13 1 T10 13
valid_sources[0x15] 761 1 T3 4 T13 267 T10 15
valid_sources[0x16] 536 1 T2 1 T13 6 T10 15
valid_sources[0x17] 282 1 T10 10 T168 1 T216 6
valid_sources[0x18] 365 1 T13 73 T10 9 T217 1
valid_sources[0x19] 539 1 T212 1 T13 98 T10 18
valid_sources[0x1a] 394 1 T10 7 T53 56 T102 119
valid_sources[0x1b] 416 1 T3 1 T218 1 T13 1
valid_sources[0x1c] 380 1 T13 2 T10 14 T53 63
valid_sources[0x1d] 543 1 T3 1 T13 2 T10 14
valid_sources[0x1e] 529 1 T3 72 T181 1 T13 3
valid_sources[0x1f] 293 1 T13 1 T14 2 T10 10
valid_sources[0x20] 567 1 T13 93 T10 9 T219 1
valid_sources[0x21] 222 1 T13 1 T10 6 T220 1
valid_sources[0x22] 265 1 T213 2 T53 34 T102 31
valid_sources[0x23] 383 1 T17 1 T80 1 T10 16
valid_sources[0x24] 372 1 T10 10 T211 2 T221 3
valid_sources[0x25] 349 1 T3 1 T10 4 T39 1
valid_sources[0x26] 662 1 T3 73 T33 1 T97 2
valid_sources[0x27] 328 1 T3 1 T13 2 T10 10
valid_sources[0x28] 306 1 T10 15 T53 39 T102 14
valid_sources[0x29] 409 1 T44 1 T13 46 T10 7
valid_sources[0x2a] 363 1 T38 1 T44 1 T13 92
valid_sources[0x2b] 327 1 T10 8 T53 68 T51 18
valid_sources[0x2c] 505 1 T3 27 T13 27 T10 13
valid_sources[0x2d] 252 1 T30 7 T13 2 T10 16
valid_sources[0x2e] 418 1 T13 93 T10 10 T183 1
valid_sources[0x2f] 311 1 T76 2 T10 15 T53 51
valid_sources[0x30] 463 1 T40 1 T10 10 T213 1
valid_sources[0x31] 402 1 T13 1 T10 19 T179 1
valid_sources[0x32] 403 1 T3 60 T13 46 T10 2
valid_sources[0x33] 373 1 T3 2 T71 3 T13 71
valid_sources[0x34] 430 1 T3 2 T110 1 T13 150
valid_sources[0x35] 325 1 T24 8 T10 8 T222 1
valid_sources[0x36] 400 1 T3 2 T212 1 T13 1
valid_sources[0x37] 447 1 T1 1 T5 1 T13 79
valid_sources[0x38] 310 1 T13 28 T10 7 T223 2
valid_sources[0x39] 433 1 T13 2 T10 9 T53 56
valid_sources[0x3a] 598 1 T3 8 T77 7 T224 1
valid_sources[0x3b] 523 1 T3 1 T225 1 T13 3
valid_sources[0x3c] 288 1 T10 5 T198 7 T85 4
valid_sources[0x3d] 380 1 T3 1 T226 1 T227 1
valid_sources[0x3e] 415 1 T3 77 T189 1 T13 79
valid_sources[0x3f] 361 1 T13 1 T10 20 T53 46
valid_sources[0x40] 320 1 T3 10 T13 12 T10 6
valid_sources[0x41] 523 1 T10 6 T53 24 T91 2
valid_sources[0x42] 344 1 T13 1 T10 13 T53 40
valid_sources[0x43] 236 1 T2 1 T13 3 T10 10
valid_sources[0x44] 331 1 T27 2 T228 1 T17 2
valid_sources[0x45] 293 1 T3 2 T12 1 T10 6
valid_sources[0x46] 437 1 T3 1 T13 83 T10 12
valid_sources[0x47] 315 1 T55 1 T10 12 T53 53
valid_sources[0x48] 412 1 T3 1 T13 1 T10 7
valid_sources[0x49] 426 1 T10 8 T169 1 T229 1
valid_sources[0x4a] 354 1 T3 6 T27 1 T9 7
valid_sources[0x4b] 316 1 T3 1 T10 10 T182 7
valid_sources[0x4c] 380 1 T10 15 T21 6 T220 2
valid_sources[0x4d] 416 1 T13 71 T10 8 T53 47
valid_sources[0x4e] 565 1 T10 11 T53 52 T102 78
valid_sources[0x4f] 235 1 T48 1 T13 13 T10 9
valid_sources[0x50] 292 1 T3 34 T78 1 T10 11
valid_sources[0x51] 627 1 T3 27 T5 3 T13 187
valid_sources[0x52] 557 1 T3 1 T10 6 T53 34
valid_sources[0x53] 341 1 T3 3 T13 1 T10 7
valid_sources[0x54] 481 1 T44 1 T17 1 T10 4
valid_sources[0x55] 602 1 T228 1 T13 2 T10 17
valid_sources[0x56] 269 1 T13 2 T10 7 T53 42
valid_sources[0x57] 327 1 T72 1 T13 1 T10 13
valid_sources[0x58] 458 1 T14 1 T230 2 T10 15
valid_sources[0x59] 369 1 T3 56 T10 19 T220 1
valid_sources[0x5a] 372 1 T12 1 T10 6 T171 1
valid_sources[0x5b] 333 1 T13 1 T10 11 T53 46
valid_sources[0x5c] 391 1 T13 40 T10 10 T185 1
valid_sources[0x5d] 277 1 T69 1 T13 3 T10 12
valid_sources[0x5e] 380 1 T13 1 T10 16 T53 38
valid_sources[0x5f] 446 1 T212 1 T231 10 T10 7
valid_sources[0x60] 456 1 T13 4 T10 10 T167 1
valid_sources[0x61] 349 1 T13 2 T10 4 T87 1
valid_sources[0x62] 363 1 T10 12 T85 5 T53 29
valid_sources[0x63] 576 1 T12 1 T10 16 T232 1
valid_sources[0x64] 401 1 T3 1 T33 1 T13 45
valid_sources[0x65] 277 1 T181 1 T48 2 T13 4
valid_sources[0x66] 333 1 T2 1 T3 2 T13 2
valid_sources[0x67] 515 1 T13 1 T14 2 T10 10
valid_sources[0x68] 282 1 T1 1 T29 8 T233 7
valid_sources[0x69] 391 1 T12 1 T13 35 T10 9
valid_sources[0x6a] 520 1 T3 91 T12 1 T10 12
valid_sources[0x6b] 462 1 T3 141 T13 49 T10 8
valid_sources[0x6c] 853 1 T3 1 T212 1 T48 1
valid_sources[0x6d] 359 1 T3 2 T10 6 T234 4
valid_sources[0x6e] 355 1 T66 1 T81 1 T13 5
valid_sources[0x6f] 455 1 T3 1 T13 179 T10 16
valid_sources[0x70] 339 1 T68 1 T40 1 T13 2
valid_sources[0x71] 364 1 T2 1 T10 13 T185 2
valid_sources[0x72] 310 1 T3 60 T10 15 T235 1
valid_sources[0x73] 485 1 T2 1 T44 2 T48 1
valid_sources[0x74] 529 1 T3 101 T79 1 T13 2
valid_sources[0x75] 520 1 T2 1 T3 1 T13 95
valid_sources[0x76] 396 1 T13 1 T10 8 T84 1
valid_sources[0x77] 496 1 T13 48 T10 23 T53 40
valid_sources[0x78] 294 1 T13 7 T10 12 T53 51
valid_sources[0x79] 427 1 T13 56 T10 19 T85 1
valid_sources[0x7a] 260 1 T13 15 T10 13 T53 35
valid_sources[0x7b] 254 1 T12 1 T10 20 T53 25
valid_sources[0x7c] 464 1 T13 1 T10 5 T53 48
valid_sources[0x7d] 272 1 T3 1 T79 2 T13 1
valid_sources[0x7e] 356 1 T3 2 T13 31 T10 10
valid_sources[0x7f] 311 1 T3 1 T10 8 T236 1
valid_sources[0x80] 399 1 T3 1 T10 13 T58 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 25551 1 T3 623 T13 1459 T10 651
values[0x0] all_enables biggest_size 35409 1 T1 1 T2 4 T3 945
values[0x1] all_enables biggest_size 35209 1 T1 1 T3 917 T8 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%