SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[rv_dm_mem_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[rv_dm_regs_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 1097286 | 1 | T3 | 9500 | T7 | 2 | T4 | 7 | ||||
auto[1] | 161123 | 1 | T3 | 3901 | T13 | 10035 | T41 | 80 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 1258200 | 1 | T3 | 13401 | T7 | 2 | T4 | 7 | ||||
values[1] | 28 | 1 | T114 | 1 | T174 | 2 | T199 | 1 | ||||
values[2] | 4 | 1 | T114 | 1 | T199 | 1 | T200 | 1 | ||||
values[3] | 92 | 1 | T114 | 6 | T173 | 1 | T174 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 1258196 | 1 | T3 | 13401 | T7 | 2 | T4 | 7 | ||||
values[1] | 19 | 1 | T114 | 1 | T173 | 1 | T199 | 2 | ||||
values[2] | 5 | 1 | T114 | 1 | T201 | 2 | T200 | 1 | ||||
values[3] | 112 | 1 | T114 | 7 | T173 | 4 | T174 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 1258089 | 1 | T3 | 13401 | T7 | 2 | T4 | 7 | ||||
auto[TlIntgErrCmd] | 107 | 1 | T114 | 6 | T173 | 3 | T174 | 3 | ||||
auto[TlIntgErrData] | 111 | 1 | T114 | 5 | T173 | 5 | T174 | 2 | ||||
auto[TlIntgErrBoth] | 102 | 1 | T114 | 9 | T173 | 2 | T174 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[0] | 261361 | 0 | T1 | 11 | T2 | 14 | T3 | 6991 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 261142 | 1 | T1 | 11 | T2 | 14 | T3 | 6991 | ||||
values[1] | 17 | 1 | T199 | 2 | T201 | 2 | T202 | 1 | ||||
values[2] | 1 | 1 | T203 | 1 | - | - | - | - | ||||
values[3] | 122 | 1 | T114 | 6 | T173 | 4 | T174 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 261148 | 1 | T1 | 11 | T2 | 14 | T3 | 6991 | ||||
values[1] | 33 | 1 | T114 | 1 | T173 | 2 | T199 | 2 | ||||
values[2] | 6 | 1 | T114 | 1 | T199 | 1 | T204 | 1 | ||||
values[3] | 102 | 1 | T114 | 8 | T173 | 3 | T174 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 261041 | 1 | T1 | 11 | T2 | 14 | T3 | 6991 | ||||
auto[TlIntgErrCmd] | 107 | 1 | T114 | 7 | T173 | 1 | T174 | 2 | ||||
auto[TlIntgErrData] | 101 | 1 | T114 | 4 | T173 | 5 | T174 | 1 | ||||
auto[TlIntgErrBoth] | 112 | 1 | T114 | 9 | T173 | 4 | T174 | 7 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |