Summary for Variable cp_num_num_enable_bytes
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_num_num_enable_bytes
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
partial |
638848 |
1 |
|
|
T3 |
11094 |
|
T7 |
1 |
|
T4 |
6 |
full_word |
619561 |
1 |
|
|
T3 |
2307 |
|
T7 |
1 |
|
T4 |
1 |
Summary for Variable cp_tl_intg_err_type
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
4 |
0 |
4 |
100.00 |
Automatically Generated Bins for cp_tl_intg_err_type
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
1258089 |
1 |
|
|
T3 |
13401 |
|
T7 |
2 |
|
T4 |
7 |
auto[TlIntgErrCmd] |
107 |
1 |
|
|
T114 |
6 |
|
T173 |
3 |
|
T174 |
3 |
auto[TlIntgErrData] |
111 |
1 |
|
|
T114 |
5 |
|
T173 |
5 |
|
T174 |
2 |
auto[TlIntgErrBoth] |
102 |
1 |
|
|
T114 |
9 |
|
T173 |
2 |
|
T174 |
5 |
Summary for Variable cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_write
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
517125 |
1 |
|
|
T3 |
2033 |
|
T4 |
3 |
|
T5 |
4 |
auto[1] |
741284 |
1 |
|
|
T3 |
11368 |
|
T7 |
2 |
|
T4 |
4 |
Summary for Cross cr_all
Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
16 |
0 |
16 |
100.00 |
|
Automatically Generated Cross Bins for cr_all
Bins
cp_tl_intg_err_type | cp_num_num_enable_bytes | cp_write | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
partial |
auto[0] |
214289 |
1 |
|
|
T3 |
987 |
|
T4 |
2 |
|
T5 |
2 |
auto[TlIntgErrNone] |
partial |
auto[1] |
424269 |
1 |
|
|
T3 |
10107 |
|
T7 |
1 |
|
T4 |
4 |
auto[TlIntgErrNone] |
full_word |
auto[0] |
302686 |
1 |
|
|
T3 |
1046 |
|
T4 |
1 |
|
T5 |
2 |
auto[TlIntgErrNone] |
full_word |
auto[1] |
316845 |
1 |
|
|
T3 |
1261 |
|
T7 |
1 |
|
T5 |
1 |
auto[TlIntgErrCmd] |
partial |
auto[0] |
37 |
1 |
|
|
T114 |
4 |
|
T173 |
1 |
|
T174 |
1 |
auto[TlIntgErrCmd] |
partial |
auto[1] |
63 |
1 |
|
|
T114 |
2 |
|
T173 |
2 |
|
T174 |
2 |
auto[TlIntgErrCmd] |
full_word |
auto[0] |
3 |
1 |
|
|
T205 |
1 |
|
T206 |
1 |
|
T207 |
1 |
auto[TlIntgErrCmd] |
full_word |
auto[1] |
4 |
1 |
|
|
T199 |
1 |
|
T208 |
1 |
|
T209 |
1 |
auto[TlIntgErrData] |
partial |
auto[0] |
54 |
1 |
|
|
T114 |
3 |
|
T173 |
1 |
|
T174 |
1 |
auto[TlIntgErrData] |
partial |
auto[1] |
41 |
1 |
|
|
T114 |
2 |
|
T173 |
3 |
|
T174 |
1 |
auto[TlIntgErrData] |
full_word |
auto[0] |
7 |
1 |
|
|
T199 |
1 |
|
T201 |
2 |
|
T204 |
1 |
auto[TlIntgErrData] |
full_word |
auto[1] |
9 |
1 |
|
|
T173 |
1 |
|
T210 |
1 |
|
T208 |
1 |
auto[TlIntgErrBoth] |
partial |
auto[0] |
46 |
1 |
|
|
T114 |
3 |
|
T173 |
1 |
|
T174 |
3 |
auto[TlIntgErrBoth] |
partial |
auto[1] |
49 |
1 |
|
|
T114 |
5 |
|
T173 |
1 |
|
T174 |
2 |
auto[TlIntgErrBoth] |
full_word |
auto[0] |
3 |
1 |
|
|
T210 |
1 |
|
T206 |
2 |
|
- |
- |
auto[TlIntgErrBoth] |
full_word |
auto[1] |
4 |
1 |
|
|
T114 |
1 |
|
T199 |
1 |
|
T206 |
1 |