Assert Coverage for Module :
rv_dm_regs_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
105852250 |
117147 |
0 |
0 |
T3 |
96385 |
3366 |
0 |
0 |
T4 |
34974 |
0 |
0 |
0 |
T5 |
238528 |
0 |
0 |
0 |
T6 |
37055 |
0 |
0 |
0 |
T7 |
144584 |
0 |
0 |
0 |
T8 |
46421 |
0 |
0 |
0 |
T10 |
0 |
3845 |
0 |
0 |
T13 |
0 |
8186 |
0 |
0 |
T15 |
115353 |
0 |
0 |
0 |
T32 |
6855 |
0 |
0 |
0 |
T34 |
3637 |
0 |
0 |
0 |
T51 |
0 |
7852 |
0 |
0 |
T52 |
0 |
5179 |
0 |
0 |
T53 |
0 |
16490 |
0 |
0 |
T71 |
2364 |
0 |
0 |
0 |
T102 |
0 |
10419 |
0 |
0 |
T111 |
0 |
1636 |
0 |
0 |
T112 |
0 |
391 |
0 |
0 |
T113 |
0 |
32 |
0 |
0 |
late_debug_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
105852250 |
7358 |
0 |
0 |
T10 |
206227 |
697 |
0 |
0 |
T11 |
39156 |
0 |
0 |
0 |
T21 |
93801 |
0 |
0 |
0 |
T52 |
0 |
975 |
0 |
0 |
T111 |
0 |
662 |
0 |
0 |
T113 |
0 |
58 |
0 |
0 |
T116 |
0 |
1 |
0 |
0 |
T122 |
0 |
23 |
0 |
0 |
T140 |
0 |
7 |
0 |
0 |
T156 |
0 |
46 |
0 |
0 |
T163 |
0 |
46 |
0 |
0 |
T164 |
0 |
31 |
0 |
0 |
T165 |
126085 |
0 |
0 |
0 |
T166 |
226676 |
0 |
0 |
0 |
T167 |
882025 |
0 |
0 |
0 |
T168 |
143633 |
0 |
0 |
0 |
T169 |
36676 |
0 |
0 |
0 |
T170 |
1257 |
0 |
0 |
0 |
T171 |
1797 |
0 |
0 |
0 |
late_debug_enable_regwen_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
105852250 |
5888 |
0 |
0 |
T10 |
206227 |
527 |
0 |
0 |
T11 |
39156 |
0 |
0 |
0 |
T21 |
93801 |
0 |
0 |
0 |
T52 |
0 |
710 |
0 |
0 |
T111 |
0 |
684 |
0 |
0 |
T113 |
0 |
31 |
0 |
0 |
T122 |
0 |
18 |
0 |
0 |
T140 |
0 |
4 |
0 |
0 |
T156 |
0 |
16 |
0 |
0 |
T163 |
0 |
48 |
0 |
0 |
T164 |
0 |
50 |
0 |
0 |
T165 |
126085 |
0 |
0 |
0 |
T166 |
226676 |
0 |
0 |
0 |
T167 |
882025 |
0 |
0 |
0 |
T168 |
143633 |
0 |
0 |
0 |
T169 |
36676 |
0 |
0 |
0 |
T170 |
1257 |
0 |
0 |
0 |
T171 |
1797 |
0 |
0 |
0 |
T172 |
0 |
42 |
0 |
0 |