Line Coverage for Module :
rv_dm_enable_checker
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 36 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv' or '../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
29 |
1 |
1 |
36 |
1 |
1 |
Assert Coverage for Module :
rv_dm_enable_checker
Assertion Details
DebugRequestNeedsDebug_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
49295582 |
49235714 |
0 |
0 |
T1 |
3566 |
3475 |
0 |
0 |
T2 |
1949 |
1884 |
0 |
0 |
T3 |
96385 |
94011 |
0 |
0 |
T4 |
34974 |
34916 |
0 |
0 |
T5 |
238528 |
238250 |
0 |
0 |
T6 |
37055 |
36644 |
0 |
0 |
T7 |
144584 |
144351 |
0 |
0 |
T8 |
46421 |
46365 |
0 |
0 |
T15 |
115353 |
115140 |
0 |
0 |
T34 |
3637 |
3586 |
0 |
0 |
MemTLResponseWithoutDebugIsError_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
49149700 |
49089832 |
0 |
0 |
T1 |
3566 |
3475 |
0 |
0 |
T2 |
1949 |
1884 |
0 |
0 |
T3 |
96385 |
94011 |
0 |
0 |
T4 |
34974 |
34916 |
0 |
0 |
T5 |
238528 |
238250 |
0 |
0 |
T6 |
37055 |
36644 |
0 |
0 |
T7 |
144584 |
144351 |
0 |
0 |
T8 |
46421 |
46365 |
0 |
0 |
T15 |
115353 |
115140 |
0 |
0 |
T34 |
3637 |
3586 |
0 |
0 |
NdmResetAckNeedsDebug_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
49296285 |
49236417 |
0 |
0 |
T1 |
3566 |
3475 |
0 |
0 |
T2 |
1949 |
1884 |
0 |
0 |
T3 |
96385 |
94011 |
0 |
0 |
T4 |
34974 |
34916 |
0 |
0 |
T5 |
238528 |
238250 |
0 |
0 |
T6 |
37055 |
36644 |
0 |
0 |
T7 |
144584 |
144351 |
0 |
0 |
T8 |
46421 |
46365 |
0 |
0 |
T15 |
115353 |
115140 |
0 |
0 |
T34 |
3637 |
3586 |
0 |
0 |
SbaTLRequestNeedsDebug_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
49149700 |
49089832 |
0 |
0 |
T1 |
3566 |
3475 |
0 |
0 |
T2 |
1949 |
1884 |
0 |
0 |
T3 |
96385 |
94011 |
0 |
0 |
T4 |
34974 |
34916 |
0 |
0 |
T5 |
238528 |
238250 |
0 |
0 |
T6 |
37055 |
36644 |
0 |
0 |
T7 |
144584 |
144351 |
0 |
0 |
T8 |
46421 |
46365 |
0 |
0 |
T15 |
115353 |
115140 |
0 |
0 |
T34 |
3637 |
3586 |
0 |
0 |