Line Coverage for Module :
prim_generic_clock_mux2
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Module :
prim_generic_clock_mux2
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T82 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T82 |
1 | 1 | Covered | T82 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T82 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Module :
prim_generic_clock_mux2
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
7459300 |
7457816 |
0 |
0 |
selKnown1 |
54516794 |
54515310 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7459300 |
7457816 |
0 |
0 |
T1 |
236 |
234 |
0 |
0 |
T2 |
240 |
238 |
0 |
0 |
T3 |
3737 |
3733 |
0 |
0 |
T4 |
2672 |
2668 |
0 |
0 |
T5 |
14710 |
14706 |
0 |
0 |
T6 |
14964 |
14960 |
0 |
0 |
T7 |
11476 |
11472 |
0 |
0 |
T8 |
11634 |
11630 |
0 |
0 |
T15 |
17862 |
17858 |
0 |
0 |
T20 |
0 |
6 |
0 |
0 |
T26 |
0 |
10 |
0 |
0 |
T27 |
0 |
13 |
0 |
0 |
T29 |
0 |
20 |
0 |
0 |
T32 |
2 |
0 |
0 |
0 |
T33 |
0 |
9 |
0 |
0 |
T34 |
238 |
234 |
0 |
0 |
T71 |
2 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
54516794 |
54515310 |
0 |
0 |
T1 |
3684 |
3682 |
0 |
0 |
T2 |
2069 |
2067 |
0 |
0 |
T3 |
98260 |
98256 |
0 |
0 |
T4 |
36311 |
36307 |
0 |
0 |
T5 |
245886 |
245882 |
0 |
0 |
T6 |
44541 |
44537 |
0 |
0 |
T7 |
150326 |
150322 |
0 |
0 |
T8 |
52239 |
52235 |
0 |
0 |
T15 |
124287 |
124283 |
0 |
0 |
T20 |
0 |
6 |
0 |
0 |
T26 |
0 |
10 |
0 |
0 |
T27 |
0 |
10 |
0 |
0 |
T29 |
0 |
20 |
0 |
0 |
T32 |
2 |
0 |
0 |
0 |
T33 |
0 |
6 |
0 |
0 |
T34 |
3757 |
3753 |
0 |
0 |
T71 |
2 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T82 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T82 |
1 | 1 | Covered | T82 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T82 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
2238692 |
2238431 |
0 |
0 |
selKnown1 |
49296285 |
49296024 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2238692 |
2238431 |
0 |
0 |
T1 |
118 |
117 |
0 |
0 |
T2 |
120 |
119 |
0 |
0 |
T3 |
1863 |
1862 |
0 |
0 |
T4 |
1335 |
1334 |
0 |
0 |
T5 |
7350 |
7349 |
0 |
0 |
T6 |
7474 |
7473 |
0 |
0 |
T7 |
5734 |
5733 |
0 |
0 |
T8 |
5816 |
5815 |
0 |
0 |
T15 |
8928 |
8927 |
0 |
0 |
T34 |
118 |
117 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
49296285 |
49296024 |
0 |
0 |
T1 |
3566 |
3565 |
0 |
0 |
T2 |
1949 |
1948 |
0 |
0 |
T3 |
96385 |
96384 |
0 |
0 |
T4 |
34974 |
34973 |
0 |
0 |
T5 |
238528 |
238527 |
0 |
0 |
T6 |
37055 |
37054 |
0 |
0 |
T7 |
144584 |
144583 |
0 |
0 |
T8 |
46421 |
46420 |
0 |
0 |
T15 |
115353 |
115352 |
0 |
0 |
T34 |
3637 |
3636 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T82 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T82 |
1 | 1 | Covered | T82 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T82 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
794 |
533 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
4 |
3 |
0 |
0 |
T6 |
7 |
6 |
0 |
0 |
T7 |
4 |
3 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T15 |
3 |
2 |
0 |
0 |
T20 |
0 |
3 |
0 |
0 |
T26 |
0 |
5 |
0 |
0 |
T27 |
0 |
5 |
0 |
0 |
T29 |
0 |
10 |
0 |
0 |
T32 |
1 |
0 |
0 |
0 |
T33 |
0 |
4 |
0 |
0 |
T34 |
1 |
0 |
0 |
0 |
T71 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
752 |
491 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
4 |
3 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
4 |
3 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T15 |
3 |
2 |
0 |
0 |
T20 |
0 |
3 |
0 |
0 |
T26 |
0 |
5 |
0 |
0 |
T27 |
0 |
5 |
0 |
0 |
T29 |
0 |
10 |
0 |
0 |
T32 |
1 |
0 |
0 |
0 |
T33 |
0 |
3 |
0 |
0 |
T34 |
1 |
0 |
0 |
0 |
T71 |
1 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T82 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T82 |
1 | 1 | Covered | T82 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T82 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
5218004 |
5217523 |
0 |
0 |
selKnown1 |
5218004 |
5217523 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
5218004 |
5217523 |
0 |
0 |
T1 |
118 |
117 |
0 |
0 |
T2 |
120 |
119 |
0 |
0 |
T3 |
1863 |
1862 |
0 |
0 |
T4 |
1335 |
1334 |
0 |
0 |
T5 |
7350 |
7349 |
0 |
0 |
T6 |
7474 |
7473 |
0 |
0 |
T7 |
5734 |
5733 |
0 |
0 |
T8 |
5816 |
5815 |
0 |
0 |
T15 |
8928 |
8927 |
0 |
0 |
T34 |
118 |
117 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
5218004 |
5217523 |
0 |
0 |
T1 |
118 |
117 |
0 |
0 |
T2 |
120 |
119 |
0 |
0 |
T3 |
1863 |
1862 |
0 |
0 |
T4 |
1335 |
1334 |
0 |
0 |
T5 |
7350 |
7349 |
0 |
0 |
T6 |
7474 |
7473 |
0 |
0 |
T7 |
5734 |
5733 |
0 |
0 |
T8 |
5816 |
5815 |
0 |
0 |
T15 |
8928 |
8927 |
0 |
0 |
T34 |
118 |
117 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T82 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T82 |
1 | 1 | Covered | T82 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T82 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
1810 |
1329 |
0 |
0 |
selKnown1 |
1753 |
1272 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1810 |
1329 |
0 |
0 |
T3 |
5 |
4 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
6 |
5 |
0 |
0 |
T6 |
9 |
8 |
0 |
0 |
T7 |
4 |
3 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T15 |
3 |
2 |
0 |
0 |
T20 |
0 |
3 |
0 |
0 |
T26 |
0 |
5 |
0 |
0 |
T27 |
0 |
8 |
0 |
0 |
T29 |
0 |
10 |
0 |
0 |
T32 |
1 |
0 |
0 |
0 |
T33 |
0 |
5 |
0 |
0 |
T34 |
1 |
0 |
0 |
0 |
T71 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1753 |
1272 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
4 |
3 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
4 |
3 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T15 |
3 |
2 |
0 |
0 |
T20 |
0 |
3 |
0 |
0 |
T26 |
0 |
5 |
0 |
0 |
T27 |
0 |
5 |
0 |
0 |
T29 |
0 |
10 |
0 |
0 |
T32 |
1 |
0 |
0 |
0 |
T33 |
0 |
3 |
0 |
0 |
T34 |
1 |
0 |
0 |
0 |
T71 |
1 |
0 |
0 |
0 |